JP2003218849A - Burst data reception system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a burst data reception system that receives burst data from each slave station without decreasing a main signal transmission rate even if there is no reception phase information, and at the same time can reduce the size of a circuit. <P>SOLUTION: A 1/2 dividing section 11 where reception burst data (a) are inputted subjects an RZ code arranged in a training bit to 1/2 division and outputs a 1/2 divided signal (h). A pattern detection section 12 detects a unique pattern from the 1/2 divided signal (h) for outputting a pattern detection signal (i). An ID pattern detection section 13 detects an ID pattern that becomes the identifier of a plurality of slave stations from the reception burst data (a) with the pattern detection signal (i) as a trigger and outputs an ID pattern detection result (k). A terminating end 5 terminates the reception burst data (a) based on a timing pulse (c) from a reception counter 6 and the ID pattern detection signal (i) from the ID pattern detection section 13. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst data receiving system.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an outline of a conventional burst data receiving system and a structure of a transmission frame. In the conventional burst data receiving system, as shown in FIG. 3, one master station 30 and a plurality of slave stations 31-1 to 31-1 are connected.
n is connected via a star coupler 32, and bidirectional transmission is performed between the master station 30 and the plurality of slave stations 31-1 to 31-n.

In the burst frame on the transmission path, as shown in FIG. 3, downlink burst data from the master station 30 to a plurality of slave stations 31-1 to 31-n is provided in a period of about 1/3 of the first half of one transmission frame period. That is, the upstream burst data from the plurality of slave stations 31-1 to 31-n is passively multiplexed in about 1/3 of the latter half of the transmission frame period.

FIG. 4 is a block diagram showing the structure of upstream burst data. In the upstream burst data, in order to identify the end of the burst frame and the beginning of each burst frame on the master station side, as shown in FIG. 4, training bits and synchronization patterns are arranged at the beginning of each upstream burst data. Has been done. The training bit raises the ATC to an optimum value when the master station receives the optical burst data, and also controls the digital PLL (hereinafter referred to as the digital PLL that controls the clock on the master station side device so that the phase matches the received data bit string. , "D-PLL"). A unique pattern is inserted in the synchronization pattern to indicate the beginning of the burst, and the main station side can process the main signal of subsequent data by detecting the main synchronization pattern.

FIG. 5 is a block diagram showing the structure of a conventional burst data receiving system in the master station. As shown in FIG. 5, the conventional burst data reception method includes a synchronization pattern detection unit 1 that detects a first synchronization pattern detection pulse from received burst data, and a first synchronization pattern detection pulse from a second synchronization pattern detection pulse according to a window pulse. , A window control unit 2 for detecting a synchronization pattern detection pulse, an in-device clock source 3 for transmitting an in-device clock, and a phase control of the in-device clock according to the phase of the received burst data to generate an optimum clock D A PLL unit 4, a terminating unit 5 for terminating the received burst data, a reception counter 6 for generating a timing pulse for driving the terminating unit 5 from a clock output from the D-PLL unit 4, and one transmission line frame period. A frame counter 7 for managing downlink burst data transmission timing and uplink burst data reception timing A communication capacity information unit 8 having communication capacity information for a slave station, a reception phase information unit 9 having a reception phase expected value for each slave station, and a transmission unit for transmitting downlink burst data based on an instruction from the frame counter 7. And 10.

Next, the operation of the conventional burst data receiving system shown in FIG. 5 will be described with reference to the time chart of FIG. Received burst data a input to the master station
Is input to the D-PLL unit 4 and the synchronization pattern detection unit 1.
The D-PLL unit 4 phase-controls the in-device clock output from the in-device clock source 3 in accordance with the phase of the received burst data a to generate an optimum clock e, and the synchronization pattern detection unit 1 and the reception counter. Output to 6. Further, the synchronization pattern detection unit 1 detects the first synchronization pattern detection pulse b1 from the received burst data a and sends it to the window control unit 2.

The frame counter 7 manages one transmission path frame period and manages downlink burst data transmission timing and uplink burst data reception timing. In the downlink burst data area, each slave station from the communication capacity information section 8 is managed. The communication unit 10 refers to the communication capacity information for the transmission unit 10 to time-division-multiplex the main signal to each slave station for each allocated communication capacity.
To control. Further, in the upstream burst data area, the reception phase expected value for each slave station from the reception phase information unit 9 is referred to,
The window pulse d is output to the window control unit 2.
The first sync pattern detection pulse b1 output from the sync pattern detection unit 1 is the same as the sync pattern accidentally included in the main signal, together with the detection result of the sync pattern arranged at the beginning of the original burst data. The detection result by is included. Therefore, the frame counter 7 obtains the upstream burst data reception expected phase information for each slave station, and generates the window pulse d aiming at a regular synchronization pattern (probable place) from this reception phase expected information.

The window control unit 2 detects the sync pattern among the first sync pattern detection pulses b1 output from the sync pattern detection unit 1 only when the window pulse d from the frame counter 7 is in a significant state. The second synchronization pattern detection pulse b2 is masked by unnecessary synchronization patterns.
As a result, it is sent to the reception counter 6 and the terminal unit 5.

The reception counter 6 receives the second sync pattern detection pulse b2 and DP which are output from the window controller 2.
The clock e output from the LL unit 4 is input, the timing pulse c is generated, and the terminal unit 5 is driven.

The terminating unit 5 terminates the received burst data a with the second synchronization pattern detection pulse b2 and the timing pulse c.

[0011]

In the above-mentioned conventional burst data receiving system, the reception phase information section 9 is provided by the number of slave stations.
Is required, the complexity of the processing of the frame counter 7 for generating the window pulse d while referring to the reception abnormality information, and further the processing of the parameter setting signal g for setting the reception phase information section 9 is performed. There is a problem that the circuit scale becomes large due to such factors.

The present invention has been made in view of the above problems. The present invention receives burst data from each slave station without lowering the main signal transmission efficiency without receiving phase information. It is an object of the present invention to provide a burst data receiving method capable of reducing the circuit scale.

[0013]

The invention according to claim 1 is
In a burst data receiving method having a training bit at the head, an RZ code is arranged in the training bit, and a bit string obtained by dividing the RZ code by ½ is used as a unique pattern for identifying the head of the burst. It is characterized by being used.

According to a second aspect of the present invention, in a burst data receiving system in which bidirectional transmission of burst data is performed between a master station and a plurality of slave stations, burst data in which an RZ code is arranged in the head training bit And 1/2 dividing means for generating a 1/2 divided signal, and a pattern detecting means for detecting a toggle pattern as a unique pattern from the 1/2 divided signal and outputting a pattern detection signal. An ID pattern detecting means for detecting an ID pattern serving as an identifier of a plurality of slave stations from the burst data and outputting an ID pattern detection result signal by using the pattern detection signal as a trigger; and a clock source for generating an in-device clock. And phase synchronization control means for generating an appropriate clock from the internal clock so as to follow the bit phase of the burst data, and assigning to each slave station Communication capacity information means for externally receiving and storing communication capacity information indicating the communication capacity, and a timing pulse for terminating burst data by receiving the ID pattern detection result signal as a trigger based on the communication capacity information. , A terminating means for terminating the burst data based on the timing pulse and the ID pattern detection result signal, downlink burst data transmission timing and uplink burst data reception timing by managing one transmission line frame period. And a transmission means for transmitting downlink burst data based on an instruction from the frame counter.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment relating to the burst data receiving system of the present invention. The burst data receiving method according to the present embodiment is a 1/2 frequency division section that generates 1/2 frequency division signal h by dividing the burst data a in which the RZ code is arranged in the middle of the head training bit by 1/2. 11 and 1/2 divided signal h
A pattern detection unit 12 that detects a toggle pattern as a unique pattern from the above and outputs a unique pattern detection signal i;
Burst data a triggered by the unique pattern detection signal i
ID pattern detection unit 13 that detects an ID pattern serving as an identifier of a plurality of slave stations and outputs an ID pattern detection result signal k, an internal clock source 3 that generates an internal clock, and burst data a. A D-PLL (digital PL) that generates an appropriate clock e from the internal clock so as to follow the bit phase of the burst data a by input
L) section 4, a communication capacity information section 8 for inputting the parameter setting signal g and accumulating communication capacity information allocated to each slave station, and an ID based on the communication capacity information of the communication capacity information section 8.
A reception counter 6 that outputs a timing pulse c for terminating the received burst data triggered by the pattern detection result signal k, a timing pulse c from the reception counter 6, and an ID pattern detection result signal k from the ID pattern detection unit 13. Termination unit 5 for terminating burst data a based on
A frame counter 7 that manages one transmission frame period and manages downlink burst data transmission timing and uplink burst data reception timing; and a transmission unit 10 that transmits downlink burst data based on an instruction from the frame counter 7. Consists of.

Next, the operation of this embodiment will be described in detail with reference to the drawings. FIG. 2 is a time chart diagram showing the operation of the present embodiment. As shown in FIG. 2, RZ is provided in the middle of the training bit at the beginning of the upstream burst data.
Codes (bits that change from "H" to "L" at 50% of the bit width) are arranged, and the ID of the slave station is assigned instead of the synchronization pattern in the conventional technique. In FIG. 1, the input burst data a is divided by 1 in the 1/2 frequency divider 11.
The frequency is divided by two and input to the pattern detection unit 12.

The 1/2 frequency-divided signal h has a pattern in which only the RZ code area is toggled in bit units as shown in h of FIG. 2 and does not appear in the area other than the RZ code. It can be a unique pattern. In FIG. 2, as an example, X: Do is used as the unique pattern detection condition.
n't Care, T: toggle from the previous bit, N: the same value as the previous bit, and the pattern "TTTN" is a unique pattern. 1/2 in pattern detection unit 12
The above-mentioned unique pattern is detected from the frequency-divided signal h, and the unique pattern detection signal i is output to the ID pattern detection unit 13.

The ID pattern detection unit 13 detects the ID pattern from the burst data a triggered by the unique pattern detection signal i and outputs the ID pattern detection result signal k to the terminal unit 5 and the reception counter 6.

As described above, in the present embodiment, the RZ code is arranged in the training bit, and the bit string obtained by dividing the RZ code by ½ is detected to identify the head of the burst. Therefore, even if there is no upstream burst data reception phase information in advance, the head of the burst and the slave station ID can be extracted from the data string of the repeatedly input burst data a to terminate the data.

[0020]

As described above, in the present invention, burst data can be received from each slave station without lowering the main signal transmission efficiency without receiving phase information.
In addition, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment relating to a burst data receiving system of the present invention.

FIG. 2 is a time chart diagram showing the operation of the present embodiment.

FIG. 3 is a block diagram showing an outline of a conventional burst data receiving system and a configuration of a transmission frame.

FIG. 4 is an explanatory diagram showing a structure of conventional upstream burst data.

FIG. 5 is a block diagram showing a configuration of a conventional burst data receiving system.

FIG. 6 is a time chart showing the operation of a conventional burst data receiving system.

[Explanation of symbols]

1 Synchronous pattern detector 2 Window control unit 3 Internal clock source 4 Digital PLL section 5 Terminal 6 Reception counter 7 frame counter 8 Communication capacity information section 9 Reception phase information section 10 Transmitter 11 1/2 frequency division 12 Unique pattern detector 13 ID pattern detector 30 parent station 31-1 to n slave station 32 star coupler Received burst data b1 First synchronization pattern detection pulse b2 Second synchronization pattern detection pulse c Timing pulse d window pulse e Internal device clock g Parameter setting signal h 1/2 divided signal i Unique pattern detection signal k ID pattern detection result signal

Claims (2)

[Claims] 1. In a burst data receiving method having a training bit at the head, an RZ code is arranged in the training bit, and a bit string obtained by dividing the RZ code by 1/2 is used to identify the head of the burst. Burst data receiving method characterized by being used as a unique pattern for 2. In a burst data receiving method in which bidirectional transmission of burst data is performed between a master station and a plurality of slave stations, burst data in which an RZ code is placed in the head training bit is divided by 1/2. A 1/2 frequency dividing means for generating a 1/2 frequency divided signal, a pattern detecting means for detecting a toggle pattern as a unique pattern from the 1/2 frequency divided signal and outputting a pattern detection signal, and the pattern detecting signal Is used as a trigger to detect an ID pattern serving as an identifier of a plurality of slave stations in the burst data and output an ID pattern detection result signal, a clock source for generating an in-device clock, and the burst data of the burst data. Phase synchronization control means for generating an appropriate clock from the internal clock so as to follow the bit phase, and a communication indicating the communication capacity assigned to each slave station. Communication capacity information means for receiving and accumulating signal capacity information from the outside, and a reception counter for receiving a timing pulse for terminating burst data by receiving the ID pattern detection result signal as a trigger based on the communication capacity information A terminating means for terminating the burst data on the basis of the timing pulse and the ID pattern detection result signal; and a frame counter for managing one burst path frame period to manage a downstream burst data transmission timing and an upstream burst data reception timing. A burst data receiving method, comprising: a transmitting unit that transmits downlink burst data based on an instruction from the frame counter.