JP2003218154A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2003218154A JP2003218154A JP2002018482A JP2002018482A JP2003218154A JP 2003218154 A JP2003218154 A JP 2003218154A JP 2002018482 A JP2002018482 A JP 2002018482A JP 2002018482 A JP2002018482 A JP 2002018482A JP 2003218154 A JP2003218154 A JP 2003218154A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- pad
- bonding
- semiconductor device
- inner lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/78—Apparatus for connecting with wire connectors
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- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H01L2224/7865—Means for transporting the components to be connected
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
半導体製造装置に関し、特にボンディングワイヤを自由
に引き回されるようにした半導体装置および半導体製造
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor manufacturing apparatus, and more particularly to a semiconductor device and a semiconductor manufacturing apparatus in which a bonding wire can be freely routed.
【０００２】[0002]
【従来の技術】従来の半導体装置におけるワイヤボンデ
ィングにおいては、半導体チップのパッドとインナリー
ドを連結するボンディングワイヤが、パッドとインナリ
ードとを結ぶ概ね直線上に配置されて連結されたものが
多いが、特開２０００−２１６１８８号公報（以下従来
例という）では、そのワイヤを自由に引き回して配置す
るワイヤボンディング方法が示されている。2. Description of the Related Art In conventional wire bonding in a semiconductor device, a bonding wire connecting a pad of a semiconductor chip and an inner lead is generally arranged and connected on a substantially straight line connecting the pad and the inner lead. Japanese Patent Laid-Open No. 2000-216188 (hereinafter referred to as a conventional example) discloses a wire bonding method in which the wire is freely routed and arranged.
【０００３】図６はこの従来例を説明する半導体装置の
部分平面図である。すなわち、このワイヤボンディング
方法は、仮想直線Ｌ１上で一列に並んだ複数の電極（パ
ッド）３を有する半導体チップ１の周囲に、仮想平面Ｐ
上に並べられた複数のリード４を、電極３の中心点間距
離よりもリード４の中心点間距離を広くして配置する第
１工程と、一対の電極３及び一つのリード４の一方に、
ワイヤ５をボンディングする第２工程と、仮想平面に対
して垂直な方向の平面視において、一対をなす一つの電
極及び一つのリードの他方に向けて、ワイヤ５をピン４
０を介して屈曲させる第３工程と、一対電極及び一つの
リードの他方に、ワイヤ５をボンディングする第４工程
とを含む方法である。FIG. 6 is a partial plan view of a semiconductor device for explaining this conventional example. That is, in this wire bonding method, the virtual plane P is formed around the semiconductor chip 1 having the plurality of electrodes (pads) 3 arranged in a line on the virtual straight line L1.
The first step of arranging the plurality of leads 4 arranged above with the distance between the center points of the leads 4 wider than the distance between the center points of the electrodes 3 and one of the pair of electrodes 3 and one lead 4 ,
In the second step of bonding the wire 5 and in plan view in a direction perpendicular to the virtual plane, the wire 5 is pinned toward the other of the pair of one electrode and one lead.
It is a method including a third step of bending through 0 and a fourth step of bonding the wire 5 to the other of the pair of electrodes and the one lead.
【０００４】このワイヤ５を引き出して電極３とリード
４を接続するボンディングツールは、ボンディングヘッ
ドやワイヤークランプ等を含み、ワイヤ５を屈曲させる
ために、仮想平面Ｐに対して垂直な方向の平面において
非直線的に移動する。このワイヤ５を屈曲させるときに
は、ワイヤ５が必要な長さに至るまで電極３から真っ直
ぐにボンディングツールを移動させ、ピン４０の廻りで
弧を描くようにして、ワイヤ５を屈曲させたり、あるい
は屈曲位置までボンディングツールを真っ直ぐに移動さ
せ、ピン４０の廻りを廻りながらかつピン４０からボン
ディングツールを遠ざけて、ワイヤ５を屈曲させてもよ
い。The bonding tool for pulling out the wire 5 to connect the electrode 3 and the lead 4 includes a bonding head, a wire clamp, etc., and in order to bend the wire 5, in a plane perpendicular to the virtual plane P. Move non-linearly. When the wire 5 is bent, the bonding tool is moved straight from the electrode 3 until the wire 5 reaches a required length, and the wire 5 is bent or bent by drawing an arc around the pin 40. The wire 5 may be bent by moving the bonding tool straight to the position and moving the bonding tool away from the pin 40 while rotating around the pin 40.
【０００５】このピン４０は、ワイヤ５を屈曲させるた
めに使用され、また、ピン４０は、いずれかのワイヤ５
のボンディングを行って、次のワイヤ５のボンディング
を行う時に、移動するが、このピン４０にはアームが設
けられ、アームが駆動されることでピン４０が移動す
る。アームはテーブル上における半導体チップ１を載置
する面またはその反対側に配置される。この場合、ピン
４０の移動する軌跡に沿って、テーブルに溝を形成して
もよく、また、半導体チップ１が配置される側に、ピン
４０を支持するアームを設けてもよい。The pin 40 is used to bend the wire 5, and the pin 40 is used for any one of the wires 5.
The pin 40 is provided with an arm, and the pin 40 is moved when the arm is driven. The arm is arranged on the surface of the table on which the semiconductor chip 1 is mounted or on the opposite side. In this case, a groove may be formed in the table along the trajectory of the pin 40, and an arm for supporting the pin 40 may be provided on the side where the semiconductor chip 1 is arranged.
【０００６】[0006]
【発明が解決しようとする課題】しかし、この従来例で
も、半導体装置のパッケージのチップ１のパッド３とリ
ード４とからのボンディングワイヤが、それぞれパッド
３またはリード４に沿った直線から平行に取り出され
て、そのワイヤ５の途中で屈曲されており、そのためパ
ッド３とリード４との間に隙間を必要とするので、半導
体装置のパッケージそのものが大きくなってしまうとい
う問題がある。However, also in this conventional example, the bonding wires from the pad 3 and the lead 4 of the chip 1 of the semiconductor device package are taken out in parallel from the straight line along the pad 3 or the lead 4, respectively. In addition, since the wire 5 is bent in the middle thereof, and a gap is required between the pad 3 and the lead 4, the package of the semiconductor device itself becomes large.
【０００７】また、この従来例では、ワイヤ５を屈曲さ
せるためのピン４０が、半導体チップ１を載置するテー
ブルにアームが配置されているため、アームの位置決め
をするための駆動が複雑になるという問題もある。Further, in this conventional example, since the pin 40 for bending the wire 5 is arranged on the table on which the semiconductor chip 1 is mounted, the driving for positioning the arm becomes complicated. There is also a problem.
【０００８】本発明の主な目的は、このような問題を解
決し、ボンディングによる結線の自由度を向上させ、チ
ップを多数搭載するパッケージでもボンディングが自由
に出来るようにすると共に、その製造時のボンディング
加工を容易にした半導体装置およびその製造装置装置を
提供することにある。The main object of the present invention is to solve such a problem, improve the degree of freedom of connection by bonding, and make it possible to perform bonding freely even in a package having a large number of chips mounted thereon. It is an object of the present invention to provide a semiconductor device that facilitates bonding and a device for manufacturing the same.
【０００９】[0009]
【課題を解決するための手段】本発明の構成は、半導体
チップのパッドとインナリードを連結するボンディング
ワイヤを有する半導体装置において、前記ボンディング
ワイヤが、前記パッドと前記インナリードとが屈曲さ
れ、これらパッドとインナリードとを結ぶ概ね直線上に
配置されないようにして連結されたことを特徴とする。According to the structure of the present invention, in a semiconductor device having a bonding wire for connecting a pad of a semiconductor chip and an inner lead, the bonding wire is bent at the pad and the inner lead, It is characterized in that the pads and the inner leads are connected so as not to be arranged on a substantially straight line connecting them.
【００１０】本発明において、ボンディングワイヤが、
パッドとインナリードとを結ぶ概ね直線上の少なくとも
一箇所で平面的に屈曲点を有するようにできる。In the present invention, the bonding wire is
It is possible to have a bending point in a plane at least at one position on a substantially straight line connecting the pad and the inner lead.
【００１１】また、本発明の半導体製造装置の構成は、
半導体装置のワイヤボンダでワイヤリングする機構とは
別の個所にワイヤをクランプするクランプ手段と、前記
ワイヤに平面的な屈曲点を有するよう加工するキャピラ
リとを有することを特徴とする。The structure of the semiconductor manufacturing apparatus of the present invention is as follows:
It is characterized in that it has a clamping means for clamping the wire at a position different from the mechanism for wiring with the wire bonder of the semiconductor device, and a capillary for processing the wire so as to have a planar bending point.
【００１２】本発明において、クランプ手段が、ワイヤ
ボンダのキャピラリの下方に上下動作と回転動作を行え
るようにした治具からなり、前記キャピラリが、ワイヤ
リングの途中でワイヤの方向を平面的に変え、屈曲点を
少なくとも一箇所形成できるものからなることができ、
また、クランプ手段内に、加工手段が配置されるように
でき、さらに、クランプ手段が、中央に加工手段を配置
し外周にワイヤを通す一部切欠き部を有し回転可能な回
転治具からなることができる。In the present invention, the clamping means comprises a jig that can be moved up and down and rotated below the capillary of the wire bonder, and the capillary changes the direction of the wire in the middle of the wiring and bends the wire. Can be made up of at least one point,
Further, the processing means can be arranged in the clamp means, and further, the clamp means is provided with the processing means in the center and has a partial cutout portion for passing the wire on the outer periphery, and is made from a rotatable jig. Can be
【００１３】[0013]
【発明の実施の形態】次に図面により本発明の実施形態
を説明する。図１は本発明の一実施形態を説明する半導
体装置の正面図である。本実施形態は、アイランド２上
に半導体チップ１が形成され、この半導体チップ１上の
パッド３からリード４にワイヤ５が接続されている。こ
のボンディングされたワイヤ５は、その屈曲部でクラン
パ１１にクランプされたのち、キャピラリ１０が直線方
向から所定の方向へ向きを変え、リード４にボンディン
グされるまでクランプしておく。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a front view of a semiconductor device according to an embodiment of the present invention. In this embodiment, the semiconductor chip 1 is formed on the island 2, and the wire 5 is connected to the lead 4 from the pad 3 on the semiconductor chip 1. This bonded wire 5 is clamped by the clamper 11 at its bent portion, and then the capillary 10 is turned from the linear direction to a predetermined direction and clamped until it is bonded to the lead 4.
【００１４】このキャピラリ１０は、上下左右の動作を
別の機構部により行うが、クランパ１１も上下左右動作
ならびに開閉動作をキャピラリ１０とは別の機構部によ
り行うが、いずれもワイヤボンダ側で駆動される。The capillary 10 performs up / down / left / right movements by separate mechanical portions, and the clamper 11 also performs up / down / left / right movements and opening / closing operations by different mechanical portions from the capillary 10. Both are driven by the wire bonder side. It
【００１５】図２（ａ）（ｂ）は本発明の実施形態を説
明するワイヤリング実施の場合の平面図である。図２
（ａ）はアイランド２上に一個のチップのパッドからリ
ードを結ぶ直線から外れた個所に屈曲点を持って連結す
る場合、図２（ｂ）はアイランド２上に複数個のチップ
１ａ，１ｂのパッド３からリード４へ結んだワイヤリン
グの場合の形状を示す平面図である。2 (a) and 2 (b) are plan views in the case of carrying out the wiring for explaining the embodiment of the present invention. Figure 2
2A shows a case in which a plurality of chips 1a and 1b on the island 2 are connected to each other with a bending point at a position deviating from the straight line connecting the leads from the pad of one chip on the island 2. FIG. FIG. 6 is a plan view showing a shape in the case of wiring connected from the pad 3 to the lead 4.
【００１６】図３は本発明の実施形態を説明する半導体
製造装置の平面図である。この半導体製造装置は、製造
すべき半導体装置のチップ１ａを供給する供給部２１
と、供給されたチップ１ａを処理しながら搬送する搬送
部２０と、搬送部２０からのチップ１ａを収納する収納
部２２とから構成される。FIG. 3 is a plan view of a semiconductor manufacturing apparatus for explaining an embodiment of the present invention. This semiconductor manufacturing apparatus includes a supply unit 21 for supplying a chip 1a of the semiconductor device to be manufactured.
And a carrying section 20 for carrying the supplied chip 1a while processing it, and a housing section 22 for housing the chip 1a from the carrying section 20.
【００１７】この供給部２１より供給された半導体装置
のチップ１ａは、搬送部２０と、上下左右に動く機構部
を有するボンディングヘッド２４と、このボンディング
ヘッド２４と同様に動作するクランパ１１のクランパヘ
ッド２３を持つ機構部により屈曲点を有するワイヤボン
ディングを行う。このボンディングの終了後、収納部２
２へ収納される。The semiconductor device chip 1a supplied from the supply unit 21 includes a carrier unit 20, a bonding head 24 having a mechanism unit that moves vertically and horizontally, and a clamper head of a clamper 11 that operates similarly to the bonding head 24. Wire bonding having a bending point is performed by a mechanism portion having 23. After completion of this bonding, the storage unit 2
It is stored in 2.
【００１８】図４（ａ）（ｂ）は本発明の第二の実施形
態を示す半導体装置の加工時の断面図およびその回転治
具の裏面図である。本実施形態は、クランパ１１の代り
に、切り欠き部１４を有する回転治具１３を用いてい
る。第一の実施例と同様に、チップ１のパッド３から引
き出されたボンディングワイヤ５は、リード４の方向へ
結線していくが、この場合、チップ１のパッド３をボン
ディングする時には、キャピラリ１０が下がり、回転治
具１３は上方へ退避している。FIGS. 4 (a) and 4 (b) are a cross-sectional view of a semiconductor device during processing and a rear view of a rotating jig thereof, showing a second embodiment of the present invention. In this embodiment, instead of the clamper 11, a rotary jig 13 having a cutout portion 14 is used. Similar to the first embodiment, the bonding wire 5 pulled out from the pad 3 of the chip 1 is connected in the direction of the lead 4. In this case, when the pad 3 of the chip 1 is bonded, the capillary 10 is The rotary jig 13 is lowered and retracted upward.
【００１９】この回転治具１３は、図４（ｂ）の平面図
に示すように、パッド３をボンディングし途中まで結線
したとき回転治具１３が下がり、回転治具の切り欠き部
１４にワイヤ５を挟み回転してワイヤの方向を変更す
る。このときワイヤ５に塑性変形を起こさせる。その後
リードボンディングを行う。As shown in the plan view of FIG. 4B, the rotary jig 13 is lowered when the pad 3 is bonded and connected halfway, and the wire is placed in the notch portion 14 of the rotary jig. Rotate with 5 in between to change the direction of the wire. At this time, the wire 5 is plastically deformed. After that, lead bonding is performed.
【００２０】図５は本発明の第二の実施形態を説明する
半導体製造装置のボンダの平面図である。本実施形態
は、ボンディングヘッド２４ａが、切り欠き部１４をも
つ回転治具１３であるので、その切り欠き部１４がクラ
ンパヘッド２３の役割をしており、１個のヘッドでよく
簡単化された機構となっている。FIG. 5 is a plan view of a bonder of a semiconductor manufacturing apparatus for explaining a second embodiment of the present invention. In the present embodiment, since the bonding head 24a is the rotary jig 13 having the cutout portion 14, the cutout portion 14 functions as the clamper head 23, which is simplified by one head. It is a mechanism.
【００２１】[0021]
【発明の効果】以上説明したように本発明の構成によれ
ば、ボンディングワイヤを結線の途中の任意の箇所で変
形させ、パッドとリードの一直線上から離れる方向に結
線することにより、ボンディングによる結線の自由度が
向上し、チップを多数搭載するパッケージでもボンディ
ングが自由に出来るという効果がある。As described above, according to the structure of the present invention, the bonding wire is deformed at an arbitrary position on the way of connection, and is connected in a direction away from the straight line of the pad and the lead, thereby connecting by bonding. The degree of freedom is improved, and there is an effect that bonding can be freely performed even in a package mounting a large number of chips.
【００２２】また、ワイヤボンディング装置側にクラン
パが設けられているので、キャピラリの動作に合わせた
動作が可能となり、ワイヤボンディング装置の構成が容
易に出来るという効果もある。Further, since the clamper is provided on the side of the wire bonding apparatus, it is possible to operate in accordance with the operation of the capillaries, and the wire bonding apparatus can be easily constructed.
【図１】本発明の第１の実施形態を説明する半導体装置
の部分断面図。FIG. 1 is a partial cross-sectional view of a semiconductor device illustrating a first embodiment of the present invention.
【図２】（ａ）（ｂ）は図１の平面図てあり、チップが
１個の場合および複数のチップの場合を示す。2 (a) and 2 (b) are plan views of FIG. 1, showing a case of one chip and a case of a plurality of chips.
【図３】第１の実施形態を製造する半導体製造装置の模
式的平面図。FIG. 3 is a schematic plan view of a semiconductor manufacturing apparatus that manufactures the first embodiment.
【図４】（ａ）（ｂ）は本発明の第２の実施形態を説明
する半導体装置の部分断面図およびそのクランパ部分の
平面図。4A and 4B are a partial cross-sectional view of a semiconductor device and a plan view of a clamper portion thereof for explaining a second embodiment of the present invention.
【図５】第２の実施形態を製造する半導体製造装置の模
式的平面図。FIG. 5 is a schematic plan view of a semiconductor manufacturing apparatus that manufactures a second embodiment.
【図６】従来例の半導体装置を説明する平面図。FIG. 6 is a plan view illustrating a conventional semiconductor device.
【符号の説明】 １，１ａ，１ｂ 半導体チップ ２ アイランド ３ パッド ４ リード ５ ワイヤ １０ キャピラリ １１ クランパ １３ 回転治具 １４ 回転治具切欠き部 ２０ 搬送部 ２１ 供給部 ２２ 収納部 ２３ クランパヘッド ２４，２４ａ ボンディングヘッド ４０ ピン[Explanation of symbols] 1,1a, 1b Semiconductor chip 2 islands 3 pads 4 leads 5 wires 10 capillaries 11 clamper 13 Rotating jig 14 Rotating jig notch 20 Transport section 21 Supply Department 22 Storage 23 Clamper head 24, 24a Bonding head 40 pin
Claims (6)
連結するボンディングワイヤを有する半導体装置におい
て、前記ボンディングワイヤが、前記パッドと前記イン
ナリードとが任意の箇所で屈曲され、これらパッドとイ
ンナリードとを結ぶ直線上に配置されないように連結さ
れたことを特徴とする半導体装置。1. A semiconductor device having a bonding wire connecting a pad of a semiconductor chip and an inner lead, wherein the bonding wire is bent at an arbitrary position between the pad and the inner lead, and the pad and the inner lead are connected to each other. A semiconductor device, which is connected so as not to be arranged on a straight line.
リードとを結ぶ概ね直線上の少なくとも一箇所で平面的
に屈曲点を有するようにした請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the bonding wire has a bending point in a plane at least at one position on a substantially straight line connecting the pad and the inner lead.
グする機構とは別の個所にワイヤをクランプするクラン
プ手段と、前記ワイヤに平面的な屈曲点を有するよう加
工するキャピラリとを有することを特徴とする半導体製
造装置。3. A semiconductor comprising: a clamp means for clamping the wire at a position different from a mechanism for wiring with a wire bonder of the semiconductor device; and a capillary for processing the wire so as to have a planar bending point. Manufacturing equipment.
ラリの下方に上下動作と回転動作を行えるようにした治
具からなり、前記キャピラリが、ワイヤリングの途中で
ワイヤの方向を平面的に変え、屈曲点を少なくとも一箇
所形成できるようにしたものからなる請求項３記載の半
導体製造装置。4. The clamp means is composed of a jig capable of performing a vertical movement and a rotation operation below a capillary of a wire bonder, and the capillary changes the direction of the wire two-dimensionally in the middle of the wiring and changes the bending point. The semiconductor manufacturing apparatus according to claim 3, which is formed so as to be formed at at least one place.
され、ワイヤリングと同時にクランプされるようにした
請求項３または４記載の半導体製造装置。5. The semiconductor manufacturing apparatus according to claim 3, wherein a capillary is arranged at the center of the clamp means and clamped simultaneously with the wiring.
し外周にワイヤを通す一部切欠き部を有し、かつ回転可
能な回転治具からなる請求項５記載の半導体製造装置。6. The semiconductor manufacturing apparatus according to claim 5, wherein the clamping means is a rotatable jig having a machining means arranged at the center and a partially cutout portion through which a wire is passed through the outer circumference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002018482A JP2003218154A (en) | 2002-01-28 | 2002-01-28 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002018482A JP2003218154A (en) | 2002-01-28 | 2002-01-28 | Semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003218154A true JP2003218154A (en) | 2003-07-31 |
Family
ID=27653813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002018482A Pending JP2003218154A (en) | 2002-01-28 | 2002-01-28 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003218154A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007073937A (en) * | 2005-08-12 | 2007-03-22 | Kaijo Corp | Loop shape of bonding wire, semiconductor device comprising the same and bonding method |
| JP2007194470A (en) * | 2006-01-20 | 2007-08-02 | Kaijo Corp | Loop shape of bonding wire and semiconductor device having the loop shape, and bonding method |
| JP2007208148A (en) * | 2006-02-03 | 2007-08-16 | Ail Kk | Semiconductor chip mounted substrate |
| JP2009071046A (en) * | 2007-09-13 | 2009-04-02 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof, and wire bonding method |
-
2002
- 2002-01-28 JP JP2002018482A patent/JP2003218154A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007073937A (en) * | 2005-08-12 | 2007-03-22 | Kaijo Corp | Loop shape of bonding wire, semiconductor device comprising the same and bonding method |
| JP2007194470A (en) * | 2006-01-20 | 2007-08-02 | Kaijo Corp | Loop shape of bonding wire and semiconductor device having the loop shape, and bonding method |
| JP2007208148A (en) * | 2006-02-03 | 2007-08-16 | Ail Kk | Semiconductor chip mounted substrate |
| JP2009071046A (en) * | 2007-09-13 | 2009-04-02 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof, and wire bonding method |
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