JP2003217293A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which it can be judged at high speed and accurately whether a block is normal or not by performing status-read which a defective block is selected. <P>SOLUTION: The semiconductor memory device has memory cells which can read, write, and erase data, a row selecting means 3 selecting a specific row of this memory cell or selecting a block unit constituted unity of a row or more, a row selecting means control circuit 2 performing operation control of this row selecting means, and an I/O terminal 8 from which a first potential is outputted as an output result of a chip status of status-read when the normal block is accessed, and a second potential is outputted as an output result of a chip status of status-read when the defective block is accessed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which detects a defective block in a test state.

[0002]

2. Description of the Related Art In a semiconductor memory, memory cells are arranged in rows and columns, and the memory cells can be accessed by designating row and column addresses. Before a semiconductor memory is manufactured and shipped, various operation tests are performed.

The case of a NAND flash memory will be described below as an example. As one of the operation tests, the memory cells are accessed by specifying the row and column addresses, and a test is performed as to whether or not data writing, erasing, and reading can be performed normally. If a defect occurs, it is collected. Line by line
It is replaced with a redundant area (hereinafter referred to as a block) or a group of columns (hereinafter referred to as a column). Note that the group of collected lines may include both a defective line and a normal line, or may include only a defective line. Since a block is a group of rows, for example, when 32 rows form one block, and if one row out of 32 rows is a defective row, the entire 32 rows are replaced with redundant blocks.

If the number of defective blocks exceeds the number of redundant blocks prepared in advance (for example, 16), the defective blocks cannot be replaced with normal blocks, but the defective blocks that cannot be replaced (hereinafter referred to as Bad Block ( BB)) is the upper limit (e.g. 20
If it is less than or equal to 1), the operation test passes and is shipped.

Next, a read method of a conventional NAND flash memory will be described. FIG. 6 shows a schematic configuration of a conventional semiconductor memory device. An address input command and an address are input from the input terminal 50, and a read operation is performed on unused memory cells. The input address and command are input to the control circuit (Control Circuit) 51, and the row selection means (row decoder) 5 is input from the control circuit 51.
2. The control signals of the column selecting means (Column Decoder) and the sense amplifier (Sense Amplifier) 53 are output. The row selecting means 52, the column selecting means, and the sense amplifier 53 perform an operation of accessing a memory cell designated by an address when a normal memory cell is accessed. When the input address is the address of BB, the row selecting means 52 brings the block address into the non-selected state as described later. As a result, all the read cell data are regarded as “0” data (off cells), and the block of the accessed address can be recognized as BB. That is, no current is unconditionally passed through the memory cell. It looks like all the data is written. The memory cells are arranged in a matrix in a memory cell array 54. The column selection means and the sense amplifier 53 use the read data as I / O data control means (I / O controller: I / O controller:
O Data Controller) 55 and status output pins (I / O pins) 56 to the outside of the semiconductor memory device. Here, when the pin indicating the chip status is in the pass state and the output data is all "0" data, the selected block is determined to be a defective block.

That is, as shown in FIG. 7 showing a conventional defective block detection method for a semiconductor memory device, the semiconductor memory device is powered on (ST1) and an address input command is input to the semiconductor memory device (ST2). ). Next, the address is input (ST3). Next, an operational command is input to write or erase the cell (ST4). Next, a verify read operation is performed as a read operation for verifying whether or not desired writing or erasing has been performed (ST5). Next, in the judgment step (ST6), it is confirmed whether or not the written or erased state in the cell is correctly recorded. In this step, if all "0" data is read, it is determined that the block is defective (ST7). Next, when all "0" data is not read, it is determined that the block is a normal block (ST8).

A method of recognizing a defective block (Bad Block: hereinafter also referred to as BB) which cannot be replaced by a redundant block, which occurs before shipment of a product, is performed by a block address decoding circuit in the row selecting means 52 shown in FIG. Set not to hit. As shown in FIG. 8, this block decoding circuit uses a system in which the information indicating that it is BB is held in the latch L1. There is also a method of using a fuse other than the latch.

When accessing the block address decoding circuit shown in FIG. 8, RADD1 to RADDn are all at "H" level. In this state, any of read / write / erase operations can be executed. FIG. 9 shows the BB registration method of the block address decoding circuit shown in FIG. 8 and the operation when the BB is accessed. From time t1 to t6, the block of FIG.
As a result of accessing (denoted as 1), the bad block registration operation when it is found to be BB is shown. After time t7, the operation of B1 when BB is selected is shown.

The signal BAEN is biased at "L". This signal BAEN is a defective block access enable signal which becomes "H" level when it is desired to forcibly access the defective block. BLKBUS1 signal is a defective block detection signal line that is commonly connected to all blocks.
The ENSE signal is a bad block detection signal. The LRESET signal is a latch reset signal, the LSET signal is a defective block set signal that activates the state of the defective block, and Lout is a latch output. Loutn is an inverted signal of the latch output.

First, at time t1, a pulse of L → H → L is input to the LRESET signal to reset the latch L1, and the Lout node becomes “H” level and the Loutn node becomes “L” level. This means not in BB. When the block is accessed, "H" level is input to all row addresses RADD1 to RADDn (n is a natural number) at time t2. PREC at time t3
The Hn signal changes from the “H” level to the “L” level, decoding is started, DECn becomes the “L” level, DEC becomes the “H” level, and the selected state is set.

If the block B1 is found to be BB (for example, if the write operation could not be executed normally), the pulse L → H → L is input to the LSET node at time t5, and the transistors Tr2 and Tr3 are input. Are turned on, the node Lout changes from “H” level to “L” level, and BB information is set. That is, when the block B1 is written during the period from the time t3 to the time t5 and the normal operation cannot be performed, it is determined to be a defective block. At time t6, access to the illustrated block ends, and BB registration is completed.

After that, when the block B1 is accessed at time t7 and all "H" levels are input to the row addresses RADD1 to RADDn, the signal PRECHn changes from "H" level to "L" level at time t8. , Decoding is started, but since the node Lout is at “L” level, DECn is at “H” level, DE
C becomes "L" level and the block shown in FIG. 6 is not selected.

At time t1, the LRESET signal becomes a pulse signal of "H" level, and it is recognized that the memory cell being accessed is not a defective block. Next, between time t3 and time t5, the write or erase operation is performed on the selected memory cell. Next, at time t5, a pulse signal of “H” level is input as the LSET signal, and it is recognized that the defective block has been accessed. Then from time t6
A read operation is performed during t7. Here, when a read operation is normally performed as a write verify operation, for example, writing is performed 10 times, and if normal data is not output in the 10th verify read,
Judge as defective. Further, when the read operation is performed as the erase verify operation, the erase is performed, for example, four times, and if normal data is not output in the fourth verify read, it is determined to be defective.

The above is the BB registration method and the operation of the block B1 when the BB is accessed. As described above, when the BB data is read, the memory cell is not brought into the selected state and the bit line is not discharged, so that all the data is read as "0" and it can be recognized as a defective block. That is, the cells are unconditionally supplied with no current, and it is made to appear as if all the data is being written, so that it can be clearly seen that there is an error region. The nonvolatile semiconductor memory device immediately after being manufactured is normally in the "1" data state, or all the "1" states are set before the test. Also,
Immediately before product shipment, the nonvolatile semiconductor memory device is shipped with the memory area used by the user in the completely erased state (“1” data). Therefore, at the time of the test, it is possible to definitely determine that the error is made by accessing and reading the area in which all “0” data is not written.

In the accessed block, not only defective cells but also normal cells are collectively replaced with redundant cells. Here, when there are about 1000 blocks in one semiconductor memory device, about 10 blocks are provided as a redundant area, and the specification is set to ship as a non-defective product up to a specified number of blocks. Then, it is determined whether or not there are a specified number of defective blocks or more, and when a specified number or more of defective blocks are detected, they are treated as defective products. When a defective block of less than a specific number is detected, the defective block is replaced with a redundant block as much as possible, repaired, and shipped.

Conventionally, when a bad block is selected, the status is that the bad block is selected,
It was set to output the path. The outputs of this path are all in the state of being displayed as "0", and if the block operates correctly and is a defective block, it becomes a path. This is because the defective block can be recognized by reading the data of a predetermined memory cell (which can be arbitrarily determined by the user) in the defective block and determining whether or not the data is all "0" data. By detecting the bad block, it is possible to set so that the user does not use the bad block. That is, the defective block is replaced with the redundant block. Thus, by replacing with a spare block, even if an address that originally points to a defective block is input, it is possible to access a normal redundant cell and read / write and erase correct information. Here, if there is no redundant block to replace the bad block,
When a user specifies a defective address, the address is set to be inaccessible to prevent a malfunction when the user uses the semiconductor memory device.

[0017]

The conventional semiconductor memory device as described above has the following problems. When a bad block is selected, it means that normal memory cell access cannot be performed. Therefore, although outputting a fail is appropriate, the path is output. Therefore, it is not possible to correctly and simply judge whether or not the data writing, erasing, and reading are normally performed. In addition, it is necessary to select an area in which all "0" data is not written to perform reading, and there are restrictions on reading. Furthermore, when accessing and reading the memory cell,
It takes several tens of microseconds per block, so B
It takes a long time to detect B. Here, there are, for example, about 1 million memory cells in one block. Note that when a memory cell is accessed and read, a high voltage is applied and a relatively long time is required.
As described above, there has been a problem that it becomes difficult to perform an efficient test operation as the semiconductor memory device becomes larger in scale.

An object of the present invention is to solve the above problems of the prior art.

In particular, an object of the present invention is to provide a semiconductor memory device capable of performing status reading when a defective block is selected to judge whether it is normal or not at high speed and accurately.

[0020]

In order to achieve the above object, a feature of the present invention is that a memory cell capable of reading and writing data and a specific row of this memory cell or a group of one or more rows is formed. Row selecting means for selecting a block unit to be processed, a row selecting means control circuit for controlling the operation of the row selecting means, and when the normal block is accessed, the chip status output result of the status read is the first result. A semiconductor memory device having an I / O terminal to which a second potential is output as a chip status output result of status read when a potential is output and the defective block is accessed.

According to another aspect of the present invention, a memory cell capable of reading and writing data and a row for selecting a specific row of this memory cell or a block unit composed of one or more rows is selected. Detecting means, a row selecting means control circuit for controlling the operation of this row selecting means, and a defective block detection for judging whether the row selected by this row selecting means control circuit is defective and outputting the result Means and
When the normal block is accessed, the first block is output as the chip status output result of the status read in response to the judgment result of the normal state from the defective block detection means.
When the defective block is accessed, the second potential is output as the chip status output result of status read when the defective block is accessed. Semiconductor memory having an I / O data controller that performs a control operation as described above and an I / O terminal that receives the output from the I / O data controller and outputs the first potential or the second potential It is a device.

[0022]

1 is a block diagram of a semiconductor memory device using a flash memory according to an embodiment of the present invention as an example.
It will be described with reference to FIGS. FIG. 1 shows a configuration related to defective block detection of the semiconductor memory device of the present embodiment and its peripheral configuration. Note that, in FIG. 1, unlike FIG. 6 showing a conventional example, illustration of control signals from the control circuit 2 to the column selecting means and the sense amplifier 4 is omitted.
An address input command and an address are input from the input terminal 1 to perform a read operation of unused memory cells. The input address and command are controlled by the control circuit (Cont.
input from the control circuit 2 to the row selection means (row decoder: row decoder) 3, column selection means (column decoder: column decoder) and sense amplifier (sense).
Amplifier 4 control signal is output. The row selecting unit 3, the column selecting unit, and the sense amplifier 4 perform an operation of accessing a memory cell designated by an address when accessing a normal memory cell. In the row selection means 3, the accessed block is the normal block, BB
Regardless of the selected state. From the row selection means 3, a BB signal holding circuit (Bad B) is provided with a signal for identifying whether or not the BB is accessed using the signal in the selected state and the signal of the BB information.
lock Signal Latch) 6 is output. The memory cells are arranged in a matrix in a memory cell array (Memory Cell Array) 5.

If the input address is an address designating a defective block, the row selecting means 3 will be described later.
The block address is set to the non-selected state. Here, when the memory cell is read, the BB signal holding circuit 6
Then, all the read cell data is regarded as "0" data (off cell), and the block of the accessed address can be recognized as a defective block. That is, no current is unconditionally passed through the memory cell. It looks like all the data is written. Thus, data regarded as "0" data is I / O data control means (I / O controller: I / O Data Controller).
7 and from the status output terminal (“I / O” pin) 8 to the outside of the semiconductor memory device. The input address and command are input to the control circuit 2 and the control circuit 2 outputs the control signal of the row selecting means 3. I /
Upon receiving the output from the BB signal holding circuit 6, the O data control means 7 outputs a status fail when the defective block is accessed, and outputs a pass when the normal block is accessed. I / O data control means 7
Is an inverter circuit, NAND circuit, NOR circuit (not shown)
It is a logic circuit composed of, for example, a circuit that satisfies the above output conditions.

FIG. 2 shows a flowchart of a method for detecting a defective block in the semiconductor memory device of this embodiment. In this embodiment mode, the reading operation of the memory cell is not performed,
This is a method of outputting the fail status when the status is read by using the BB information held in the row selection means. That is, the details of the operation of the row selection means will be described below. First, the semiconductor memory device is powered on (S1), and an address input command is input (S1).
2). Next, the address is input (S3). Next, an operational command is input (S4). Here, a command for activating the defective block detecting means is input. Next, a status read operation (Status Read Operation) is executed (S5). Here, the status read result is valid when the chip status is in the ready state (for example, the state where the “I / O6” pin is “1”). Next, in the output status output terminal 8, "I /
When the "O6" pin is "1", it is determined whether the "I / O1" pin in the output status output terminal 8 is "1" (S6). And the "I / O1" pin is "1"
If it is, it is treated as a defective block (S7).
If the "I / O1" pin is not "1", it is treated as a normal block (S8).

Here, the address and the command are input to the control circuit 2. The control circuit 2 outputs data to the row decoder 3. That is, RADD1 to RADDn signals, BAEN signals, LRESET signals, LSET signals, BLKSENSE signals, PRECHn signals, etc. are output. The BLKBUS1 signal is output from the row decoder 3 to the BB signal holding circuit 6. The BB signal holding circuit 6 also receives a part of the output from the control circuit 2, performs a latch operation, and holds data during the status read period. The output of the BB signal holding circuit 6 and the defective block detection status read signal of the control circuit 2 are input to the I / O data control circuit 7. A status read result is output from the I / O data control circuit 7 to the outside of the semiconductor memory device. That is, when the chip status indicates a failure in the ready state, the specified address is a bad block. In the case of the busy state instead of the ready state, it means that the writing, erasing or reading operation is being performed, and the result of the status read is not valid.

FIG. 3 shows a block address decoding circuit which is a part of the row decoder 3. The block address decoding circuit has an address decoding means 10 to which a precharge signal PRECHn, row address signals RADD1, ..., RADDn, a defective block enable signal BAEN, and a Lout node are input. The Lout node is connected to the defective block information holding means 11 including a latch circuit.
In the Lout node of this bad block information holding means 11,
Further, the setting means 12 of the defective block information holding means 11 controlled by receiving the set signal LSET is connected. In addition, the Loutn node of this information holding means 11
The reset means 13 of the bad block information holding means 11 controlled by receiving the reset signal LRESET is connected. The reset means 13 has an NMOS transistor whose gate receives the reset signal LRESET and whose source is grounded.

Then, the output (DEC node) of the address decoding means 10 and the Lou of the defective block information holding means 11
The tn node is input to the BB detection means 14. The BB detection means 14 is controlled by the block sense signal BLKSENSE, and its output (BLKBUS1 node) is input to the BB signal holding circuit 6. The row decoder 3 holds the defective block information, transfers the BB information of the block accessed during the BB detection operation to the BB signal holding circuit 6, and outputs the content during the status read operation. In a semiconductor memory device having memory cell arrays 5 arranged in rows and columns, when a defective block (row) is accessed and a BB detection operation is performed, a status read (Status Read) is performed and a fail status is output.

The address decoding means 10 has a first PMOS transistor PT1 whose source is connected to the power supply potential and whose gate receives the signal PRECHn. This first PMOS transistor PT1 has 2
Two PMOS transistors PT2 and PT3 are connected in series with each other. Of these two PMOS transistors,
The gate of the PMOS transistor PT2 on the power supply potential side is grounded, and the gate of the PMOS transistor PT3 connected to the drain thereof is connected to the input terminal (DEC node) of the setting means 12 of the defective block information holding means 11. Further, an inverter IV1 is connected between the gate and drain of the PMOS transistor PT3.

Further, a plurality of NMOS transistors NT1 to NTn connected in series to each other are connected to the drain of the PMOS transistor PT1, and a row address signal RADD1, ..., RADDn is provided to each gate. It has been entered. Then, the source of the NMOS transistor NTn receives the precharge signal PRECHn at the gate N
The MOS transistor NTP is connected. This NMO
Two NMOS transistors NTB and TR6 connected in parallel with the ground are connected to the source of the S transistor NTP. Of these, the BAEN signal is input to the gate of the NMOS transistor NTB. Also, NMOS
The gate of the transistor TR6 is input to the defective block information holding unit 11 (Loutn node).

In the setting means 12, the source is grounded, the set signal is input to the gate, and the NMOS transistor TR2 connected to the LSET node is connected in series to this transistor, and the PM of the address decoding means 10 is connected to the gate.
The gate of the OS transistor PT3 is connected to the DEC node,
Drain is bad block information holding means (Lout node) 1
Connected to 1.

The defective block information holding means 11 has two inverters IV2 and IV3 whose input ends are connected to the output ends of other inverters.

The BB detecting means 14 has an NMOS transistor TR1 whose gate is connected to the reset means and whose source is grounded. Further, the drain of the NMOS transistor TR1 has an NM gate whose gate is connected to the BLKSENSE signal.
The source of the OS transistor TR4 is connected. The drain of the NMOS transistor TR4 is connected to the NMOS transistor TR5 whose gate is connected to the gate of the NMOS transistor TR3 of the setting means of the information holding means, and the drain of the NMOS transistor TR5 is BLKBUS1.
The signal is output to the BB signal holding circuit 6 as a signal.

FIG. 4 shows an example of signal output from the I / O terminal when status reading is performed. When BB is accessed and status read is performed, if the output result of status read is valid and the output result of I / O1 is "0" when the chip is in the ready state ("1" output), pass , "1" indicates a fail state. "I /
The output of "O6" is used as a test state, and it is determined whether or not the output result of "I / O1" is valid. "I / O1" and "I / O
Other than the output of "6", it is irrelevant to the values indicating the defectiveness and normality of the block. Thus, even if an address is input, it is possible to detect a defective or normal block of a specific address by accessing only the logic circuit without actually accessing the memory cell. It can speed up.

Next, FIG. 5 shows the BB registration method of the block address decoding circuit shown in FIG. 3 and the operation when the BB is accessed. From time t1 to t6, the block of FIG.
Access), the bad block registration operation when it is found to be BB is shown. After time t7, the operation of B1 when BB is selected is shown. In FIG. 3, the BAEN signal is
The BLKBUS1 signal is maintained at the "H" level, and the BLKBUS1 signal is maintained at the "H" level except when the BLKSENSE signal is at the "H" level.
First, at time t1, a pulse of L → H → L is input to the reset signal LRESET to reset the reset means 13 to set the Lout node to “H” level and the Loutn node to “L” level. This means not in BB. When the Loutn node is at the “L” level (that is, the Lout node is at the “H” level), the transistor TR6 is turned on when accessed. Next, at time t2, the "H" level signal is input to the row addresses RADD1 to RADDn (n is a natural number).

Next, at time t3, the PRECHn signal changes from the "H" level to the "L" level, decoding is started, the DECn signal becomes the "L" level, the DEC signal becomes the "H" level, and the selection state is set.

BLKSENSE becomes "H" level at time t4,
Detects whether block B1 is BB. The BLKBUS1 signal is
Initially, it is biased to the “H” level (the bias circuit is not shown). If the Loutn node is at “L” level,
Since it is a normal block, transistor TR1 does not conduct and BLK
The BUS1 signal remains at "H" level.

When the block B1 is found to be BB (for example, when the write operation cannot be executed normally), a pulse of L → H → L is input to the LSET node at time t5, and the transistors TR2 and TR3 are input. Are turned on, the Lout node changes from the “H” level to the “L” level, and the BB information is held.

Next, at time t6, the PRECHn signal changes from the "L" level to the "H" level, the decoding is completed, the access to the block B1 is completed, and the BB registration is completed.

After that, when the block B1 is accessed at time t7 and "H" is input to the nodes RADD1 to RADDn, the signal PRECHn changes from "H" level to "L" level at time t8. Decoding is started, the signal DECn is at “L” level, DEC is at “H” level, and the block shown in FIG. 3 is in the selected state. Next, at time t9, the signal BLKSENSE becomes “H” level, and the block When it is detected whether B1 is BB or not, since the signal DEC is “H” level and the node Loutn is “H” level, the transistors TR1, TR4 and TR5 are turned on and the signal B
LKBUS1 goes from “H” level to “L” level, and it can be detected that it is BB.

In this way, when the signal BLKBUS1 becomes "L" level, the signal BLKBUS1 is input to the BB signal holding circuit 6 of FIG. 1 and the state is held, and the status read is carried out in the ready state of the chip, I / I The O output signal control circuit 7 outputs a control signal for outputting the chip status in the fail state.

In the test mode, the signal BAEN is at "H" level, and in the prior art, the defective block is pretended to read out the memory cell to load the memory cell and the sense amplifier. On the other hand, in the semiconductor memory device of the present embodiment, the load on the memory cell and the sense amplifier is removed. That is, an address is entered, block access is performed, defective block detection and status reading are performed, and defective block information is read. The chip status information is output to, for example, the “I / O1” pin.

In this way, when the normal block is selected when the detection command is input and executed in the ready state, the normal state data is output as the chip status output result. In addition, when a detection command is input and executed in the ready state, if a defective block is selected, defective state data is output as the chip status output result.

The read chip status information is
Check that the access block is failing with the "I / O1" pin and confirm that it is ready with the "I / O6" pin. The number of lines in one block is 32, 16,
There are cases where there are eight or the like, and the number may be one.

Here, when the present embodiment is applied to the flash memory, the block is composed of a plurality of rows. On the other hand, when the present embodiment is applied to DRAM, SRAM, etc., blocks can be applied in units of one row.

As described above, according to this embodiment, no memory cell is accessed in the defective block detection mode. Furthermore, it does not access the sense amplifier. Therefore, the defective block detection operation can be executed faster than in the conventional semiconductor memory device.

As described above, in the semiconductor memory device of the present embodiment, it is possible to judge whether it is pass or fail when the defective block is accessed by performing the status read operation. When a defective block is selected, it means that normal memory cell access cannot be performed, and therefore a fail can be output. Further, by doing so, it is possible to correctly and simply determine whether or not the data writing, erasing, and reading have normally performed. That is, writing is performed in all cells, erasing is performed in all cells, and reading is performed in verify read for verifying whether writing or erasing is correctly performed after writing or erasing operation. . That is, in the semiconductor memory device of the present embodiment, when a defective block is selected in a semiconductor memory having a defective block, the status read is performed without reading the data of the memory cell, thereby making a high-speed and accurate determination. it can.

When reading the status, 1 is set.
The time required for each block can be executed in the order of several hundreds of nanoseconds, and the BB detection work time can be shortened. Here, there are, for example, about 1 million memory cells in one block. On the other hand, in the status read operation, since no signal is sent to the memory cell, the applied voltage may be about the power supply voltage, the boosted potential is unnecessary, and the read time is short. Further, the status read of the present invention is always valid as long as the chip is in the ready state, and can be performed during other operations.

In this way, only the logic circuit is accessed without accessing the memory cell, the current consumption is kept low without operating the sense amplifier, the test can be executed at high speed, and the manufacturing efficiency of the semiconductor memory device can be improved.
That is, it becomes possible to perform the test operation in a time period of tens of minutes as compared with the conventional case. This shortening of the test time can shorten the manufacturing process particularly in a large-scale semiconductor memory device in which the number of times of testing is large, and can improve the manufacturing efficiency. If the user of the semiconductor memory device knows the test command, the user can also perform the test operation.

[0049]

As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of performing a status read at the time of selecting a defective block and determining whether it is normal or not at high speed and accurately.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a defective block detection method for a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a block address decoding circuit of the semiconductor memory device according to the exemplary embodiment of the present invention.

FIG. 4 is a table showing a relationship between status read status and output of the semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a timing chart showing an operation when a defective block registration unit and a defective block of the semiconductor memory device according to the exemplary embodiment of the present invention are accessed.

FIG. 6 is a schematic configuration diagram of a conventional semiconductor memory device.

FIG. 7 is a flowchart showing a conventional defective block detection method for a semiconductor memory device.

FIG. 8 is a circuit diagram of a block address decoding circuit of a conventional semiconductor memory device.

FIG. 9 is a timing chart showing an operation when a defective block registering unit and a defective block of a conventional semiconductor memory device are accessed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 input terminal 2 control circuit 3 row selection means (row decoder) 4 column selection means (column decoder) and sense amplifier 5 memory cell array 6 BB signal holding circuit 7 I / O data control means 8 status output terminal ("I / O") Pin) 10 address decoding means 11 bad block information holding means 12 setting means 13 resetting means 14 BB detecting means IV1, IV2, IV3 inverters NT1, NTB, NTn, NTP, TR1, TR2, TR3, TR4, TR5, TR6 NMOS transistor PT1 , PT2, PT3 PMOS transistor S1, ..., S8, ST1, ..., ST8 Step

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Nakamura             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F term (reference) 5B018 GA04 HA21 KA15 NA06                 5B025 AD00 AD01 AD02 AD13 AD16                       AE00 AE09                 5L106 AA10 CC01 DD00 EE02 FF05                       GG07

Claims (4)

[Claims] 1. A memory cell capable of reading and writing data, a row selecting means for selecting a specific row of this memory cell or a block unit composed of a group of one or more rows, and an operation of this row selecting means. When the normal block is accessed, the first potential is output as a chip status output result of status read, and when the defective block is accessed, the status read A semiconductor memory device having an I / O terminal to which a second potential is output as a chip status output result. 2. A memory cell capable of reading and writing data, a row selecting means for selecting a specific row of this memory cell or a block unit composed of a group of one or more rows, and an operation of this row selecting means. The row selecting means control circuit for controlling, the defective block detecting means for judging whether the row selected by the row selecting means control circuit is defective, and outputting the result, and the normal block are accessed. In the case where the chip status output result of the status read is received from the defective block detection means, the first status is received as the chip status output result.
When the defective block is accessed, the second potential is output as the chip status output result of status read when the defective block is accessed. An I / O data controller that performs a control operation as described above, and an I / O terminal that receives the output from the I / O data controller and outputs the first potential or the second potential. And semiconductor memory device. 3. The potential output indicating the defective block or the normal block is a potential indicating the defective block or the normal block when the output of the specific I / O terminal is an output indicating the ready state. 3. The semiconductor memory device according to claim 1 or 2, wherein the output of is valid. 4. A command is input to detect whether or not the memory cell block is in a normal state,
4. The output of the potential indicating that the defective block or the normal block is executed.
2. The semiconductor memory device according to claim 1.