JP2003216066A - Electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical device which is capable of solving the nonuniformity of electric resistance in a fixing part and in which failure on display such as the lowering of a contrast does not occur by making contact bonding conditions of a display board and a junction board equal over the whole of the fixing part and the electronic apparatus provided with the electro- optical device. <P>SOLUTION: In this electro-optical device, a flattening film 80 is formed between electrodes 74, 75 and the like each of which is connected to the wiring formed on a junction board such as a flexible board and the like and a first interlayer insulating layer 284 is formed on the flattening film 80 and at edge parts of the electrodes 74, 75. Moreover, a transparent electrode 77 is formed on the electrodes 74, 75 and on a projected part 79. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device and an electronic device, and more particularly to an electro-optical device including an organic electroluminescent material and an electronic device including the electro-optical device.

[0002]

2. Description of the Related Art In recent years, a color electro-optical device having a structure in which a light emitting element made of a light emitting material such as an organic fluorescent material is sandwiched between a pixel electrode (anode) and a cathode, and particularly as a light emitting material, organic electroluminescence (organic EL) is used. ) Organic EL display devices using materials are being developed. Hereinafter, a conventional electro-optical device (organic EL display device) will be briefly described.

FIG. 13 is a diagram showing a wiring structure of a conventional electro-optical device. As shown in FIG. 13, the conventional electro-optical device includes a plurality of scanning lines 901, a plurality of signal lines 902 extending in a direction intersecting with the scanning lines 901, and a signal line 9.
02, a plurality of light emitting power supply wirings 903 extending in parallel with each other are provided, and a pixel region A is provided at each intersection of the scanning line 901 and the signal line 902. Each signal line 90
2 is a shift register, a level shifter, a video line,
And data side drive circuit 904 including analog switch
, And each scanning line 901 is connected to a scanning side drive circuit 905 including a shift register and a level shifter.

Further, in each pixel area A, a scanning line 90
1, a switching thin film transistor 913 to which a scanning signal is supplied to the gate electrode, a holding capacitor Cap that holds an image signal supplied from the signal line 902 via the switching thin film transistor 913, and a holding capacitor Ca.
A driving current flows from the light emitting power supply wiring 903 when electrically connected to the current thin film transistor 914 to which the image signal held by p is supplied to the gate electrode and the light emitting power supply wiring 903 via the current thin film transistor 914. The pixel electrode 911 and this pixel electrode 91
1 and a cathode 912, and a light emitting layer 910 sandwiched therebetween. The cathode 912 is a cathode power supply circuit 931.
It is connected to the.

The above-mentioned light emitting layer 910 includes three types of light emitting elements: a light emitting layer 910R that emits red light, a light emitting layer 910G that emits green light, and a light emitting layer 910B that emits blue light.
Each light emitting layer 910R, 910G, 910B is arranged in stripes. The current thin film transistor 91
Power supply wirings 903R, 903G, 903B for light emission connected to the respective light emitting layers 910R, 910G, 910B via
Are connected to the light emitting power supply circuit 932.
The light emitting power source wiring is provided for each color because the drive potential of the light emitting layer 910 is different for each color.

In the above structure, the scanning signal is supplied to the scanning line 901 to cause the switching thin film transistor 913.
When is turned on, the charge corresponding to the image signal supplied to the signal line 902 at that time is held in the holding capacitor Cap. The on / off state of the current thin film transistor 914 is determined according to the amount of electric charge stored in the storage capacitor Cap. Then, the current thin film transistor 914
Power supply wiring for light emission 903R, 903G, 903B via
Current flows from the pixel electrode 911 to the pixel electrode 911, and further, a driving current flows to the cathode 912 through the light emitting layer 910. At this time, an amount of light emitted according to the amount of current flowing through the light emitting layer 910 is emitted by the light emitting layer 91.
Obtained from 0.

[0007]

By the way, in the electro-optical device shown in FIG. 13, the scanning line 901, the signal line 902, the cathode 912, and the light-emitting power source wiring 903 (903R, 903).
G, 903B), the scanning side drive circuit 905, and the pixel region A are formed on a transparent substrate (display substrate) such as glass, and the cathode power supply circuit 931, the light emission power supply circuit 932, the data side drive circuit 904, and the like. The circuit may be arranged on a flexible board (relay board) having flexibility.

In the case of such a structure, the flexible substrate is fixed to the substrate, and the scanning line 901 and the signal line 90 are attached.
2, it is necessary to electrically connect the cathode 912, the light emitting power source wiring 903, and the circuit formed on the flexible substrate. Fixing and electrical connection between the substrate and the flexible substrate are performed by disposing an anisotropic conductive film containing conductive particles between the substrate and the flexible substrate and pressing the flexible substrate onto the substrate.

In order to stably emit light from the light emitting layer 910 provided in the above-described electro-optical device, it is required to reduce the potential fluctuation of the drive current applied from the light emitting power source wiring 903 to the pixel electrode 911 as much as possible. . In particular, the electro-optical device shown in FIG. 13 is a current-driven electro-optical device, and in order to prevent display defects such as display unevenness and contrast reduction, the wiring resistance of the cathode 912 and the light-emitting power supply wiring 903 is reduced. It is necessary to suppress the voltage drop due to factors such as Therefore, the cathode 912 and the light-emitting power source wiring 90
3 is wider than the scanning line 901 and the signal line 902.

When the substrate and the flexible substrate are fixed to each other, there is a demand for making the pressure bonding conditions uniform over the entire surface of the bonding portion, mainly in order to make the electrical resistance generated in the pressure bonding portion uniform. To meet this requirement,
It is necessary that the terminals provided on the fixed portion and connected to the various wirings described above have the same shape.

However, as described above, since the electro-optical device shown in FIG. 13 is a current-driven electro-optical device, it is necessary to reduce the wiring width of the cathode 912 and the light-emitting power supply wiring 903 due to wiring resistance or the like. It is difficult to consider the voltage drop. Further, since the number of the scanning lines 901 and the signal lines 902 is large and it is necessary to make the lines thin and the pitch narrow to arrange them all, the scanning lines 901 and the signal lines 9 are required.
It is also difficult to make the line width of 02 equal to the line widths of the cathode 912 and the light emission power wiring 903.

The present invention has been made in view of the above circumstances, and by making the pressure bonding conditions of the display substrate and the relay substrate the same over the entire fixed portion, the non-uniformity of electrical resistance in the fixed portion is achieved. It is an object of the present invention to provide an electro-optical device which can solve the above-mentioned problems and which does not cause a display defect such as a decrease in contrast, and an electronic apparatus including the electro-optical device.

[0013]

In order to solve the above problems, an electro-optical device according to the present invention is an electro-optical device in which at least a first wiring and a second wiring wider than the first wiring are formed. In, a first terminal for external connection connected to the first wiring, a plurality of second terminals for external connection connected to the second wiring, between the first terminals, between the second terminals, And a flattening film provided between the first terminal and the second terminal, on the flattening film, an end portion of the first terminal,
And a second insulating layer formed at an end of the second terminal. According to this invention, the first
A flattening film is provided between the terminals, between the second terminals, and between the first terminal and the second terminal, and an insulating film is provided on the flattening film, the end portion of the first terminal, and the end portion of the second terminal. Therefore, even if the thickness of the insulating layer is increased, the height of the insulating layer formed at the end of the first terminal and the end of the second terminal is equal to that of the insulating layer formed on the planarization film. Flatness can be ensured without being too high with respect to the surface of the layer. As a result, no connection failure occurs in the wiring connected to the first terminal and the second terminal. In addition, the electro-optical device of the present invention,
A convex portion is formed by the second insulating layer at an end portion of the first terminal and the second terminal. According to the present invention, the convex portion is formed at either end of the first terminal and the second terminal provided for the first wiring and the second wiring. For example, the wiring is made of an anisotropic conductive film. When the fixed substrate is fixed to the display substrate, the proportion of the conductive particles contained in the anisotropic conductive film protruding from both ends of the first terminal and the second terminal is reduced, and conversely, the conductive particles are formed on the first terminal and the second terminal. Since the ratio of staying is increased, it is extremely suitable for reducing the electric resistance in the fixed portion. Further, the electro-optical device of the invention is characterized in that a plurality of recesses are formed in the first terminal and the second terminal. According to the present invention, since the first and second terminals are so divided into a plurality of electrodes by the plurality of recesses formed on the surfaces of the first and second terminals, the wiring board is provided. It is possible to further uniformize the pressure bonding conditions such as the degree of pressure applied at the time of fixing the to the display substrate and establishing conduction. Further, in the electro-optical device of the present invention, a first relay wiring having a width similar to that of the first wiring and a second relay wiring having a width similar to that of the second wiring are formed. A relay board in which the first wiring and the first relay wiring are electrically connected via a terminal, and the second wiring and the second relay wiring are electrically connected via the second terminal. It is characterized by having. In order to solve the above problems, an electro-optical device according to the present invention supplies a plurality of light emitting elements and a current supplied through a power supply line to the light emitting element according to a signal supplied through a signal line. In an electro-optical device in which a switching element is formed, a first terminal for external connection connected to the signal line and an external connection formed to be wider than the signal line and connected to the power supply line. A plurality of second terminals, a flattening film provided between the first terminals, between the second terminals, and between the first terminals and the second terminals; on the flattening film; It is characterized by comprising an end of the terminal and an insulating layer formed on the end of the second terminal. Further, the electro-optical device of the present invention is characterized in that a convex portion is formed by the insulating layer at an end portion of the first terminal and the second terminal. Further, the electro-optical device of the invention is characterized in that a plurality of recesses are formed in the first terminal and the second terminal.
Also, in the electro-optical device of the present invention, a first wiring having a width similar to that of the signal line and a second wiring having a width similar to that of the power supply line are formed, and the first wiring is provided via the first terminal. It is characterized by having a relay substrate in which the signal line and the first wiring are electrically connected and the power supply line and the second wiring are electrically connected via the second terminal. Also,
The electro-optical device of the present invention is characterized in that the first and second terminals and the first and second wirings are fixed by an anisotropic conductive film. An electronic apparatus of the invention is characterized by including the electro-optical device described in any one of the above.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An electro-optical device and electronic equipment according to an embodiment of the present invention will be described in detail below with reference to the drawings. Each drawing referred to in the following description has a size such that each layer and each member are recognizable in the drawing.
The scale is made different for each layer and each member.

FIG. 1 is an exploded perspective view schematically showing an electro-optical device according to an embodiment of the present invention. As shown in FIG. 1, the electro-optical device 10 according to the present embodiment is roughly classified into a display substrate 20 and a relay substrate 30 connected to the display substrate 20.
Composed of and. The display substrate 20 is an active matrix organic EL device using a thin film transistor as a switching element.

A plurality of scanning lines 21 are formed on the display substrate 20.
Are formed, and a plurality of signal lines 22 extending in a direction intersecting the scanning lines 21 are formed. In addition, the display substrate 20 includes a display element 20a having a plurality of light emitting elements formed thereon.
Is provided. Further, although not shown in FIG. 1, a power supply line and a cathode are formed on the display substrate 20. In addition, at one end of the display substrate 20, the scanning line 21,
External connection terminals 27 for the signal line 22 and the power supply line and the cathode (not shown) are formed.

It should be noted that the electro-optical device 10 shown in FIG. 1 is merely a schematic representation of the main structure, and the actual scanning lines 21, signal lines 22, and external connection terminals 27 are
It should be noted that a large number are formed on the display substrate 20 at extremely narrow intervals. Further, the connection state between the external connection terminal 27 and the connection state of the scanning line 21 is also omitted in FIG.

The relay substrate 30 has a structure in which a plurality of wirings 32 are formed on a flexible base substrate 31, and a semiconductor chip 33 is mounted on a predetermined position of the relay substrate 30. At one end of the wiring 32, an external connection terminal 34 for electrically connecting with the wiring such as the scanning line 21 and the signal line 22 formed on the display substrate 20 is formed. Incidentally, FIG.
In the above, only the semiconductor chip 33 is mounted on the relay board 30, but resistors, capacitors, and other chip components may be mounted at predetermined positions other than the part where the semiconductor chip 33 is mounted. In addition, the wiring 32 and the external connection terminal 34 formed on the relay substrate 30 are also schematically illustrated by enlarging the interval and simplifying the structure in order to facilitate understanding of the structure.

As shown in FIG. 1, the relay substrate 30 is fixed to the display substrate 20 via the anisotropic conductive film 40. At this time, the external connection terminal 34 of the relay substrate 30 is electrically connected to the external connection terminal 27 of the display substrate 20 via the anisotropic conductive film 40. The anisotropic conductive film 40 is a conductive polymer film used to electrically connect a pair of terminals in an anisotropic manner and collectively, for example, as shown in FIG. , Thermoplastic or thermosetting adhesive resin 4
It is formed by dispersing a large number of conductive particles 41b in 1a.

FIG. 2 is a sectional view showing the manner in which the relay substrate 30 and the display substrate 20 are fixed by the anisotropic conductive film 40. As shown in FIG. 2, since the conductive particles 41b are sandwiched between the external connection terminal 27 formed on the display substrate 20 and the external connection terminal 34 formed on the relay substrate 30, the external connection terminal 27 and the relay wiring are formed. The external connection terminal 34 is electrically connected. On the other hand, even if the conductive particles 41b are sandwiched in a portion other than the portion where the external connection terminals 27 and 34 are formed,
There is no connection terminal, so there is no continuity. In this way, electrical connection can be established only between the external connection terminal 27 and the external connection terminal 34.

To fix the display substrate 20 and the relay substrate 30 to each other by using the anisotropic conductive film 40, the display substrate 20 is placed on a mounting table (not shown) having a guide plate having a rough surface. , And the display substrate 20 is vacuum-sucked. At this time, the display substrate 20 is mounted on the mounting table so that at least the portion where the relay substrate 30 is fixed to the display substrate 20 is located above the guide plate. Here, using the guide plate having a rough surface reduces the contact area between the guide plate and the display substrate 20 to suppress heat dissipation from the guide plate, thereby lowering the temperature applied to the display substrate 20. This is because.

When the mounting of the display substrate 20 on the mounting table is completed, the anisotropic conductive film 40 is attached to the portion of the display substrate 20 to which the relay substrate 30 is fixed, and further the semiconductor chip 33 is mounted. The relay substrate 30 is aligned so that the surface is on the lower side and the external connection terminals 34 are located above the anisotropic conductive film 40. When the above steps are completed, the back surface of the surface on which the external connection terminals 34 are formed is heated and pressed using a heating / pressurizing head (not shown), and the external connection terminals 34 and the external connection formed on the display substrate 20 are connected. The relay board 30 is fixed to the display board 20 while being electrically connected to the terminal 27. At this time, the temperature applied from the heating / pressurizing head to the relay substrate 30 and the display substrate 20 is about several tens to several hundreds of degrees Celsius,
The pressure applied is a few megapascals. Through the above steps, the relay substrate 30 can be fixed to the display substrate 20.

Next, details of the wiring structure of the electro-optical device 10 of this embodiment will be described. FIG. 3 is a diagram schematically showing the wiring structure of the electro-optical device according to the embodiment of the present invention. As shown in FIG. 3, the electro-optical device 10 includes a plurality of scanning lines 21, a plurality of signal lines 22 extending in a direction intersecting with the scanning lines 21, and a plurality of light emitting devices extending in parallel with the signal lines 22. The power supply wiring 23 is wired, and the pixel area A is provided near each intersection of the scanning line 21 and the signal line 22.

A data side drive circuit 33a including a shift register, a level shifter, a video line, and an analog switch is connected to each signal line 22. In addition, each signal line 22 has an inspection circuit 2 including a thin film transistor.
5 is connected. Further, each scanning line 21 has a scanning line driving circuit 24 including a shift register and a level shifter.
Are connected.

In each pixel area A, a switching thin film transistor 52, a storage capacitor Cap, a current thin film transistor 53, a pixel electrode 51, a light emitting layer 50, and a cathode 26 are provided. The switching thin film transistor 52 is connected to the gate electrode of the scanning line 21, and is driven according to a scanning signal supplied from the scanning line 21 to be turned on or off. The storage capacity Cap is
Signal line 22 via switching thin film transistor 52
Holds the image signal supplied from.

The gate electrode of the current thin film transistor 53 is connected to the switching thin film transistor 52 and the storage capacitor Cap, and the image signal held by the storage capacitor Cap is supplied to the gate electrode. The pixel electrode 51 is connected to the current thin film transistor 53, and when it is electrically connected to the light emitting power supply line 23 via the current thin film transistor 53, the light emitting power supply line 2
The drive current flows in from 3. The light emitting layer 50 is the pixel electrode 51.
And the cathode 26.

The light emitting layer 50 includes three types of light emitting elements, that is, a light emitting layer 50R that emits red light, a light emitting layer 50G that emits green light, and a light emitting layer 50B that emits blue light. 50G and 50B are arranged in stripes. The light-emitting power supply wirings 23R, 23G, and 23B connected to the light-emitting layers 50R, 50G, and 50B via the current thin film transistor 53 are connected to the light-emitting power supply circuit 33c, respectively. Power supply wiring 2 for each color
3R, 23G, and 23B are wired in the light emitting layer 5
This is because the driving potentials of 0R, 50G, and 50B are different for each color.

Further, in the electro-optical device of this embodiment, the cathode 26 and the light-emitting power source wirings 23R, 23G, 23B are provided.
And a capacitance C ₁ is formed between them. When the electro-optical device 10 is driven, electric charges are accumulated in this electrostatic capacitance C ₁ . Power supply wiring 23 for each light emission while driving the electro-optical device 10.
When the potential of the drive current flowing through the drive current fluctuates, the accumulated electric charge is discharged to each light-emitting power source wiring 23 to suppress the potential fluctuation of the drive current. Thereby, the image display of the electro-optical device 10 can be normally maintained.

In the electro-optical device 10, when the scanning signal is supplied from the scanning line 21 and the switching thin film transistor 52 is turned on, the potential of the signal line 22 at that time is held in the holding capacitor Cap, and the holding capacitor is held. Ca
The on / off state of the current thin film transistor 53 is determined according to the potential held at p. Then, a driving current flows from the light-emitting power supply wirings 23R, 23G, and 23B to the pixel electrode 51 through the channel of the current thin film transistor 53, and further a current flows to the cathode 26 through the light-emitting layers 50R, 50G, and 50B. At this time, an amount of light emission according to the amount of current flowing through the light emitting layer 50 is obtained from the light emitting layer 50.

Next, a specific structure of the electro-optical device 10 of this embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a schematic plan view of the electro-optical device of this embodiment, and FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG.
As shown in FIG. 4, the electro-optical device 10 of the present embodiment is
Substrate 60, pixel electrode group region (not shown), light-emitting power supply wiring 2
3 (23R, 23G, 23B), and the display pixel portion 61
(In the frame of the one-dot chain line in the figure).

The substrate 60 is a transparent substrate made of glass or the like. The pixel electrode group region is a region in which pixel electrodes (not shown) connected to the current thin film transistor 53 shown in FIG. 3 are arranged in a matrix on the substrate 60. Power line 23 for light emission (23R, 23G, 23B)
Are arranged around the pixel electrode group region and are connected to the respective pixel electrodes, as shown in FIG. Display pixel section 61
Is located at least on the pixel electrode group region and has a substantially rectangular shape in plan view. The display pixel portion 61 includes a real display area (or also referred to as an effective display area) 62 in a central portion (within a two-dot chain line in the figure) and a dummy area 63 (one point) arranged outside the real display area 62. The area between the chain line and the chain double-dashed line).

Further, the scanning line drive circuits 24 are arranged on both sides of the actual display area 62 in the figure. The scanning line drive circuit 24 is provided on the lower layer side (the substrate 60 side) of the dummy region 63. Further, on the lower layer side of the dummy region 63, the scanning line drive circuit control signal wiring 24 a and the scanning line drive circuit power supply wiring 24 b connected to the scanning line drive circuit 24.
And are provided. Further, the inspection circuit 25 described above is arranged above the actual display area 62 in the figure. The inspection circuit 25 is provided on the lower layer side (substrate side 2) of the dummy region 63, and the inspection circuit 25 can inspect the quality and defects of the electro-optical device during manufacturing or at the time of shipping. it can.

As shown in FIG. 4, the light-emitting power wiring 23
R, 23G, and 23B are arranged around the dummy area 63. Power lines 23R, 23G, 23B for light emission
2 extends from the lower side of the substrate 60 in FIG. 2 to the upper side in FIG. 4 along the scanning line drive circuit control signal wiring 24a, and is bent from the position where the scanning line drive circuit control signal wiring 24a is interrupted. The actual display area 62 extends along the outside of the dummy area 63.
It is connected to a pixel electrode (not shown) inside. Further, on the substrate 60, a cathode wiring 26 a connected to the cathode 26 is formed. The cathode wiring 26a is formed in a substantially U shape in plan view so as to surround the light emitting power wirings 23R, 23G, and 23B.

Next, as shown in FIG. 5, the circuit section 11 is formed on the substrate 60, and the display pixel section 61 is formed on the circuit section 11. Further, the substrate 60 is provided with a sealing material 13 that surrounds the display pixel portion 61 in a ring shape, and further, the sealing substrate 14 is provided on the display pixel portion 61. The sealing substrate 14 is bonded to the substrate 60 via the sealing material 13, and is made of glass, metal, resin, or the like. An adsorbent 15 is attached to the back side of the sealing substrate 14 so that water or oxygen mixed in the space between the display pixel portion 61 and the sealing substrate 14 can be absorbed. A getter agent may be used instead of the adsorbent 15. The sealing material 13 is made of, for example, a thermosetting resin or an ultraviolet curable resin, and is particularly preferably made of an epoxy resin which is a kind of thermosetting resin.

A pixel electrode group region 11a is provided in the central portion of the circuit portion 11. This pixel electrode group region 11a
Is provided with a current thin film transistor 53 and a pixel electrode 51 connected to the current thin film transistor 53. The current thin film transistor 53 includes a base protection layer 281 and a second interlayer insulating layer 28, which are stacked on the substrate 60.
3 and the first interlayer insulating layer 284, the pixel electrode 51 is formed on the first interlayer insulating layer 284. Connected to the current thin film transistor 53,
One of the electrodes (source electrode) formed on the second interlayer insulating layer 283 has a light-emitting power supply wiring 23 (23R, 23G,
23B) is connected. Although the storage capacitor Cap and the switching thin film transistor 52 described above are also formed in the circuit portion 11, they are not shown in FIG. Further, in FIG. 5, the signal line 22 is not shown.

Next, referring to FIG. 5, the pixel electrode group region 11
The above-mentioned scanning line drive circuit 24 is provided on both sides of a in the figure. The scanning line drive circuit 24 shown in FIG. 4 is provided with an N-channel type or P-channel type thin film transistor 24c forming an inverter included in a shift register, and the thin film transistor 24c is not connected to the pixel electrode 51. Except for the above, the current thin film transistor 53 has the same structure. Although the inspection circuit 25 is not shown in FIG. 5, the inspection circuit 25 is similarly provided with a thin film transistor.
The thin film transistor provided in the inspection circuit 25 has the same structure as the current thin film transistor 53 except that it is not connected to a dummy pixel electrode 51 'described later.

As shown in FIG. 5, the scanning line driving circuit control signal wiring 24a is formed on the underlying protective layer 281 outside the scanning line driving circuit 24 in the figure. In addition, the second interlayer insulating layer 2 outside the control signal wiring 24a for the scanning line driving circuit
The power supply wiring 24b for the scanning line drive circuit is formed on 83. Further, the light emitting power supply wiring 23 is formed outside the power supply wiring 24b for the scanning line drive circuit. The light-emitting power supply wiring 23 has a double wiring structure including two wirings, and is arranged outside the display pixel portion 61 as described above. Wiring resistance can be reduced by adopting a double wiring structure.

For example, for red light emission on the left side in FIG.
The power supply wiring 23R is the first wiring formed on the base protection layer 281.
1 wiring 23R₁And a first interlayer insulating layer 283
Wiring 23R₁Second wiring 23R formed above₂Composed of and
Has been done. First wiring 23R ₁And the second wiring 23R₂Is
As shown in FIG. 2, a capacitor that penetrates the second interlayer insulating layer 283 is formed.
Tact Hall 23R₃Connected by. like this
And the first wiring 23R₁Is the same level as the cathode wiring 26a
The first wiring 23R is formed at the position₁And cathode wiring
26a, the second interlayer insulating layer 283 is disposed between
It Also, as shown in FIG. 5, the cathode wiring 26a is
Is formed on the second interlayer insulating layer 283 through the hole.
It is electrically connected to the cathode wiring 26b, so to speak
The pole wiring 26a also has a double wiring structure. Therefore,
Second wiring 23R₂Indicates the same hierarchical position as the cathode wiring 26b
Formed on the first wiring 23R₂And cathode wiring 26
A first interlayer insulating layer 284 is arranged between the first and second layers. This
By adopting such a structure, the first wiring 23R₁And for cathode
Between the wiring 26a and the second wiring 23R₂And for cathode
The second capacitance C between the line 26b₂Is formed
It

Similarly, the blue and green light-emitting power source wirings 23G and 23B on the right side of FIG. 5 also have a double wiring structure, and the first wirings 23G ₁ formed on the base protection layer 281 respectively. , 23B ₁ and second wirings 23G ₂ , 23B ₂ formed on the second interlayer insulating layer 283,
The first wirings 23G ₁ and 23B ₁ and the second wirings 23G ₂ and 23
B ₂ is connected by contact holes 23G ₃ and 23B ₃ penetrating the second interlayer insulating layer 283 as shown in FIG. A _second capacitance C ₂ is formed between the blue first wiring 23B ₁ and the cathode wiring 26a, and between the blue second wiring 23B ₂ and the cathode wiring 26b.

The distance between the first wiring 23R ₁ and the second wiring 23R ₂ is preferably in the range of 0.6 to 1.0 μm, for example.
If the distance is less than 0.6 μm, the parasitic capacitance between the source metal and the gate metal having different potentials such as the signal line 22 and the scanning line 21 increases, which is not preferable. For example, in the actual display area 62, there are many locations where the source metal and the gate metal intersect, and if the parasitic capacitance at these locations is large, there is a risk of causing a time delay of the image signal. As a result, an image signal cannot be written in the pixel electrode 51 within a predetermined period, which causes a reduction in contrast. The material of the second interlayer insulating layer 283 sandwiched between the first wiring 23R ₁ and the second wiring 23R ₂ is
For example, SiO ₂ or the like is preferable, but if formed to have a thickness of 1.0 μm or more, the substrate 60 may be cracked by the stress of SiO ₂ .

In addition, on the upper side of each light-emitting power wiring 23R
The cathode 26 extending from the display pixel portion 61 is formed.
There is. As a result, the second wiring of each light emitting power wiring 23R
23R ₂With the cathode 26 with the first interlayer insulating layer 284 in between.
The second wiring 23R is disposed so as to face each other.₂And cathode 26
And the above-mentioned first capacitance C₁Is formed. here
Then, the second wiring 23R₂The distance between the cathode and the cathode 26 is, for example,
The range of 0.6 to 1.0 μm is preferable. The interval is 0.6μ
If it is less than m, it is different like the pixel electrode and the source metal.
Parasitic capacitance between pixel electrode with potential and source metal
Therefore, the wiring delay of the signal line that uses the source metal
Delay occurs. As a result, the image signal is
Can't write, causing a drop in contrast
Rub Second wiring 23R₂And the first layer sandwiched between the cathode 26
The material of the insulating layer 284 is, for example, SiO.₂And acrylic resin
Etc. are preferred. However, SiO₂1.0 μm or less
If formed on top, stress may cause the substrate 60 to crack.
It In the case of acrylic resin, up to about 2.0 μm
Although it can be formed, it has the property of expanding when it contains water.
Therefore, there is a possibility that the pixel electrode formed thereon may be broken.

As described above, since the display substrate 20 is provided with the first electrostatic capacitance C ₁ between the light emitting power wiring 23 and the cathode 26, the potential of the drive current flowing through the light emitting power wiring 23 is When it fluctuates, the electric charge accumulated in the first electrostatic capacitance C ₁ is supplied to the light-emitting power source wiring 23, and the electric potential shortage of the driving current is compensated by this electric charge, so that the electric potential fluctuation can be suppressed, and the light emission The image display of the device 1 can be kept normal. In particular, since the light emitting power supply wiring 23 and the cathode 26 face each other outside the display pixel portion 61, the light emitting power supply wiring 2
3 and the cathode 26 to reduce the distance between the first electrostatic capacitance C ₁
It is possible to increase the amount of electric charge accumulated in the capacitor, reduce the potential fluctuation of the drive current, and perform stable image display. Further, the light-emitting power source wiring 23 has a double wiring structure including the first wiring and the second wiring, and the second capacitance C ₂ is provided between the first wiring and the cathode wiring. Since the electric charge accumulated in the second electrostatic capacitance C ₂ is also supplied to the light-emitting power source wiring 23, the potential fluctuation can be further suppressed, and the image display of the light-emitting device 1 can be kept more normal. .

Next, in the actual pixel area 62 of the display pixel section 61, the light emitting layer 50 and the bank section (insulating section) 122 are formed. As shown in FIG. 5, the light emitting layer 50 includes the pixel electrode 5
1 stacked on each. In addition, the bank unit 122
Is provided between each pixel electrode 51 and each light emitting layer 50 to partition each light emitting layer 50. Bank section 122
Is formed by stacking an inorganic bank layer 122a located on the substrate 60 side and an organic bank layer 122b located away from the substrate 60. The inorganic bank layer 122
A light shielding layer may be arranged between a and the organic bank layer 122b.

Inorganic and organic bank layers 122a, 122
b is formed so as to extend onto the peripheral portion of the pixel electrode 51, and the inorganic bank layer 122a is formed so as to extend closer to the center of the pixel electrode 51 than the organic bank layer 122b. The inorganic bank layer 122a is preferably made of an inorganic material such as SiO ₂ , TiO ₂ , or SiN. The thickness of the inorganic bank layer 122a is
The range of 50 to 200 nm is preferable, and 150 nm is particularly preferable. If the film thickness is less than 50 nm, the inorganic bank layer 122
It is not preferable because a becomes thinner than the hole injection / transport layer described later and the flatness of the hole injection / transport layer cannot be secured. On the other hand, if the film thickness exceeds 200 nm, the step due to the inorganic bank layer 122a becomes large and the flatness of the light emitting layer to be described later laminated on the hole injecting / transporting layer cannot be ensured, which is not preferable.

Further, the organic bank layer 122b is formed of a normal resist such as acrylic resin or polyimide resin. The organic bank layer 122b has a thickness of 0.
The range of 1 to 3.5 μm is preferable, and about 2 μm is particularly preferable. If the thickness is less than 0.1 μm, the organic bank layer 122b becomes thinner than the total thickness of the hole injecting / transporting layer and the light emitting layer described later, and the light emitting layer may overflow from the upper opening, which is not preferable. Further, if the thickness exceeds 3.5 μm, the step difference due to the upper opening becomes large, and step coverage of the cathode 26 formed on the organic bank layer 122b cannot be secured, which is not preferable. If the thickness of the organic bank layer 122b is 2 μm or more, the cathode 26
It is more preferable in that the insulation between the pixel electrode 51 and the pixel electrode can be enhanced. In this way, the light emitting layer 50 has the bank portion 1
It is formed thinner than 22.

Around the bank portion 122, a lyophilic region and a lyophobic region are formed. The lyophilic region is the inorganic bank layer 122a and the pixel electrode 51, and a lyophilic group such as a hydroxyl group is introduced into these regions by plasma treatment using oxygen as a reaction gas. Further, the region showing liquid repellency is the organic bank layer 12
2b, a liquid repellent group such as fluorine is introduced by plasma treatment using tetrafluoromethane as a reaction gas.

The light emitting layer 50 is laminated on a hole injection / transport layer (not shown) laminated on the pixel electrode 51. still,
In this specification, a structure including the light emitting layer 50 and the hole injecting / transporting layer is referred to as a functional layer, and a structure including the pixel electrode 51, the functional layer, and the cathode 26 is referred to as a light emitting element. The hole injection / transport layer is
It has a function of injecting holes into the light emitting layer 50 and a function of transporting holes inside the hole injecting / transporting layer. By providing such a hole injecting / transporting layer between the pixel electrode 51 and the light emitting layer 50, device characteristics such as light emitting efficiency and life of the light emitting layer 50 are improved. In the light emitting layer 50, the holes injected from the hole injection / transport layer and the cathode 26
It combines with the electrons from and emits fluorescence. Light emitting layer 50
Has three types, a red light emitting layer that emits red (R), a green light emitting layer that emits green (G), and a blue light emitting layer that emits blue (B), as shown in FIGS. 3 and 4. In addition, the respective light emitting layers are arranged in stripes.

Next, as shown in FIG. 5, the display pixel section 6
A dummy light emitting layer 210 and a dummy bank portion 212 are formed in the first dummy region 63. Dummy bank section 2
12 is the dummy inorganic bank layer 2 located on the substrate 60 side.
12a and a dummy organic bank layer 212b located away from the substrate 60 are laminated. The dummy inorganic bank layer 212a is formed on the entire surface of the dummy pixel electrode 51 '. Also, the dummy organic bank layer 212b
Are formed between the pixel electrodes 51 similarly to the organic bank layer 122b. The dummy light emitting layer 210 is formed on the dummy pixel electrode 5 via the dummy inorganic material bank 212a.
1 '.

The dummy inorganic bank layer 212a and the dummy organic bank layer 211b are made of the same material and have the same film thickness as the inorganic and organic bank layers 122a and 122b described above. In addition, the dummy light emitting layer 210 is
It is laminated on a dummy hole injection / transport layer (not shown),
The material and film thickness of the dummy hole injecting / transporting layer and the dummy light emitting layer are the same as those of the hole injecting / transporting layer and the light emitting layer 50 described above. Therefore, like the light emitting layer 50 described above, the dummy light emitting layer 210 is formed thinner than the dummy bank portion 212.

By arranging the dummy region 63 around the actual display region 62, the thickness of the light emitting layer 50 in the actual display region 62 can be made uniform and display unevenness can be suppressed. That is, by disposing the dummy region 63, the drying condition of the ejected composition ink when the display element is formed by the inkjet method can be made constant within the actual display region 62, and the peripheral portion of the actual display region 62 can be formed. Therefore, there is no possibility that the thickness of the light emitting layer 50 is uneven.

Next, the cathode 26 is formed on the entire surface of the actual display area 62 and the dummy area 63 and the dummy area 63.
Of the dummy region 63 extending over the substrate 60 outside the
Outside the display pixel portion 61, that is, outside the display pixel portion 61
It is arranged to face No. 3. Further, the end portion of the cathode 26 is connected to the cathode wiring 26 a formed on the circuit portion 11. The cathode 26 functions as a counter electrode of the pixel electrode 51 and causes a current to flow in the light emitting layer 50. The cathode 26 is configured by laminating a cathode layer 26b made of a laminated body of lithium fluoride and calcium and a reflecting layer 26c, for example. Of the cathode 26, only the reflective layer 26c is included in the display pixel portion 6
It is extended to the outside of 1. The reflective layer 26c reflects the light emitted from the light emitting layer 50 to the substrate 60 side, and is preferably made of, for example, Al, Ag, a Mg / Ag laminated body or the like. Further, a protective layer made of SiO ₂ , SiN or the like for preventing oxidation may be provided on the reflective layer 26c.

Further, as shown in FIG. 4, the relay substrate 30 is fixed to one end of the substrate 60 using the anisotropic conductive film 40 described above. The semiconductor chip 33 mounted on the relay board 30 includes the data side drive circuit 33 shown in FIG.
a, a cathode power supply circuit 33b, and a light emission power supply circuit 33c
Is built in. A portion surrounded by a broken line in FIG. 4 shows a fixed portion between the display substrate 20 and the relay substrate 30. Figure 6
[FIG. 5] is a top view of the vicinity of a fixed portion 65 shown in FIG. 4. still,
In FIG. 6, the illustration of the anisotropic conductive film 40 and the relay substrate 30 is omitted.

As shown in FIG. 6, in the fixing portion 65, a first external connection terminal having a width similar to the width of the wiring is provided for each wiring having a small line width, and for the wiring having a wide width. In other words, a plurality of second external connection terminals having a width smaller than the line width are provided. For example, for each of the scanning line drive circuit control signal wirings 24a having a small line width, the first external connection terminals 67, 68 having the same width as the scanning line drive circuit control signal wiring 24a are formed. 69 is provided. On the other hand, for the light emitting power supply wiring 23R having a wide width, the light emitting power supply wiring 23R
Second external connection terminals 66a, 66 having a width narrower than the line width of R
b and 66c are provided. Further, for the signal line 22 whose width is narrower than that of the scanning line drive circuit control signal wiring 24a,
The second external connection terminal 7 having the same line width as the signal line 22.
0 is provided for each. The numbers of the first external connection terminals and the second external connection terminals are appropriately set according to the line width of the wiring formed on the substrate 60.

As described above, the number of the first external connecting terminals and the second external connecting terminals is changed according to the line width of the wiring formed on the substrate 60. This is to make them the same. That is, as described with reference to FIGS. 1 and 2, the display substrate 10 and the relay substrate 20 are fixed to each other by the anisotropic conductive film 40, but the fixing conditions (for example, terminal width, bonding area, pressure The electrical resistance inside the fixing portion 65 varies depending on the position thereof. If the electric resistance of the fixing portion 65 differs depending on the position, display problems such as display unevenness and contrast reduction occur. For this reason, in the fixing portion 65, the crimping conditions are made as uniform as possible by changing the number of external connection terminals according to the line width of the wiring formed on the substrate 60. Furthermore, by providing multiple external connection terminals,
The adhesion area can be increased. That is, since the anisotropic conductive film can be arranged between the plurality of external connection terminals, firm adhesion can be achieved.

Next, the structure of the external connection terminal formed on the fixing portion 65 will be described in detail. FIG. 7 shows B in FIG.
FIG. 9 is a cross-sectional view of the second external connection terminal 66c and the second external connection terminal 70 taken along the line −B ′, and FIG. 8 is an enlarged view of the external connection terminal 70 in FIG. 7. As shown in FIGS. 7 and 8,
A base protective layer 281 is formed on the substrate 60, and a gate insulating layer 71 mainly composed of SiO ₂ and / or SiN is formed on the base protective layer 281. The gate insulating layer 71 is formed to electrically insulate a channel region and a gate electrode of a thin film transistor (not shown). In addition, in this specification, the component which is “mainly” means the component having the highest content rate.

A signal line 22 and a light-emitting power source wiring 23R are formed on the gate insulating layer 71, and the signal line 22 is further formed.
A second interlayer insulating layer 283 is formed on the light-emitting power source wiring 23R. The light-emitting power source wiring 23 and the scanning line driving circuit control signal wiring 24a are the scanning lines 2 shown in FIG.
It is formed at the same time as 1.

The signal line 2 is formed on the second interlayer insulating layer 283.
2 and a plurality of contact holes H are formed at positions above the light-emitting power source wiring 23R. Also, the power supply wiring 2 for light emission
The electrode 73 is formed on the second interlayer insulating layer 283 above 3R, and the electrodes 74 and 75 are formed on the second interlayer insulating layer 283 above the signal line 22.

Since these electrodes 73, 74 and 75 are formed by the sputtering method after forming the contact hole H, the surface of the electrode 73, 74 and 75 is formed by the metal material deposited in the contact hole H above the contact hole H. A concave portion B is formed at. In this way, the contact hole H
Through, the electrical connection between the light-emitting power supply wiring 23R covered with the second interlayer insulating layer 283 and the electrode 74 formed on the second interlayer insulating layer 283, and the signal covered with the second interlayer insulating layer 283. The line 22 and the electrodes 74 and 75 formed on the second interlayer insulating layer 283 are electrically connected.

Further, the ends and sides of the electrodes 73, 74, 75 formed on the second interlayer insulating layer 283 and the spaces between these electrodes 73, 74, 75 are intended to be electrically insulated. A first interlayer insulating layer 284 made of an inorganic material such as SiN is formed. A transparent electrode 77 made of ITO or the like is formed on the upper portion, the side portion, and the peripheral portion of the electrodes 73, 74, 75, and the transparent electrode 77 and the second external portion formed on the peripheral portion of the electrodes 73, 74, 75. A protective layer 78 made of SiO ₂ is formed between the connection terminals 66c, 70, 70.
The electrodes 73, 74 and 75 are formed at the same time as the gate line shown in FIG. 3, and the transparent electrode 77 is made of ITO.
And is formed at the same time as the pixel electrode (anode).

As shown in FIGS. 7 and 8, the second external connection terminals 66c, 7 provided in the electro-optical device of this embodiment.
A plurality of recesses B are formed on the surfaces of the first and second external connection terminals 66c and 7c.
0 and 70 are divided into a plurality of electrodes, so to speak. As shown in FIG. 6, the number of external connection terminals is changed in accordance with the line widths of the light-emitting power source wiring 23R and the signal line 22, thereby making the fixing conditions in the fixing portion 65 uniform. Since the plurality of concave portions B are formed on the surfaces of the external connection terminals 66c, 70, 70, the second external connection terminals 66c, 70, 70 are further divided into a plurality of electrodes, and the fixing conditions are made uniform. It is extremely suitable for the purpose.

In addition, the electrodes 73, 74, 75 are provided with a first
By forming the interlayer insulating layer 284, the convex portion 79 is formed at the end portion of the second external connection terminal 66c, 70, 70. In the convex portion 79, when the display substrate 10 and the relay substrate 20 are fixed to each other by using the anisotropic conductive film 40, the conductive particles 41b included in the anisotropic conductive film 40 serve as the second external connection terminal 66.
c, 70, 70 to prevent the protrusion of the side. As a result, more conductive particles 41b are arranged on the second external connection terminals 66c, 70, 70, which is an extremely excellent structure for reducing the electrical resistance in the fixing portion 65.

The display substrate 20 of this embodiment described above
Since the fixing portion 65 is provided with a structure for equalizing the pressure bonding conditions, the external connection terminals 34 formed on the relay substrate 30 fixed to the fixing portion 65 are the light-emitting power supply wirings shown in FIG. 23R and the scanning line drive circuit control signal wiring 24a and the like may have the same line width. However, in order to fix the relay substrate 30 and the display substrate 20 under a more uniform pressure bonding condition, it is preferable that the pattern is the same as that of the second external connection terminals 66c, 70, 70 and the like formed on the fixing portion 65. Is.

By the way, the second interlayer insulating layer 2 shown in FIG.
The parasitic capacitance between the various wirings formed on 83 and the cathode 26 formed so as to cover the upper portions of the actual display area 62 and the dummy area 63 (opposite side to the substrate 60 side) is reduced to display unevenness. Also, in order to reduce display defects such as reduction in contrast as much as possible, there is a tendency to increase the thickness of the first interlayer insulating layer 284.

FIG. 9 is an enlarged view of the second external connection terminals 70, 70 in which the first interlayer insulating layer 284 is formed thick. As shown in FIG. 9, when the thickness of the first interlayer insulating layer 284 between the electrodes 74 and 75 is increased, the first external connection terminal 7 is removed.
The height of the convex portion 79 formed at the end portions of 0 and 70 is higher than the height of the convex portion 79 shown in FIG. still,
In FIGS. 7 and 8, the first interlayer insulating layer 284 is made of Si.
Although it was formed from N, in FIG. 9, the first interlayer insulating layer 2 is formed.
84 is formed using SiO ₂ .

As shown in FIG. 9, the first interlayer insulating layer 284 is formed.
By increasing the thickness of the electrodes 74 and 75, the height of the protrusions 79 formed at the ends of the electrodes 74 and 75 is increased, and the thickness between the electrodes 74 and 75 and the transparent electrode 77 is reduced. Also, the second
When the first interlayer insulating layer 284 is formed directly on the interlayer insulating layer 283 and the electrodes 74 and 75, the protrusions 79 formed at the end portions of the electrodes 74 and 75 are not only on the electrodes 74 and 75 but also on the first layer. The shape is also projected to the surface of the first interlayer insulating layer 284 between the external connection terminals 70, 70, the flatness is impaired, and a problem occurs when the relay substrate 30 is fixed using the anisotropic conductive film 40. May occur.

In order to prevent such a problem, a flattening film for flattening the unevenness formed by the electrodes 74 and 75 is provided in this embodiment. FIG. 10 is an enlarged view of the first external connection terminals 70, 70 in which the first interlayer insulating layer 284 is formed thick and the flattening film is provided between the electrodes 74, 75. The flattening film 80 is a first interlayer insulating layer 284.
Before the formation of, the electrode 74, the electrode 75, and the like are formed on a portion other than the portion where the electrodes are formed.

Referring to FIG. 10, by forming the first interlayer insulating layer 284 after forming the planarizing film 80,
It can be seen that the height difference (step) between the surface of the first interlayer insulating layer 284 and the convex portion 79 between the first external connection terminals 70, 70 becomes small. Therefore, no problem occurs when the relay substrate 30 is fixed by using the anisotropic conductive film 40.

The electro-optical device according to the embodiment of the present invention has been described above.
By incorporating an electronic component such as a motherboard having a CPU (central processing unit), a keyboard, a hard disk, etc. in a housing, for example, a laptop personal computer 600 (electronic device) shown in FIG. 11 is manufactured. Figure 11
FIG. 6 is a diagram showing an example of an electronic apparatus including the electro-optical device according to the embodiment of the invention. Incidentally, in FIG.
Is a housing, 602 is a liquid crystal display device, and 603 is a keyboard. FIG. 12 is a perspective view showing a mobile phone as another electronic device. The mobile phone 700 shown in FIG. 12 includes an antenna 701, a receiver 702, and a transmitter 7.
03, a liquid crystal display device 704, an operation button unit 705, and the like.

Further, in the above-described embodiment, a notebook computer and a mobile phone are taken as examples of the electronic equipment, but the electronic equipment is not limited to these, and a liquid crystal projector, a multimedia compatible personal computer (PC) and an engineering workstation. (EWS), pager, word processor, television, viewfinder type or monitor direct-view type video tape recorder, electronic notebook, electronic desk calculator, car navigation device, POS terminal,
It is possible to apply to electronic equipment such as a device provided with a touch panel.

[0070]

As described above, according to the present invention,
Flattening films are provided between the first terminals, between the second terminals, and between the first terminals and the second terminals, and on the flattening films, on the end portions of the first terminals and the end portions of the second terminals. Since the insulating film is formed, even if the thickness of the insulating layer is increased, the height of the insulating layer formed at the end of the first terminal and the end of the second terminal is formed on the flattening film. There is an effect that the flatness can be ensured without being so much higher than the surface of the insulating layer. As a result, there is an effect that a connection failure of the wiring connected to the first terminal and the second terminal does not occur.

[Brief description of drawings]

FIG. 1 is an exploded perspective view schematically showing an electro-optical device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing how the relay substrate 30 and the display substrate 20 are fixed to each other by the anisotropic conductive film 40.

FIG. 3 is a diagram schematically showing a wiring structure of an electro-optical device according to an embodiment of the present invention.

FIG. 4 is a schematic plan view of the electro-optical device according to the present embodiment.

5 is a cross-sectional view taken along the line AA ′ of FIG.

6 is a top view of the vicinity of a fixed portion 65 shown in FIG.

7 is a cross-sectional view of the second external connection terminal 66c and the second external connection terminal 70 taken along the line BB 'in FIG.

8 is an enlarged view of the external connection terminal 70 in FIG.

9 is an enlarged view of second external connection terminals 70, 70 in which a first interlayer insulating layer 284 is formed thick.

FIG. 10 shows a first interlayer insulating layer 284 having a large thickness and a flattening film provided between electrodes 74 and 75.
It is an enlarged view of external connection terminals 70 and 70.

FIG. 11 is a diagram showing an example of an electronic apparatus including the electro-optical device according to the embodiment of the invention.

FIG. 12 is a perspective view showing a mobile phone as another electronic device.

FIG. 13 is a diagram showing a wiring structure of a conventional electro-optical device.

[Explanation of symbols]

10 ... Electro-optical device 22 ... Signal line (first wiring) 23, 23R ... Power source wiring for light emission (second wiring, power source line) 24a ... Control signal wiring for scanning line drive circuit (first wiring) 30 ... Relay board 40 ... Anisotropic conductive film 50 ... Light emitting element 53 ... Switching element 66a, 66b, 66c ... Electrode (second terminal) 67, 68, 69, 70 ... Electrode (first terminal) 284: First interlayer insulating layer (insulating layer) 79 ... Convex 80: Flattening film B: recess

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G02F 1/1368 G02F 1/1368 5G435 G09F 9/00 348 G09F 9/00 348L H05B 33/06 H05B 33/06 33/12 33/12 B 33/14 33/14 A 33/22 33/22 ZF term (reference) 2H088 EA22 HA02 MA02 MA20 2H090 HA04 HD03 JA05 JB02 JC07 LA01 2H092 GA33 GA40 GA48 GA50 HA18 HA26 JA24 NA01 NA25 3K007 AB17 CC05 DB03 5C094 AA03 BA29 CA19 CA24 DA15 DB02 FA01 FA04 FB15 HA08 5G435 AA01 BB05 CC09 CC12 EE40 EE42 HH14 LL07 LL08

Claims (10)

[Claims] 1. An electro-optical device having at least a first wire and a second wire wider than the first wire, wherein a first terminal for external connection connected to the first wire, A plurality of second terminals for external connection connected to the second wiring, a flattening film provided between the first terminals, between the second terminals, and between the first terminals and the second terminals. And an second insulating layer formed on the flattening film, on the end of the first terminal, and on the end of the second terminal. 2. The electro-optical device according to claim 1, wherein a convex portion is formed by the second insulating layer at an end portion of the first terminal and the second terminal. 3. The electro-optical device according to claim 1, wherein a plurality of recesses are formed in the first terminal and the second terminal. 4. A first wiring having a width similar to that of the first wiring.
Relay wiring and a second relay wiring having a width similar to that of the second wiring are formed, and the first wiring and the first relay wiring are electrically connected via the first terminal, The second through the second terminal
The electro-optical device according to claim 1, further comprising a relay board in which the wiring and the second relay wiring are electrically connected. 5. An electro-optical device having a plurality of light emitting elements, and a switching element for supplying a current supplied through a power supply line to the light emitting element in response to a signal supplied through a signal line. A first terminal for external connection connected to the signal line, a plurality of second terminals for external connection formed wider than the width of the signal line and connected to the power supply line, the first terminal Between the second terminals, and between the first terminal and the second terminal, and on the flattening film, the end portion of the first terminal, and the second terminal. An electro-optical device comprising: an insulating layer formed on an end portion. 6. The electro-optical device according to claim 5, wherein convex portions are formed by the insulating layer at end portions of the first terminal and the second terminal. 7. The electro-optical device according to claim 5, wherein a plurality of recesses are formed in the first terminal and the second terminal. 8. A first wiring having a width similar to that of the signal line and a second wiring having a width similar to that of the power supply line are formed, and the signal line and the wiring are connected via the first terminal. 8. The relay board, which is electrically connected to the first wiring, and electrically connected to the power supply line and the second wiring via the second terminal. The electro-optical device described. 9. The electro-optical device according to claim 8, wherein the first and second terminals and the first and second wirings are fixed by an anisotropic conductive film. 10. An electronic apparatus comprising the electro-optical device according to claim 1. Description: