JP2003209228A - Magnetic memory device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic memory device in which variations of diode characteristics can be prevented, and a method of manufacturing the same. <P>SOLUTION: This magnetic memory device includes an SOI substrate 14, element isolation insulating film 15 which has a depth from the surface of a second semiconductor layer 12 up to a first insulating film 13 and is formed selectively in the second semiconductor layer 12, switching element 10 formed in the second semiconductor layer 12, MTJ element 31 connected to this switching element 10, first wiring 28b disposed below the MTJ element 31 distantly from this MTJ element 31, and second wiring 32 formed on the MTJ element 31. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic memory device and a method of manufacturing the same, and more particularly to a tunnel magnetic resistance (Tunn).
"1", "0" due to the effect of eling Magneto Resistive
MTJ (Magnetic Tunnel Junction) that stores information on
Magnetic Random Access Memor (MRAM: Magnetic Random Access Memor)
y) concerning.

[0002]

2. Description of the Related Art In recent years, many memories for storing information have been proposed based on a new principle. One of them is
Magnetic Random Access Memory (Magnetic R) that utilizes the Tunneling Magneto Resistive effect
andom Access Memory: hereinafter referred to as MRAM) (for example, refer to Non-Patent Document 1).

18 (a), 18 (b), 18 (c)
Is a conventional magnetic storage device MTJ (Magnetic T
A sectional view of the unnel junction device is shown. Below, MRAM
The MTJ element used as the storage element will be described.

As shown in FIG. 18A, the MTJ element 3
1 has a structure in which an insulating layer (tunnel junction layer) 42 is sandwiched between two magnetic layers (ferromagnetic layers) 41 and 43. M
In the RAM, the MTJ element 31 causes "1",
Information of "0" is stored. The information of "1" and "0" is determined depending on whether the magnetization directions of the two magnetic layers 41 and 43 in the MTJ element 31 are parallel or antiparallel.
Here, “parallel” means that the magnetization directions of the two magnetic layers 41 and 43 are the same, and “antiparallel” means that the magnetization directions of the two magnetic layers 41 and 43 are antiparallel. means.

That is, as shown in FIG. 18B, when the magnetization directions of the two magnetic layers 41 and 43 are parallel,
The tunnel resistance of the insulating layer 42 sandwiched between these two magnetic layers 41 and 43 is the lowest. This state is, for example, the state of "1". On the other hand, as shown in FIG. 18C, when the magnetization directions of the two magnetic layers 41 and 43 are antiparallel, the tunnel resistance of the insulating layer 42 sandwiched between these two magnetic layers 41 and 43 is , The highest. This state is, for example, a "0" state.

An antiferromagnetic layer 103 is usually disposed on one side of the two magnetic layers 41 and 43. The antiferromagnetic layer 103 is a member for easily rewriting information by fixing the magnetization direction of the magnetic layer 41 on one side and changing only the magnetization direction of the magnetic layer 43 on the other side.

FIG. 19 shows MTJ elements arranged in a matrix of a conventional magnetic memory device. Figure 20
Shows the asteroid curve of a magnetic storage device according to the prior art. FIG. 21 shows an MTJ of a conventional magnetic storage device.
A curve is shown. The principle of the write operation for the MTJ element will be briefly described below.

As shown in FIG. 19, the MTJ element 31 has
The write word line 28 and the bit line (data selection line) 32 intersect each other at the intersection. For writing data, a current is passed through each of the write word line 28 and the bit line 32, and the magnetic field generated by the currents flowing through the both wirings 28, 32 is used to change the magnetization direction of the MTJ element 31 in parallel or reverse direction. It is achieved by making them parallel.

For example, at the time of writing, only a current I1 flowing in one direction is passed through the bit line 32, and the write word line 2
Currents I2 and I3 flowing in one direction or in the other direction depending on the write data are passed through 8. Here, write word line 2
When a current I2 flowing in one direction flows through the MTJ element 3
The magnetization directions of 1 are parallel (state of "1"). On the other hand, when the current I3 flowing in the other direction is passed through the write word line 28, the magnetization directions of the MTJ element 31 are antiparallel (state of "0").

The mechanism by which the magnetization direction of the MTJ element 31 changes in this way is as follows. That is, when a current is passed through the selected write word line 28, the MTJ element 31
The magnetic field Hx is generated in the long-side direction, that is, in the Easy-Axis (easy axis) direction. When a current is passed through the selected bit line 32, the short side direction of the MTJ element 31, that is, Har
A magnetic field Hy is generated in the d-Axis (hard axis) direction. As a result, the MTJ element 31 located at the intersection of the selected write word line 28 and the selected bit line 32 has magnetic fields Hx and Hard-A in the Easy-Axis direction.
A combined magnetic field with the magnetic field Hy in the xis direction is applied.

Here, as shown in FIG. 20, Easy-
When the magnitude of the combined magnetic field of the magnetic field Hx in the Axis direction and the magnetic field Hy in the Hard-Axis direction is outside the asteroid curve indicated by the solid line (hatched portion), the magnetic layer 43.
The magnetization direction of can be reversed. Conversely, Eas
When the magnitude of the combined magnetic field of the magnetic field Hx in the y-Axis direction and the magnetic field Hy in the Hard-Axis direction is inside the asteroid curve (blank part), the magnetization direction of the magnetic layer 43 is reversed. I can't.

Further, as shown by the solid and dotted lines in FIG. 21, Ea required to change the resistance value of the MTJ element 31 depending on the magnitude of the magnetic field Hy in the Hard-Axis direction.
The magnitude of the magnetic field Hx in the sy-Axis direction also changes. By utilizing this phenomenon, the MTJ element 3 existing at the intersection of the selected write word line 28 and the selected bit line 32 among the memory cells arranged in an array.
The resistance value of the MTJ element 31 can be changed by changing the magnetization direction of only 1.

The rate of change of the resistance value of the MTJ element 31 is
It is represented by an MR (Magneto Resistive) ratio. For example, E
When the magnetic field Hx is generated in the asy-Axis direction, MT
The resistance value of the J element 31 changes by, for example, about 17% as compared with that before the magnetic field Hx is generated, and the MR ratio in this case is 17%.
Becomes This MR ratio changes depending on the properties of the magnetic layer, and currently, an MTJ element having an MR ratio of about 50% is also obtained.

As described above, by changing the magnitudes of the magnetic field Hx in the Easy-Axis direction and the magnetic field Hy in the Hard-Axis direction, and changing the magnitude of the combined magnetic field, the direction of magnetization of the MTJ element 31 is changed. Controlled. In this way, a state in which the magnetization directions of the MTJ element 31 are parallel or a state in which the magnetization directions of the MTJ element 31 are antiparallel can be created, and information "1" or "0" can be stored.

FIG. 22 is a sectional view of a magnetic memory device having a transistor according to the related art. FIG. 23 shows a cross-sectional view of a magnetic memory device including a diode according to the related art. The operation of reading the information stored in the MTJ element will be briefly described below.

Data can be read by passing a current through the selected MTJ element 31 and detecting the resistance value of the MTJ element 31. This resistance is M
It changes when a magnetic field is applied to the TJ element 31. The resistance value changed in this way is read by the following method.

For example, FIG. 22 shows an example in which a MOSFET 64 is used as a switching element for reading. As shown in FIG. 22, in one cell, the MTJ element 31 has M
The source / drain diffusion layer 63 of the OSFET 64 is connected in series. Then, by turning on the gate of an arbitrary MOSFET 64, the bit line 32 to the MTJ element 31
-Lower electrode 30-Contact 29-Second wiring 28-Contact 27-First wiring 26-Contact 25-Source / drain diffused layer 63 A current path can be formed and an MTJ element connected to the turned-on MOSFET 64. The resistance value of 31 can be read.

FIG. 23 shows an example in which a diode 73 is used as a switching element for reading. FIG. 23
As shown in FIG. 1, in one cell, one MTJ element 31 is connected in series to a diode 73 composed of a P ⁺ -type first diffusion layer 71 and an N ⁻ -type second diffusion layer 72. . The resistance value of the MTJ element 31 connected to the diode 73 can be read by adjusting the bias voltage so that the current flows through the arbitrary diode 73.

As described above, as a result of reading the resistance value of the MTJ element 31, it can be determined that the information "1" is written when the resistance value is low and the information "0" is written when the resistance value is high.

[0020]

[Non-Patent Document 1] Roy Scheuerlein, et al., A 10ns Re
ad and Write Non-Volatile Memory Array Using a Mag
netic Tunnel Junction and FET Switch in each Cel
l, “2000 ISSCC Digest of Technical Papers”, (USA), February 2000, p.128-129

[0021]

In the magnetic storage device according to the above-mentioned conventional technique, the switching element is formed on the bulk substrate 61. Therefore, in the magnetic memory device using the diode 73 as the switching element, as shown in FIG. 23, the element isolation region 6 is electrically separated from the adjacent cell.
N ⁻ -type second diffusion layer 72 so as to be shallower than the bottom surface of
Is formed, and the P ⁺ -type first diffusion layer 71 is formed on the surface of the N ⁻ -type second diffusion layer 72. Therefore, when the diode 73 is formed using the bulk substrate 61,
The P ⁺ -type first diffusion layer 71 had to be formed very shallow. However, it is very difficult in the process to form the P ⁺ -type first diffusion layer 71 shallowly, and it is difficult to obtain uniform diode characteristics.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a magnetic memory device capable of suppressing variations in diode characteristics and a manufacturing method thereof. .

[0023]

The present invention uses the following means in order to achieve the above object.

A magnetic memory device according to a first aspect of the present invention is a first semiconductor layer, a first insulating film formed on the first semiconductor layer, and a first insulating film formed on the first insulating film. An SOI substrate having an exposed second semiconductor layer, and a depth reaching the first insulating film from the surface of the second semiconductor layer, and selectively formed in the second semiconductor layer. Element isolation insulating film, a switching element formed on the second semiconductor layer, a magnetoresistive effect element connected to the switching element, and a space below the magnetoresistive effect element and separated from the magnetoresistive effect element. Formed on the magnetoresistive effect element and a first wiring extending in a first direction,
And a second wiring extending in a second direction different from the first direction.

According to a second aspect of the present invention, there is provided a method of manufacturing a magnetic memory device, comprising: a first semiconductor layer, a first insulating film arranged on the first semiconductor layer, and the first insulating film. Forming an SOI substrate having a second semiconductor layer disposed thereabove, and a depth of reaching the first insulating film from the surface of the second semiconductor layer in the second semiconductor layer. Selectively forming an element isolation insulating film having: a step of forming a switching element in the second semiconductor layer; a step of forming a first wiring extending in a first direction; A step of forming a magnetoresistive effect element which is connected to the switching element above the first wiring and is separated from the first wiring; and a second step different from the first direction on the magnetoresistive effect element. And forming a second wiring extending in the direction.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION In the embodiments of the present invention, a magnetic storage device (MRAM: Magnetic Ran) using an MTJ (Magnetic Tunnel Junction) element utilizing a tunneling magnetoresistive (Tunneling Magneto Resistive) effect as a storage element.
dom Access Memory).

Embodiments of the present invention will be described below with reference to the drawings. In this description, common reference numerals are given to common portions throughout the drawings.

[First Embodiment] In the first embodiment, S
This is an example in which a diode is formed using an OI (Silicon On Insulator) substrate and the potential of the gate electrode is fixed.

FIG. 1 is a sectional view of a magnetic memory device according to the first embodiment of the present invention. FIG. 2 is a schematic circuit diagram of the magnetic memory device according to the first embodiment of the present invention.

As shown in FIGS. 1 and 2, in the magnetic memory device according to the first embodiment, the first and second semiconductor layers 11 and
12 and an embedded oxide film 13 formed between the first and second semiconductor layers 11 and 12
4 is used. In this SOI substrate 14, for example, an element isolation region 15 having an STI (Shallow Trench Isolation) structure is selectively formed from the surface of the second semiconductor layer 12 to a depth reaching the buried oxide film 13, and for each cell. A second semiconductor layer 12 surrounded by the buried oxide film 13 and the element isolation region 15 is formed. This insulating film 13,
A gate electrode 17 is selectively formed on the second semiconductor layer 12 surrounded by 15 via a gate insulating film 16. The gate electrode 17 is fixed to a predetermined potential, for example, the ground potential. Then, a P ⁺ -type first diffusion layer 19 is formed in the second semiconductor layer 12 at one end of the gate electrode 17, and an N ⁺ -type first diffusion layer 19 is formed in the second semiconductor layer 12 at the other end of the gate electrode 17. Two diffusion layers 21 are formed. In this way, the so-called gate control type diode 10 is formed on the SOI substrate 14.

Further, the first diffusion layer 19 of the diode 10
The first to fourth contacts 23a, 25, 27,
An MTJ element 31 is connected in series via 29, the first to third wirings 24 a, 26, 28 a and the lower electrode 30. A bit line 32 is connected to the MTJ element 31, and a write word line 28b formed of a third wiring is arranged below the MTJ element 31 so as to be separated from the MTJ element 31.

In addition, the second diffusion layer 21 of the diode 10
Is connected to a first contact 23b and a first wiring 24b, and the first wiring 24b is connected to a peripheral circuit (not shown).

As described above, the MTJ element 31 has the magnetization pinned layer (magnetic layer) 41 whose magnetization direction is fixed, the tunnel junction layer (nonmagnetic layer) 42, and the magnetic recording layer whose magnetization direction is reversed. (Magnetic layer) 43 and at least three layers. The MTJ element 31 has a single tunnel junction structure composed of one tunnel junction layer 42 or a double tunnel junction structure composed of two tunnel junction layers 42. Hereinafter, examples of the MTJ element 31 having a single tunnel junction structure or a double tunnel junction structure will be described.

The MTJ element 31 of the single tunnel junction structure shown in FIG. 3A is a magnetization fixed layer in which a template layer 101, an initial ferromagnetic layer 102, an antiferromagnetic layer 103 and a reference ferromagnetic layer 104 are laminated in this order. 41, a tunnel junction layer 42 formed on the magnetization fixed layer 41, and a magnetic recording layer 43 in which a free ferromagnetic layer 105 and a contact layer 106 are sequentially stacked on the tunnel junction layer 42.

The MTJ element 31 having the single tunnel junction structure shown in FIG. 3B has a template layer 101, an initial ferromagnetic layer 102, an antiferromagnetic layer 103, a ferromagnetic layer 104 ', a nonmagnetic layer 107, and a ferromagnetic layer. A magnetic pinned layer 41 in which layers 104 ″ are sequentially stacked, a tunnel junction layer 42 formed on the magnetic pinned layer 41, a ferromagnetic layer 105 ′, a nonmagnetic layer 107, and a ferromagnetic layer on the tunnel junction layer 42. The layer 105 ″ and the contact layer 106 are formed in this order on the magnetic recording layer 43.

In the MTJ element 31 shown in FIG. 3B, the ferromagnetic layer 104 'and the non-magnetic layer 1 in the magnetization pinned layer 41.
07, the three-layer structure including the ferromagnetic layer 104 ″ and the three-layer structure including the ferromagnetic layer 105 ′, the non-magnetic layer 107, and the ferromagnetic layer 105 ″ in the magnetic recording layer 43 are introduced.
As compared with the MTJ element 31 shown in (a), it is possible to suppress the generation of magnetic poles inside the ferromagnetism and provide a cell structure suitable for further miniaturization.

The MTJ element 31 having the double tunnel junction structure shown in FIG. 4A has a first layer in which a template layer 101, an initial ferromagnetic layer 102, an antiferromagnetic layer 103, and a reference ferromagnetic layer 104 are sequentially stacked. Magnetization pinned layer 41a and first tunnel junction layer 4 formed on this first magnetization pinned layer 41a.
2a, the magnetic recording layer 43 formed on the first tunnel junction layer 42a, the second tunnel junction layer 42b formed on the magnetic recording layer 43, and the second tunnel junction layer 42b. The reference ferromagnetic layer 104 and the antiferromagnetic layer 10
3, an initial ferromagnetic layer 102, and a second magnetization pinned layer 41b in which a contact layer 106 is sequentially stacked.

In the MTJ element 31 having the double tunnel junction structure shown in FIG. 4B, the template layer 101, the initial ferromagnetic layer 102, the antiferromagnetic layer 103, and the reference ferromagnetic layer 104 are laminated in this order to obtain the first magnetization. The pinned layer 41a and the first tunnel junction layer 42 formed on the first magnetization pinned layer 41a.
a and the ferromagnetic layer 4 on the first tunnel junction layer 42a.
3 ', non-magnetic layer 107, ferromagnetic layer 43 ", a magnetic recording layer 43 sequentially laminated by a three-layer structure, a second tunnel junction layer 42b formed on the magnetic recording layer 43, and a second tunnel junction layer 42b. On the tunnel junction layer 42b of the ferromagnetic layer 104 ',
Nonmagnetic layer 107, ferromagnetic layer 104 ″, antiferromagnetic layer 10
3, an initial ferromagnetic layer 102, and a second magnetization pinned layer 41b in which a contact layer 106 is sequentially stacked.

In the MTJ element 31 shown in FIG. 4B, a three-layer structure of a ferromagnetic layer 43 ', a non-magnetic layer 107 and a ferromagnetic layer 43 "constituting the magnetic recording layer 43, and a second magnetization. By introducing the three-layer structure including the ferromagnetic layer 104 ′, the nonmagnetic layer 107, and the ferromagnetic layer 104 ″ in the pinned layer 41b,
As compared with the MTJ element 31 shown in FIG. 4A, it is possible to provide a cell structure that suppresses the generation of magnetic poles inside the ferromagnetic material and is more suitable for miniaturization.

MTJ having such a double tunnel junction structure
The element 31 has an MR (Magnet) when the same external bias is applied as compared with the MTJ element 31 having a single tunnel junction structure.
o Resistive) Ratio (rate of change of resistance between "1" state and "0" state) is small, and a higher bias can be operated. That is, the double tunnel junction structure is advantageous when reading information in the cell.

The MTJ element 31 having such a single tunnel junction structure or double tunnel junction structure is formed by using, for example, the following materials.

The materials of the magnetization pinned layers 41, 41a, 41b and the magnetic recording layer 43 are, for example, Fe, Co, Ni or their alloys, magnetite having a large magnetization polarizability, and Cr.
O ₂ , RXMnO _3-y (R: rare earth, X: Ca, Ba,
In addition to oxides such as Sr), NiMnSb, PtMnSb
It is preferable to use a Heusler alloy or the like. In addition, these magnetic materials must have A
g, Cu, Au, Al, Mg, Si, Bi, Ta, B,
C, O, N, Pd, Pt, Zr, Ir, W, Mo, Nb
Some non-magnetic elements such as

The material of the antiferromagnetic layer 103 forming part of the magnetization pinned layers 41, 41a, 41b is Fe--Mn, P.
t-Mn, Pt-Cr-Mn, Ni-Mn, Ir-M
It is preferable to use n, NiO, Fe ₂ O ₃ or the like.

The tunnel junction layers 42, 42a and 42b are made of Al ₂ O ₃ , SiO ₂ , MgO, AlN and Bi.
₂ O ₃ , MgF ₂ , CaF ₂ , SrTiO ₂ , AlLa
Various dielectrics such as O ₃ can be used. Oxygen, nitrogen and fluorine deficiencies may be present in these dielectrics.

5 to 7 are sectional views showing the steps of manufacturing the magnetic memory device according to the first embodiment of the present invention. The method of manufacturing the magnetic memory device according to the first embodiment of the present invention will be briefly described below.

As shown in FIG. 5, an SO composed of, for example, a P-type first semiconductor layer 11, a second semiconductor layer 12, and a buried oxide film 13 made of, for example, a silicon oxide film.
The I substrate 14 is used. First, the element isolation region 15 having the STI structure is selectively formed so as to reach the buried oxide film 13 from the surface of the second semiconductor layer 12. Next, ion implantation and thermal diffusion are performed in the second semiconductor layer 12,
For example, the P-type second semiconductor layer 12 is formed. The second semiconductor layer 12 may be N-type. Next, the gate electrode 17 is selectively formed on the second semiconductor layer 12 via the gate insulating film 16.

Next, as shown in FIG. 6, the gate electrode 17
Then, a photoresist 18 is applied on the second semiconductor layer 12, and the photoresist 18 is formed into a desired pattern. With the photoresist 18 as a mask, the second
Ion implantation and thermal diffusion are performed in the semiconductor layer 12.
As a result, the P ⁺ -type first diffusion layer 19 is formed in the second semiconductor layer 12 at one end of the gate electrode 17. Then, the photoresist 18 is removed.

Next, as shown in FIG. 7, the gate electrode 17
Then, a photoresist 20 is applied on the second semiconductor layer 12, and the photoresist 20 is formed into a desired pattern. With the photoresist 20 as a mask, the second
Ion implantation and thermal diffusion are performed in the semiconductor layer 12.
As a result, the N ⁺ -type second diffusion layer 21 is formed in the second semiconductor layer 12 at the other end of the gate electrode 17,
The diode 10 is formed. Then, the photoresist 20 is removed.

Next, as shown in FIG. 1, the gate electrode 1
7, the insulating film 22 is formed on the second semiconductor layer 12 and the element isolation region 15. Next, using known techniques, the first to fourth contacts 23a, 23 are formed in the insulating film 22.
b, 25, 27, 29 and the first to third wirings 24a,
24b, 26, 28a, 28b are formed. here,
The first to fourth contacts 23a, 25, 27, 27 and the first to third wirings 24a, 26, 28a are connected to the first diffusion layer 19, and the first contact 23b and the first contact 23b.
The wiring 24b of is connected to the second diffusion layer 21. Also,
The third wiring 28b functions as a write word line. Next, the lower electrode 30 is formed on the fourth contact 29, and the write word line 28b on the lower electrode 30 is formed.
The MTJ element 31 is formed above. And this M
The bit line 32 is formed on the TJ element 31.

Incidentally, the first diffusion layer 19 and the second diffusion layer 21.
Either of them may be formed first, and the second diffusion layer 21 may be formed first.

According to the first embodiment described above, since the diode 10 is formed using the SOI substrate 14, the second
The semiconductor layer 12 is surrounded by the buried oxide film 13 and the element isolation region 15 under the second semiconductor layer 12 for each cell. That is, each cell has an adjacent cell and the buried oxide film 13.
And the element isolation regions 15 electrically separate. Therefore, unlike the conventional case, it is not necessary to adjust the depths of the first and second diffusion layers 19 and 21 in order to electrically separate the adjacent cells, so that variations in diode characteristics can be suppressed.

Further, if the diode 10 is formed by using the SOI substrate 14, the first and second diffusion layers 19 and 21 are formed, and the first and second diffusion layers are formed at the time of thermal diffusion after ion implantation. There is no possibility that 19 and 21 will extend to the adjacent cells. Therefore, since it is not necessary to secure a long distance between adjacent cells, the memory cell size can be reduced.

It is desirable that the first and second diffusion layers 19 and 21 are formed apart from each other by a predetermined distance X. This is because if the first and second diffusion layers 19 and 21 are formed so as to be in contact with each other, a PN junction is formed in the contacted region, and a leak current is generated. For example, the distance X between the first and second diffusion layers 19 and 21 is determined by the gate electrode 17
Although it may be about the same as the width Y of the gate electrode 17, it is preferably about ½ of the width Y of the gate electrode 17 in consideration of reducing the occupied area of the memory cell region. Thus, the gate electrode 1
In order to make the interval X between the first and second diffusion layers 19 and 21 smaller than the width Y of 7, the heat treatment time is adjusted before forming the sidewall insulating film on the sidewall of the gate electrode 17. And the second diffusion layers 19 and 21 are formed, and then the gate electrode 1 is formed.
A side wall insulating film may be formed on the side wall of No. 7.

Although the second semiconductor layer 12 is a P-type layer in the first embodiment, it may be an N-type layer, and the impurity concentration of the second semiconductor layer 12 is set to the first diffusion layer 19. Alternatively, it may be set lower than the impurity concentration of the second diffusion layer 21.

[Second Embodiment] In the second embodiment, S
This is an example in which the potential of the gate electrode arranged on the OI substrate is made variable. In the second embodiment, only points different from the first embodiment will be described.

FIG. 8 is a circuit diagram of a magnetic memory device according to the second embodiment of the present invention. As shown in FIG. 8, the second embodiment differs from the first embodiment in that the potential of the gate electrode is variable. Specifically, when the second semiconductor layer 12 serving as the channel region is a P-type diffusion layer, a negative gate voltage is applied to the gate electrode 17. On the other hand, the second semiconductor layer 12 that becomes the channel region
Is a N-type diffusion layer, a positive gate voltage is applied to the gate electrode 17. The potential of the gate electrode 17 is made variable in this way for the following reason.

The diode structure according to the first embodiment is
It is a so-called gate control type diode 10,
The IV characteristic of the diode 10 depends on the gate voltage. This is due to the interface state existing under the gate electrode 17. Usually, a depletion layer is formed under the gate electrode 17 according to the voltage applied to the gate electrode 17. At this time, if an interface state exists in the depletion layer, this interface state becomes a coupling center and a reverse bias current is generated. It is generally known that the width of the depletion layer increases and the reverse bias current increases as the gate voltage increases positively.

Here, when the second semiconductor layer 12 serving as the channel region under the gate electrode 17 is a P-type diffusion layer as shown in FIG. 1 according to the first embodiment, the N ⁺ -type second layer is used. Of the P-type second semiconductor layer 12 and the diffusion layer 21 of P
N-junction becomes a problem. Therefore, in order to prevent the generation of the reverse bias current due to the interface state, the gate voltage may be set to a negative value. On the contrary, when the second semiconductor layer 12 serving as the channel region under the gate electrode 17 is the N-type diffusion layer, the gate voltage may be set to a positive value. As described above, in the second embodiment, the potential of the gate electrode 17 is variable in order to prevent the generation of the reverse bias current due to the interface state.

According to the second embodiment, the same effect as that of the first embodiment can be obtained.

Furthermore, by varying the gate voltage of the gate electrode 17 to a positive or negative value depending on the conductivity type of the second semiconductor layer 12 which becomes the channel region, generation of a reverse bias current due to the interface state is prevented. be able to.

[Third Embodiment] The third embodiment is an example of a structure in which an SOI substrate is used in the memory cell array region and a bulk substrate is used in the peripheral circuit region. In the third embodiment, only the points different from the first embodiment will be described.

9 and 10 are sectional views showing a magnetic memory device according to the third embodiment of the present invention. As shown in FIGS. 9 and 10, in the magnetic memory device according to the third embodiment, the SOI substrate 14 is not used for both the memory cell array region and the peripheral circuit region, but only the peripheral circuit region is the bulk substrate 51. It is a thing. Specifically, in the memory cell array region, the diode 10 is formed using the SOI substrate 14 as in the first embodiment. On the other hand, in the peripheral circuit area, the bulk substrate 51 is used.
A peripheral transistor 52 is formed on the top.

Here, in the structure of FIG. 9, a bulk substrate 51 is used.
Of the first semiconductor layer 11 on the SOI substrate 14.
It is almost the same height as the surface of. Therefore, a step is formed at the boundary between the memory cell array region and the peripheral circuit region, and the gate electrodes 17 and 53 in the memory cell array region and the peripheral circuit region are located at different heights.

In the structure of FIG. 10, the bulk substrate 51
Of the second semiconductor layer 12 on the SOI substrate 14.
It is almost the same height as the surface of. Therefore, there is no step at the boundary between the memory cell array region and the peripheral circuit region, and the gate electrodes 17 and 53 in the memory cell array region and the peripheral circuit region are located at the same height.

11A to 13C are sectional views showing the steps of manufacturing the magnetic memory device according to the third embodiment of the present invention. Here, SO is provided only in the memory cell array region.
Two methods of forming the I substrate will be described.

First, FIGS. 11 (a), 11 (b) and 11
The manufacturing process according to the first method will be described with reference to FIG. As shown in FIG. 11A, a silicon oxide film 2 serving as a mask layer is formed on, for example, a P-type silicon substrate 1 in the memory cell array region and the peripheral circuit region. Then, a photoresist 3 is formed on the silicon oxide film 2 and patterned so as to remain only in the memory cell array region. Next, as shown in FIG.
After the silicon oxide film 2 is selectively etched using the photoresist 3 as a mask, the photoresist 3 is removed. Then, for example, O ⁺ is ion-implanted only into the peripheral circuit region using the silicon oxide film 2 as a mask. Then, the silicon oxide film 2 is removed. Next, as shown in FIG. 11C, by performing annealing, the buried oxide film 13 is formed only in the memory cell array region, and the SOI substrate 1
4 is formed.

Next, FIGS. 12 (a), 12 (b) and 12
The manufacturing process according to the second method will be described with reference to FIG. As shown in FIG. 12A, the first and second semiconductor layers 11 and 12, and the first and second semiconductor layers 1
The SOI substrate 14 including the buried oxide film 13 formed between 1 and 12 is formed. Then, a photoresist 3 is formed on the second semiconductor layer 12 and patterned so as to remain only in the memory cell array region. Next, as shown in FIG. 12B, the second semiconductor layer 12 and the buried oxide film 13 in the peripheral circuit region are etched using the photoresist 3 as a mask. Next, FIG.
As shown in (c), the photoresist 3 is removed.
In this way, the SOI substrate 14 is left only in the memory cell array region.

After the step of FIG. 12C, the step between the memory cell array region and the peripheral circuit region may be eliminated by the following method. For example, as shown in FIG.
A silicon nitride film 4 is deposited on the entire surface of the memory cell array region and the peripheral circuit region. Then, using the lithography technique, only the silicon nitride film 4 in the peripheral circuit region is removed. Next, as shown in FIG. 13B, selective epitaxial growth (SEG) is performed.
The epitaxial growth layer 5 is formed in the peripheral circuit region by selectively growing Si on the surface exposed by h) up to about the surface of the second semiconductor layer 12. Next, FIG. 13 (c)
As shown in, the silicon nitride film 4 on the second semiconductor layer 12 is removed.

According to the third embodiment described above, not only the same effects as those of the first embodiment can be obtained, but also the following effects are obtained.

C formed on the SOI substrate 14 is generally used.
In the MOS circuit, since it is necessary to add a body contact to the transistor, there is a drawback in that the chip area becomes larger as the body contact is provided. On the other hand, in the third embodiment, the memory cell array region is SO
The I substrate 14 is used, but the peripheral circuit region is a bulk substrate 51.
To use. This eliminates the need to add a body contact to the peripheral transistor 52, so that the chip area can be reduced as compared with the case where the SOI substrate is used for both the memory cell array region and the peripheral circuit region.

The voltage of the gate electrode in the memory cell array region in the third embodiment may be variable as in the second embodiment. In this case, the same effects as those of the second and third embodiments can be obtained.

[Fourth Embodiment] In the first to third embodiments described above, writing is performed biaxially by the write word line and the bit line. On the other hand, in the fourth embodiment, writing is performed by one axis using only bit lines.

FIG. 14 is a plan view of a magnetic memory device according to the fourth embodiment of the present invention. FIG. 15 shows XV-XV of FIG.
FIG. 16 shows a cross-sectional view of the magnetic storage device along the line, and FIG.
4 is a sectional view of the magnetic memory device taken along line XVI-XVI in FIG.
FIG. 17 is a circuit diagram of the magnetic memory device according to the fourth embodiment of the present invention. Here, only the structure different from that of the first embodiment will be described.

As shown in FIGS. 14 to 17, the memory cell of the magnetic memory device according to the fourth embodiment has an MTJ element, write transistors Tr1 and Tr2, read transistor Tr3, and bit line BL1. , B
It is composed of L2 and BLC1.

Specifically, two transistors Tr, which are switching elements for writing, are formed on the SOI substrate 14.
1 and Tr2 are formed respectively.

The gate electrode of the transistor Tr1 functions as a read / write word line WL1. One diffusion layer of the transistor Tr1 is connected to the bit line connection wiring BLC1 via the metal wiring ML1 and the contact C1. The other diffusion layer of the transistor Tr1 is connected to the bit line BL1 via the metal wiring ML3, the contact C3, and the like.

The gate electrode of the transistor Tr2 functions as the write word line WWL1. Transistor Tr
One of the diffusion layers of No. 2 has a metal wiring ML2 and a contact C.
2 and the like, and is connected to the bit line connection wiring BLC1. The other diffusion layer of the transistor Tr2 has a metal wiring M
It is connected to the bit line BL2 via L5 and the contact C5.

The bit line connection wiring BLC1 has M
A TJ element is connected, and this MTJ element is connected to the ground (GN
D) line. Here, the MTJ element is a transistor Tr3 that is a switching element for reading.
May be connected.

Since the number of write wirings is one, the angle at which the extending direction of the bit line connection wiring BLC1 to be the write wiring and the magnetization direction of the MTJ element intersect is inclined from 90 degrees to some extent (for example, 45 degrees). , So that the magnetization can be easily reversed.

In such a uniaxial write magnetic memory device, data is written and read as follows.

First, when writing data to the MTJ element, the word line WL1 which is the gate electrode of the transistors Tr1 and Tr2 of the selected cell and the write word line WWL1 are turned on to write from the bit line BL1 to the bit line BL2 or vice versa. Apply current. The magnetic field generated by this write current changes the magnetization direction of the recording layer of the MTJ element. Here, the current direction may be selected according to the magnetization direction to be changed. At the time of writing, the transistor Tr3 connected to the common GND line is turned off to prevent the write current from flowing through the MTJ element.

On the other hand, when reading data from the MTJ element, the word line WL1 of the transistor Tr1 of the selected cell is turned on and all the write word lines WWL1, 2, ...
Turn off. Then, a read current is passed from the bit line BL1 to GND through the MTJ element, and the bit line BL1
Read the data with the sense amplifier connected to. When reading, the transistor Tr3 connected to the common GND line is turned on.

According to the fourth embodiment described above, not only the same effects as those of the first embodiment can be obtained, but also the following effects are obtained.

In the case of a structure in which writing is carried out on two axes by a write word line and a bit line, a plurality of bit lines and word lines are provided in a matrix form, and MTJ elements are arranged at each intersection of these bit lines and word lines. To be done. Then, at the time of writing, not only one MTJ element located at the intersection of the selected bit line and the selected word line but also the MTJ located below the selected bit line or above the selected word line. Writing is also performed on the element. That is, in the case of writing in two axes, there is a risk of erroneous writing in a half-selected cell.

On the other hand, in the fourth embodiment, the transistors Tr1 and Tr2 are arranged so that the current flows only between the bit lines BL1 and BL2 during writing.
Therefore, the write current does not flow to the cells other than the selected cell, and there is no cell in the half-selected state. Therefore, it is possible to prevent the disturb defect (data retention defect) from occurring in the semi-selected cell.

In addition, although the diodes are used as the switching elements in the first to third embodiments, it is possible to use transistors instead of the diodes. In the fourth embodiment, the transistor T
It is also possible to use diodes instead of r1, Tr2, Tr3.

In the first to fourth embodiments,
Although the MTJ element is used as the memory element, a GMR (Giant Magneto Resistive) element including two magnetic layers and a conductor layer sandwiched between these magnetic layers can be used instead of the MTJ element.

In addition, the present invention is not limited to the above-described embodiments, but can be variously modified at the stage of implementation without departing from the spirit of the invention. further,
The embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment,
When the problem described in the column of the problem to be solved by the invention can be solved and the effect described in the column of the effect of the invention can be obtained, a configuration in which this constituent element is deleted can be extracted as the invention.

[0089]

As described above, according to the present invention, it is possible to provide a magnetic memory device capable of suppressing variations in diode characteristics and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a magnetic memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a magnetic memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a TMR element having a single tunnel junction structure according to the first to third embodiments of the present invention.

FIG. 4 is a cross-sectional view showing a TMR element having a double tunnel junction structure according to the first to third embodiments of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the magnetic memory device according to the first embodiment of the invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the magnetic memory device according to the first embodiment of the invention, following FIG. 5;

FIG. 7 is a cross-sectional view showing the manufacturing process of the magnetic memory device according to the first embodiment of the present invention, following FIG. 6;

FIG. 8 is a circuit diagram showing a magnetic memory device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a magnetic memory device according to a third embodiment of the present invention.

FIG. 10 is a cross-sectional view showing another magnetic memory device according to the third embodiment of the invention.

FIG. 11 is a sectional view showing each manufacturing process of the magnetic memory device according to the third embodiment of the present invention by the first method.

FIG. 12 is a cross-sectional view showing each manufacturing process by the second method of the magnetic memory device according to the third embodiment of the present invention.

FIG. 13 is a cross-sectional view showing each manufacturing process of the magnetic memory device according to the third embodiment of the present invention following the second method, following FIG. 12;

FIG. 14 is a plan view showing a magnetic memory device according to a fourth embodiment of the present invention.

15 is a sectional view of the magnetic memory device taken along line XV-XV in FIG.

16 is a cross-sectional view of the magnetic memory device taken along line XVI-XVI of FIG.

FIG. 17 is a circuit diagram showing a magnetic memory device according to a fourth embodiment of the present invention.

FIG. 18 is a sectional view showing a TMR element according to a conventional technique.

FIG. 19 is a diagram showing TMR elements arranged in a matrix of a magnetic storage device according to a conventional technique.

FIG. 20 is a diagram showing an asteroid curve of a conventional magnetic memory device.

FIG. 21 is a diagram showing a TMR curve of a conventional magnetic memory device.

FIG. 22 is a cross-sectional view of a magnetic memory device including a transistor according to the related art.

FIG. 23 is a cross-sectional view of a magnetic storage device including a diode according to the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Photoresist, 4 ... Silicon nitride film, 5 ... Epitaxial growth layer, 10 ... Diode, 11 ... First semiconductor layer, 12 ... Second semiconductor layer, 13 ... Embedding Oxide film, 14 ... SOI substrate, 15 ... Element isolation region, 16 ... Gate insulating film, 17, 53 ... Gate electrode, 18, 20 ... Photoresist, 19 ... First diffusion layer, 21 ... Second diffusion layer, 22 ... Insulating film, 23a, 23b ... 1st contact, 24a, 24b ... 1st wiring, 25 ... 2nd contact, 26 ... 2nd wiring, 27 ... 3rd contact, 28a ... 3rd wiring , 28b ... Write word line (third wiring), 29 ... Fourth contact, 30 ... Lower electrode, 31 ... TMR element, 32 ... Bit line, 41, 41a, 41b ... Magnetization pinned layer, 42, 42a, 42b ... Tunnel junction layer, 43 ... Magnetic recording layer, 51 ... Bulk substrate, 52 ... Peripheral transistor, 101 ... Template layer, 102 ... Initial ferromagnetic layer, 103 ... Antiferromagnetic layer, 104, 104 ', Reference numeral 104 "... Reference ferromagnetic layer, 105, 105 ', 105" ... Free recording layer, 106 ... Contact layer, 107 ... Nonmagnetic layer, BL1, BL2 ... Bit line, BLC1, BLC2 ... Bit line connection wiring, C1, C2 , C3, C4, C5 ... Contact, ML1, ML2, ML3, ML4, ML5 ... Metal wiring, Tr1, Tr2, Tr4 ... Write transistor, Tr3 ... Read transistor, WL, WL1, WL2 ... Read and write word Lines, WWL1, WWL2 ... Write word lines.

Claims (48)

[Claims] 1. A semiconductor device comprising: a first semiconductor layer; a first insulating film formed on the first semiconductor layer; and a second semiconductor layer formed on the first insulating film. An SOI substrate, an element isolation insulating film that has a depth reaching the first insulating film from the surface of the second semiconductor layer, and is selectively formed in the second semiconductor layer; A switching element formed on the semiconductor layer, a magnetoresistive effect element connected to the switching element, a magnetoresistive effect element that is disposed below the magnetoresistive effect element and spaced apart from the magnetoresistive effect element, and extends in a first direction. A magnetic storage device comprising: an existing first wiring; and a second wiring formed on the magnetoresistive effect element and extending in a second direction different from the first direction. 2. The magnetic memory device according to claim 1, wherein the switching element is a diode. 3. The diode is formed in a gate electrode formed on the second semiconductor layer via a gate insulating film, and is formed in the second semiconductor layer at one end of the gate electrode, A first conductivity type first connected to the effect element
3. The magnetic memory according to claim 2, further comprising: a diffusion layer of 2 and a second diffusion layer of a second conductivity type formed in the second semiconductor layer at the other end of the gate electrode. apparatus. 4. The magnetic storage device according to claim 3, wherein the second diffusion layer is arranged apart from the first diffusion layer. 5. The distance between the first and second diffusion layers is
4. The magnetic memory device according to claim 3, wherein the width is substantially equal to the width of the gate electrode. 6. The distance between the first and second diffusion layers is
4. The magnetic memory device according to claim 3, wherein the width is 1/2 of the width of the gate electrode. 7. The second semiconductor layer between the first diffusion layer and the second diffusion layer is a third diffusion layer of the first conductivity type or the second conductivity type. The magnetic storage device according to claim 4, wherein: 8. The magnetic memory device according to claim 7, wherein the impurity concentration of the third diffusion layer is lower than the impurity concentration of the first diffusion layer or the second diffusion layer. 9. The magnetic memory device according to claim 3, wherein the potential of the gate electrode is fixed. 10. The magnetic memory device according to claim 3, wherein the potential of the gate electrode is fixed to the ground potential. 11. The magnetic memory device according to claim 3, wherein the potential of the gate electrode is variable. 12. A negative voltage is applied to the gate electrode when the third diffusion layer is P-type, and a positive voltage is applied to the gate electrode when the third diffusion layer is N-type. The magnetic storage device according to claim 7, wherein the magnetic field is applied. 13. A peripheral circuit, which is located around a memory cell array region including the magnetoresistive effect element and the switching element, and controls the switching element,
The magnetic memory device according to claim 1, further comprising a peripheral circuit region using a bulk substrate. 14. The magnetic memory device according to claim 13, wherein the height of the surface of the bulk substrate is substantially equal to the height of the surface of the first semiconductor layer. 15. An epitaxial growth layer formed on the bulk substrate and having a surface having a height substantially equal to the surface of the second semiconductor layer, and formed between the epitaxial growth layer and the second semiconductor layer. 14. The magnetic memory device according to claim 13, further comprising a second insulating film. 16. A semiconductor device comprising: a first semiconductor layer, a first insulating film formed on the first semiconductor layer, and a second semiconductor layer formed on the first insulating film. An SOI substrate, an element isolation insulating film having a depth reaching from the surface of the second semiconductor layer to the first insulating film, selectively formed in the second semiconductor layer, and the SOI substrate Formed on the first end and having one end and the other end
And a second switching element formed on the SOI substrate and having one end and the other end.
Switching element, a first wiring connected to the one end of the first switching element, a second wiring connected to the one end of the second switching element, and a first wiring of the first switching element A magnetic storage device comprising: a third wiring connected to the other end and the other end of the second switching element; and a magnetoresistive effect element connected to the third wiring. . 17. The magnetization direction of the magnetoresistive effect element is:
The magnetic storage device according to claim 16, wherein the magnetic wiring device is inclined by 45 degrees with respect to the extending direction of the third wiring. 18. The magnetic memory device according to claim 16, wherein the gate electrode of the first switching element is a word line for writing and reading. 19. The magnetic memory device according to claim 16, wherein the gate electrode of the second switching element is a write word line. 20. The magnetic memory device according to claim 16, further comprising a third switching element connected to the magnetoresistive effect element. 21. The magnetic memory device according to claim 20, wherein the gate electrode of the third switching element is a read word line. 22. The magnetic memory device according to claim 16, wherein the magnetoresistive effect element is connected to the ground. 23. The magnetic memory device according to claim 16, wherein the first and second switching elements are transistors or diodes. 24. The magnetic memory device according to claim 20, wherein the third switching element is a transistor or a diode. 25. The first and second switching elements are turned on, a current is passed between the first and second wirings,
The magnetic storage device according to claim 16, wherein data is written in the magnetoresistive effect element. 26. A third switching element connected to the magnetoresistive effect element, further comprising: a third switching element which is turned off when writing the data. The magnetic storage device described. 27. The first switching element is turned on, the second switching element is turned off, and the first switching element is turned on.
17. The magnetic memory device according to claim 16, wherein a current is caused to flow from the wiring to the magnetoresistive effect element to read data from the magnetoresistive effect element. 28. A third switching element further connected to the magnetoresistive effect element, wherein the third switching element is turned on when reading the data. The magnetic storage device described. 29. The MTJ element according to claim 1, wherein the magnetoresistive effect element is an MTJ element including at least three layers of a first magnetic layer, a second magnetic layer and a non-magnetic layer. Magnetic storage device. 30. The MTJ element according to claim 29, which has a single-junction structure having one non-magnetic layer or a double-junction structure having two non-magnetic layers. Magnetic storage device. 31. A first semiconductor layer, a first insulating film arranged on the first semiconductor layer, and a second semiconductor layer arranged on the first insulating film. A step of forming an SOI substrate, and a step of selectively forming an element isolation insulating film in the second semiconductor layer, the element isolation insulating film having a depth reaching the first insulating film from the surface of the second semiconductor layer. A step of forming a switching element in the second semiconductor layer, a step of forming a first wiring extending in a first direction, and a step of separating the first wiring from the first wiring above the first wiring. And forming a magnetoresistive effect element connected to the switching element, and forming a second wiring extending on the magnetoresistive effect element in a second direction different from the first direction. A method of manufacturing a magnetic storage device, comprising: 32. The method of manufacturing a magnetic memory device according to claim 31, wherein the switching element is a diode. 33. The diode is formed by forming a gate electrode on the second semiconductor layer via a gate insulating film, and by forming the magnetic layer in the second semiconductor layer at one end of the gate electrode. A step of forming a first diffusion layer of a first conductivity type connected to the resistance effect element; and a second diffusion layer in the second semiconductor layer at the other end of the gate electrode.
33. A method of manufacturing a magnetic memory device according to claim 32, further comprising the step of forming a conductive type second diffusion layer. 34. The method of manufacturing a magnetic memory device according to claim 33, wherein the second diffusion layer is formed separately from the first diffusion layer. 35. Impurity is injected into the second semiconductor layer between the first diffusion layer and the second diffusion layer to form a third conductive layer of the first conductivity type or the second conductivity type. 35. The method of manufacturing a magnetic memory device according to claim 34, wherein the diffusion layer is formed. 36. The third diffusion layer is formed such that the third diffusion layer has an impurity concentration lower than that of the first diffusion layer or the second diffusion layer. Item 35. A method of manufacturing a magnetic storage device according to Item 35. 37. The first and second diffusion layers are arranged such that a distance between the first and second diffusion layers is substantially equal to a width of the gate electrode.
And a second diffusion layer is formed.
4. The method for manufacturing the magnetic storage device according to item 3. 38. The first and second diffusion layers are formed such that a distance between the first and second diffusion layers is ½ of a width of the gate electrode. Item 33
A method of manufacturing a magnetic storage device according to item 1. 39. The method of manufacturing a magnetic memory device according to claim 31, wherein a memory cell array region using the SOI substrate and a peripheral circuit region using a bulk substrate are formed. 40. A step of forming a mask layer on a substrate in the memory cell array region, a step of implanting ions into the substrate in the peripheral circuit region using the mask layer as a mask, and the substrate in the memory cell array region. Forming the first insulating film therein to form the SOI substrate in the memory cell array region and the bulk substrate in the peripheral circuit region. A method of manufacturing a magnetic storage device according to claim 39. 41. A step of forming the SOI substrate in the memory cell array region and the peripheral circuit region, and removing the first insulating film and the second semiconductor layer in the peripheral circuit region, 40. The method of manufacturing a magnetic memory device according to claim 39, further comprising: forming the SOI substrate in the memory cell array region and forming the bulk substrate in the peripheral circuit region. 42. A step of forming a second insulating film on the SOI substrate and the bulk substrate; partly removing the second insulating film in the peripheral circuit region to expose a surface of the bulk substrate. A step of forming an epitaxial growth layer on the bulk substrate, removing the second insulating film on the second semiconductor layer, and removing the surface of the epitaxial growth layer and the surface of the second semiconductor layer. 42. The method of manufacturing a magnetic memory device according to claim 41, further comprising the step of equalizing. 43. A first semiconductor layer, a first insulating film arranged on the first semiconductor layer, and a second semiconductor layer arranged on the first insulating film. A step of forming an SOI substrate, and a step of selectively forming an element isolation insulating film having a depth reaching the first insulating film from the surface of the second semiconductor layer in the second semiconductor layer. A step of forming first and second switching elements having one end and the other end on the SOI substrate; a step of forming a magnetoresistive effect element above the SOI substrate; First connecting to the one end
Wiring, a second wiring connected to the one end of the second switching element, the other end of the first switching element, the other end of the second switching element, and the magnetoresistive effect element. And a step of forming a third wiring connected to the magnetic recording medium. 44. The magnetoresistive effect element and the third wiring are formed such that the magnetization direction of the magnetoresistive effect element is inclined 45 degrees with respect to the extending direction of the third wiring. The method of manufacturing a magnetic memory device according to claim 43. 45. The method of manufacturing a magnetic memory device according to claim 43, wherein the first and second switching elements are transistors or diodes. 46. A third connecting to the magnetoresistive effect element
44. The method of manufacturing a magnetic memory device according to claim 43, further comprising the step of forming the switching element of. 47. The method of manufacturing a magnetic memory device according to claim 46, wherein the third switching element is a transistor or a diode. 48. The MTJ element according to claim 43, wherein the magnetoresistive effect element is an MTJ element including at least three layers of a first magnetic layer, a second magnetic layer and a non-magnetic layer. Method of manufacturing magnetic storage device.