JP2003208200A - Received signal reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a received signal reproducing method for correctly reproducing compressed data transmitted by a variable bit rate even when reference frequencies are shifted between a transmission side and a receiving side. <P>SOLUTION: The compressed data transmitted in order are received by a receiver and accumulated in order in FIFO 1. A DSP (digital signal processor) decoder 4 properly reads the compressed data from the FIFO 1 to decode them. A reproducing time detector 2 detects a reproducible time by the compressed data accumulated in the FIFO 1, and a frequency ratio detector 6 detects the ratio of a sampling frequency on the transmission side and that to be outputted actually based on the variation of the reproducible time. On the basis of this ratio, a clock generator 3 generates a reference signal equivalent to the sampling frequency on the transmission side, and an Fs converter 5 converts the sampling frequency of the output of the DSP decoder 4. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received signal reproducing method for receiving compressed data transmitted while sequentially compressing information of an audio signal or the like, and reproducing while sequentially decoding the received signal.

[0002]

2. Description of the Related Art Recently, audio signals have been wirelessly transmitted. However, in order to save the transmission band, as shown in FIG. 4, a digital signal processing device (hereinafter referred to as DSP) 100 is used for input. The audio signal sequence having the sampling frequency fs is compressed for each specific number and encoded into a data sequence in a unit of one frame as shown in FIG. Although each frame has a different frame length, each frame has the same amount of data when decoded. Each frame has a header (denoted as "H" in the figure), and synchronization information, information necessary for decoding such as frame length and sampling frequency is written in the header. As such a compression method, one of the audio compression methods of the international standard MPEG-2 is AAC (Advanced Audio C).
oding) is known. The encoded data string is transmitted using the transmitter 101, received by the receiver 102, and the decoder DSP 103 reads necessary information such as the sampling frequency and the frame length from the header of the frame to obtain the original audio signal. It is designed to demodulate.

[0003]

However, in the above method, when the data encoded by the DSP 100 has a variable bit rate as shown in FIG. 5, the transfer rate of the data transferred by the transmitter 101 is It is not known on the receiving side, and when reproduced at the sampling frequency specified by the header, there is a problem that the transmission data becomes excessive or insufficient due to a slight deviation in the reference frequency for each. was there.

The present invention solves the above problems by correctly outputting an audio signal even when the transfer rate is unknown or when the reference frequency on both the transmitting side and the receiving side is deviated. A method of reproducing a received signal that can be reproduced is provided.

[0005]

In order to solve this problem, the present invention provides a means for receiving transmitted compressed data having a first sampling frequency and storing it in a FIFO, and reading and decoding the compressed data from the FIFO. Means, a means for detecting the reproducible time by the compressed data stored in the FIFO, and a frequency ratio between the first sampling frequency and the actually output second sampling frequency based on the change in the reproducible time. Means, a clock generation means for generating a reference signal corresponding to the first sampling frequency based on the frequency ratio, and a sampling rate conversion means for converting the output of the decoding means based on the frequency ratio into the second sampling frequency. I had it.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention comprises means for receiving compressed data having a first sampling frequency to be transmitted and storing the compressed data in a FIFO, and the FI.
Means for reading and decoding the compressed data from the FO, means for detecting the reproducible time by the compressed data stored in the FIFO, and actually outputting the first sampling frequency based on the change in the reproducible time. Means for detecting a frequency ratio of the second sampling frequency;
Clock generation means for generating a reference signal corresponding to the first sampling frequency based on the frequency ratio; sampling rate conversion means for converting the output of the decoding means into a second sampling frequency based on the frequency ratio; Therefore, regardless of the amount of data actually transmitted, the actual value of the sampling frequency fs on the transmission side and the sampling on the reception side from the reproducible time of the data stored in the FIFO The ratio of the frequencies can be estimated, and regardless of the sampling frequency of the transmission data, the sampling frequency on the receiving side enables reproduction.

The invention described in claim 2 is the same as claim 1
In the invention according to claim 1, the compressed data is data in a unit of one frame delimited by a header, and the means for detecting the reproducible time measures the number of frames of the compressed data accumulated in the FIFO. Is to detect the reproducible time by
Since the number of samples when one frame is decoded is constant, this has the effect that the reproducible time can be easily detected by the decoding means without actually decoding.

The invention described in claim 3 is the same as claim 1
In the invention according to, the clock generating means is means for dividing the master clock to obtain the first sampling frequency, and the frequency ratio is M1: M2,
Assuming that the frequency division ratio of the first sampling frequency to the master clock is R1 and the frequency division ratio of the second sampling frequency to the master clock is R2, M1 · R
The frequency division ratio R1 is determined by an algorithm based on the magnitude relationship between 2 and M2 · R1. With this, the sampling frequency of the frequency division ratio R1 and the frequency division ratio R2 The sampling ratios of the two are macroscopically identical to each other, and in the state of being synchronized with the sampling frequency of the transmitting side, the sampling frequency is converted into a desired sampling frequency on the receiving side.

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram showing a configuration example for realizing a received signal reproducing method according to an embodiment of the present invention. To explain this figure, the receiver 7 receives the transmitted compressed data, and receives the FIFO (Fast I
n Fast Out Memory) 1 input. The signal transmitted to the receiver 7 is the encoder on the transmission side (DS shown in FIG. 4).
(Corresponding to P100), the signal having the sampling frequency fs1 is encoded. The FIFO 1 is input with data in which 1024 sample data is compressed to form one frame. When four frames of data are stored in the FIFO1, the FIFO1 starts outputting data in the order of input. After the output is started, the data is released according to the request signal rq generated by the decoding DSP 4 and the data supplied to the input is sequentially accumulated.

Based on the clock signal CK1 generated by the clock generator 3, the DSP 4 sequentially reads the accumulated data from the FIFO 1 and performs a predetermined decoding process to perform F
Output to the s converter 5. Here, the clock signal CK1 generated by the clock generator 3 is a signal corresponding to the sampling frequency fs1, and the DSP 4 starts the decoding operation when 4 frames of data are stored in the FIFO 1, and the frame is transmitted from the FIFO 1 by the request signal rq. Data is requested in units, and a signal decoded at the sampling frequency fs1 rate is sent to the Fs converter 5.

The Fs converter 5 converts the sampling frequency fs1 of the DSP4 output to fs2 based on the clock signal CK2 having the frequency ratio M1 and the sampling frequency fs2 provided from the frequency ratio detector 6, and outputs the fs2. As will be described later, the frequency of the clock signal CK1 varies finely, that is, a signal having a lot of jitter, and the DSP4 output operating based on the signal also has a jitter. The Fs converter 5 absorbs the jitter and extracts a signal synchronized with the master clock. It is assumed that all blocks are operating based on the given master clock. An Fs converter that operates in this manner is, for example, 1 in the December 1993 issue of Radio Technical Magazine published by AIA Publishing Co., Ltd.
It is described on pages 73-180.

The reproduction time detector 2 manages the amount of data input to the FIFO 1 by the reproduction possible time.
Here, when one frame of data is newly input to the FIFO 1, the frame pulse information is output to the frequency ratio detector 6. The frequency ratio detector 6 detects the frequency ratio M1 based on the frame pulse and the clock signal CK1 which is a reference signal generated by the clock generator 3. This value is the sampling frequency fs2 at the output of Fs converter 5.
And the actual sampling frequency of the transmitter encoder.

The frequency ratio detecting method will be described with reference to FIG.
The counter 20 counts the number of frame pulses given by the reproduction time detector 2. The clock signal CK1 generated by the clock generator 3 is 1024 for one frame here.
1 is converted by the converter 29 as it is decoded into samples.
One pulse is output every 024 clocks. The counter 21 measures the output of the converter 29, and the subtracter 22 is used to detect the difference D between the output of the counter 20 and the output of the counter 21. The difference D is determined by the determiners 23 to 26.
Is greater than 6, the determiner 23 outputs a pulse of "1", and when the difference D is greater than 5 and is 6 or less, the determiner 24 outputs a pulse of "1", and the difference D is 2 or more and less than 3 When the difference D is smaller than 2, the determiner 25 outputs a pulse of "1" when the difference is smaller than 2.

In the register 27, a frequency ratio M1 which is assumed in advance at the start of the operation is set. Here, 262144 (2 ¹⁸ ) is used as the reference with 19-bit data. If the sampling frequency fs2 after the sampling frequency conversion by the Fs converter 5 is 44.1 kHz and the signal to be input has a sampling frequency of 48 kHz in its header, the value of the register 27 is set to 285327. The outputs of the determiners 23 to 26 are checked at regular time intervals, and if a pulse is output, the value of +2 to -2 is added to the value stored accordingly.

If the actual sampling frequency of the transmitter encoder is exactly 48 kHz, the actual F
The number of frames written in IFO 1
The number of frames read from O1 becomes equal, and when the receiver 7 receives the data of four frames, the DSP 4 starts a data request, so the difference D between the values of the counters 20 and 21 for measuring the number of frames is always 4 Within the range of ~ 3.

However, if the actual sampling frequency of the transmitter encoder is slightly higher than 48 kHz,
The number of frames actually written in FIFO1 is DSP4
Is greater than the number of frames read from the FIFO 1, the difference D between the values of the counters 20 and 21 that measure the number of frames is gradually increased, and when it exceeds 5, the value of the frequency ratio M1 is incremented by one. After a lapse of a fixed time, the changes in the output of the subtractor 22 are checked by the determiners 23 to 26, and if the difference D increases and exceeds 6, the value of the frequency ratio M1 is further increased by +.
Add 2. This operation is repeated until the difference D becomes 5 or less.

On the contrary, if the actual sampling frequency of the transmitter encoder is slightly lower than 48 kHz, the FIFO
Since the number of frames written in 1 is smaller than the number of frames read by the DSP 4 from the FIFO 1, the difference D between the values of the counters 20 and 21 measuring the number of frames is gradually reduced, and when it is less than 3, the value of the frequency ratio M1 is reduced. Is reduced by 1. After a certain period of time, the change of the output of the subtractor 22 is judged by the judging device
Check with 3 to 26, the difference D becomes smaller,
If it is less than 2, the value of the frequency ratio M1 is further reduced to −
2. This operation is repeated until the difference D becomes 3 or more.

By operating as described above, even if the actual sampling frequency of the transmitter encoder is unknown,
Further, even if the sampling frequencies on the transmitting side and the receiving side fluctuate due to temperature drift or the like, for example, the correct frequency ratio M1 that always follows these changes can be obtained.

The clock generator 3 generates a clock signal CK1 to be sent to the DSP 4 based on the frequency ratio M1. The clock signal CK1 is a signal generated macroscopically so as to have a frequency equal to fs1, and here, a signal obtained by dividing the master clock is used. Now, the ratio of the sampling frequency fs1 on the transmission side to the sampling frequency fs2 of the output of the Fs converter 5 is the frequency ratio M1.
Therefore, if the frequency division ratio of the sampling frequency fs2 to the master clock is R2 and the frequency division ratio of the clock signal CK1 is R1, the desired frequency division ratio R1 is R1 =
It becomes R2 × 262144 / M1 (hereinafter, referred to as Expression 1). However, since the division ratio R1 can take only an integer value,
Here, the frequency division ratio R1 is changed, and macroscopically {R2 ×
262144 / M1}.

This method will be described with reference to FIG. Since the sampling frequency of the transmission side encoder is assumed to be 48 kHz here, the frequency ratio M1: M2 is 28532.
7: 262144. Also, the sampling frequency fs
2 is obtained by dividing the master clock by 256. That is, the frequency division ratio R2 is 256.

From the above equation 1, the frequency division ratio R1 = 235.2
However, since the division ratio R1 can take only an integer value, when the sampling frequency fs1 on the transmission side is estimated to be 48 kHz, R1 = 235, R2 = 256, M2 = 26214.
4 is set in step 31. The value obtained by the frequency ratio detector 6 is set in M1. Usually, the value is around 285327. Further, the value of the phase difference S is cleared.

In step 32, {(M1.R2-
M2 · R1) + S} is calculated, and the phase difference S is updated.
The value of {(M1 · R2−M2 · R1) + S} indicates how much the phase of the sampling frequency fs1 should deviate due to the provisionally determined value of the frequency division ratio R1. Depending on the polarity of the phase difference S, that is, whether it leads or lags the originally intended phase, and the magnitude of the value in (), four types of processing are performed in steps 33 to 35.

When the value in () is positive and the phase difference S is also positive, the frequency is higher than the original value and the phase is ahead of the original value. Add 1 to lower the frequency (step 3)
6).

When the value in () is positive and the phase difference S is negative, the frequency is higher than the original value, but the phase lags behind the original value. The ratio R1 is left unchanged (No in step 34).

When the value in () is negative and the phase difference S is also negative, the frequency is lower than the original value, and the phase is behind the original phase. Decrease by 1 to increase the frequency (step 37).

When the value in () is negative and the phase difference S is positive, the frequency is lower than the original value, but since the phase is ahead of the original value, it is necessary to restore the original value. The ratio R1 remains unchanged (No in step 35).

Even if the frequency ratio M1 given by the frequency ratio detector 6 fluctuates by performing such processing, the frequency division ratio R1 is set appropriately in accordance with this fluctuation.

Here, considering the clock signal CK1 generated by the clock generator 3, since this signal is obtained by dividing the master clock with a dividing ratio that finely changes, its frequency is microscopically determined. It has fine fluctuations, that is, jitter. However, since it does not largely deviate from the phase determined by the frequency ratio M1, the frequency is accurately determined by the frequency ratio M1 from a macroscopic viewpoint. DS based on this clock signal CK1
The signal output from P4 is converted to a desired sampling frequency fs2 by the Fs converter 5, but since the clock signal CK2 that is the reference of fs conversion is the master clock divided by a fixed value, there is no jitter. You can get a signal.

As described above, the margin in the FIFO 1 is managed not by the data amount but by the reproducible time, and the frequency ratio is set so that the value becomes almost constant, whereby the transfer rate is variable. Even if there is, the decoding process can be performed in synchronization with the sampling frequency of the encoder on the transmitting side, and since the frequency ratio can be directly calculated, it is also possible to freely set the sampling frequency for reproduction on the receiving side. Become.

In the above description, the frequency ratio is 262.
Although 144 is used as a reference and the frequency division ratio of the sampling frequency fs2 to the master clock is 256, 1024 samples per frame, of course, it is not limited to this value. Further, when the data of four frames is accumulated in the FIFO1, the FIFO1 starts outputting the data in the input order, but if the capacity of the FIFO1 is large, more data may be accumulated. The point is that it should be satisfied to the extent that underflow does not occur due to fluctuations in the amount of input data.

In the above embodiment, the configuration of the received signal reproducing apparatus is shown as an example of realizing the received signal reproducing method, but it goes without saying that the method according to the present invention can be implemented by software. .

[0033]

As described above, according to the present invention, means for receiving the compressed data having the first sampling frequency to be transmitted and storing it in the FIFO, and means for reading and decoding the compressed data from the FIFO, A means for detecting a reproducible time by the compressed data stored in the FIFO, and a means for detecting a frequency ratio between the first sampling frequency and the second sampling frequency to be actually output based on the change in the reproducible time. , The first based on the frequency ratio
By providing a clock generating means for generating a reference signal corresponding to the sampling frequency of S1 and a sampling rate converting means for converting the output of the means for decoding based on the frequency ratio into the second sampling frequency. The sampling frequency at is unknown,
Moreover, even if the amount of data transmitted is not constant, the sampling frequency on the transmission side can be accurately estimated and the reproduction can be performed correctly.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a received signal reproducing method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a frequency ratio detector according to the same embodiment.

FIG. 3 is a flowchart showing the operation of the clock generator in the same embodiment.

FIG. 4 is a block diagram for explaining a conventional received signal reproducing method.

FIG. 5 is an explanatory diagram showing a data stream.

[Explanation of symbols]

1 FIFO 2 Playback time detector 3 clock generator 4 DSP 5 Fs converter 6 Frequency ratio detector 7 receiver

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5D045 DA20                 5K047 AA05 LL01 MM02 MM11 MM26                       MM27 MM38 MM49 MM56 MM62

Claims (3)

[Claims] 1. A method for receiving compressed data having a first sampling frequency to be transmitted, storing the compressed data in a FIFO, reading the compressed data from the FIFO and decoding the compressed data, and compressing the compressed data stored in the FIFO. A means for detecting a reproducible time, a means for detecting a frequency ratio between the first sampling frequency and a second sampling frequency to be actually output based on a change in the reproducible time, and a means for detecting the frequency ratio based on the frequency ratio. Clock generating means for generating a reference signal corresponding to a sampling frequency of 1; and sampling rate converting means for converting an output of the decoding means into a second sampling frequency based on the frequency ratio. Receiving signal reproduction method. 2. The compressed data is data in units of one frame delimited by a header, and the means for detecting the reproducible time measures the number of frames of the compressed data stored in the FIFO. 2. The received signal reproducing method according to claim 1, which is means for detecting a reproducible time. 3. The clock generating means is a means for dividing the master clock to obtain the first sampling frequency, and the frequency ratio is M1: M2, and the master clock having the first sampling frequency. Is R1 and the frequency division ratio of the second sampling frequency to the master clock is R2, M1.R2 and M1
The frequency division ratio R1 is determined by an algorithm based on the magnitude relationship of 2 · R1.
The received signal reproduction method described.