JP2003204529A - Signal converter and video display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal converter and a video display device capable of capturing correct data even when an input timing of a received digital video signal is changed. <P>SOLUTION: The signal converter is characterized by comprising, a first delay adjustment means 25 for delaying at least one of a digital input video signal, a synchronizing signal synchronously with the digital input video signal, a display period signal and a dot clock, a data capturing means 24 for capturing the digital input video signal, the synchronizing signal and the display period signal on the basis of the dot clock from the first delay adjustment means to latch the data, a control means 9 for adjusting the delay of the first delay adjustment means depending on a value of the data latched by the data capturing means, and a conversion means 10 for converting the data from the data capturing means into a video signal with a prescribed frequency and a prescribed number of pixels. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device and a video display device for converting the frequency and the number of pixels of a video signal and displaying the same, and more particularly to a sampling clock frequency of a video signal having a different frequency and a different number of display pixels. The present invention relates to a signal conversion device and a video display device for automatically adjusting a phase timing and a display position and converting the video signal into a video signal having a predetermined frequency and a predetermined number of pixels for display.

[0002]

2. Description of the Related Art Recently, personal computers (hereinafter referred to as PCs)
As a video display device (hereinafter abbreviated), the demand for a digital video display device represented by a liquid crystal display or the like is increasing from the viewpoint of space saving and power saving. Conventionally, since an analog video display device using a cathode ray tube (CRT) has been widely used as a video display device, the video output from the PC is almost always an analog video signal. Therefore, when a digital video display device that originally displays a video by inputting a digital video signal is used for a PC, an A / D conversion function for converting an analog video signal into a digital video signal is required.

In such a digital image display device, the number of display pixels of the input analog video signal and the frequency of the synchronizing signal are discriminated using the horizontal synchronizing signal and the vertical synchronizing signal as keys, and are stored in advance in a storage device. Based on the standard display parameters (preset data), the video signal is A / D converted to generate a digital video signal. The digital image display device displays a video image based on the digital image signal thus generated.

However, the standard of the analog video signal output from the PC is not observed. Therefore, PC
Of course, the output timing of the analog video signal is deviated from the standard timing even in each PC, not to mention the models. for that reason,
A conventional digital image display device that performs A / D conversion based on standard display parameters has a screen width error,
Problems such as screen flicker, deterioration of display quality such as jitter, and display position shift are inevitable. Therefore, in order to obtain good display quality, it is essential to correct variations in the sampling interval (clock) from the standard value during A / D conversion, adjust sampling timing (phase), and adjust display position. .

In order to solve this, Japanese Patent Laid-Open No. 10-632
As disclosed in Japanese Patent Laid-Open No. 34-34, Japanese Patent Laid-Open No. 2000-47649, etc., a method of incorporating an automatic adjustment function into a digital image display device is used.

On the other hand, since digital image display devices such as liquid crystal display devices and plasma displays are being widely used, it is possible to use P as a monitor for various computers.
C and workstations (hosts) are often connected to video boards of information processing apparatuses by digital interfaces. Accordingly, the digital video signal can be directly input to the digital video display device without being converted into the analog video signal. In order to deal with this, Japanese Patent Laid-Open Nos. 11-282443 and 2001-1667
An image display device as described in Japanese Patent No. 32 is also considered.

FIG. 5 is a block diagram showing a signal conversion device used in a conventional image display device. FIG. 5 shows a block configuration in which an analog format video signal A or a digital format video signal D is selected, signal processed, and then output to the output terminals 11 and 12. In the figure, 1 is an input terminal for a digital video signal D, and 2 is a horizontal synchronizing signal H for the video signal D.
D, vertical synchronizing signal VD, input terminal of display period signal DED, 3 is input terminal of dot clock CKD of video signal D, 4 is input terminal of analog video signal A, 5 is horizontal sync signal HA of video signal A , An input terminal for the vertical synchronizing signal VA, 6 a PLL for generating a sampling clock CKA of the video signal A, 7 a delay adjustment circuit, 8 an A / D converter, 90 a control circuit, 10 a signal conversion circuit, 11 Video signal B output terminal, 12 is horizontal sync signal H of video signal B
B is an output terminal for the vertical synchronizing signal VB, 15 is a video detection circuit, 21, 22, 23 are switches, 24 is a flip-flop circuit, and 30 is a delay circuit.

First, the case where the analog video signal A is selected will be described with reference to FIG. An analog video signal A is supplied from an input terminal 4 to an 8-bit A / D converter 8. On the other hand, the horizontal synchronizing signal HA and the vertical synchronizing signal VA of the video signal A are supplied from the input terminal 5 to the PLL 6, the delay adjusting circuit 7, and the control circuit 90. The PLL 6 sets a multiplication number N according to a control signal from a control circuit 90 described later, generates a sampling clock CKA having a frequency N times that of the horizontal synchronizing signal HA, and supplies the sampling clock CKA to the delay adjusting circuit 7. In the delay adjustment circuit 7, the sampling clock CKA is delayed by a delay amount Ps corresponding to a control signal from the control circuit 90 described later, and is supplied to the A / D converter 8 and the terminal a of the switch 21. The vertical synchronizing signal VA is supplied to the terminal a of the switch 23 in synchronization with the delayed sampling clock CKa.

The 8-bit A / D converter 8 converts the analog video signal A into a digital video signal having a level value between level 0 and level 255 by the sampling clock CKa from the delay adjustment circuit 7. And supplies it to the terminal a of the switch 22. The switches 22 and 23 select the terminal a respectively, and the digital format video signal from the A / D converter 8, the horizontal synchronizing signal and the vertical synchronizing signal from the delay adjusting circuit 7 are converted into the signal converting circuit 10 and the video detecting circuit 15, respectively. Supply to. On the other hand, the switch 21 selects the terminal a, and the sampling clock CKa from the delay adjustment circuit 7 is selected.
Is supplied to the signal conversion circuit 10, the video detection circuit 15, and the flip-flop circuit 24.

In the video detection circuit 15, the switches 21, 2
Video signals in digital format from 2, 23, horizontal sync signal, vertical sync signal, detection of video range from sampling clock, detection of video level at predetermined video position,
The result is supplied to the control circuit 90. Here, the detection of the video range by the video detection circuit 15 is, for example, Japanese Patent Laid-Open No. 10-
As disclosed in the flow charts of FIGS. 6 and 7 of Japanese Patent No. 63234, the start pixel and the end pixel of the horizontal line are detected by the level detector incorporated in the video detection circuit 15 in synchronization with the sampling clock CKa. The process of obtaining the difference between the count values of the sampling clock CKa corresponding to the start pixel and the end pixel, that is, the number of pixels. Also, the number of pixels in the vertical direction is detected.

The control circuit 90 makes a signal discrimination from the horizontal synchronizing signal HA and the vertical synchronizing signal VA, and detects the result and the image range from the image detecting circuit 15 (that is, the calculation of the number of pixels).
The multiplication number N is determined based on the result. For example, if it is determined from the horizontal synchronizing signal HA and the vertical synchronizing signal that it is a VGA signal (horizontal pixel number 640 × vertical pixel number 480), the horizontal pixel number detected by the video detection circuit 15 is 64.
The multiplication number N is determined so that it becomes zero. A control signal designating the multiplication number N is output to the PLL 6, and a control signal designating the video range is output to the signal conversion circuit 10 from the result of the video range detection (that is, calculation of the number of pixels) from the video detection circuit 15. Further, the delay amount Ps is determined from the detection result of the video level at the predetermined video position, and the control signal designating this delay amount is supplied to the delay adjustment circuit 7.

In the signal conversion circuit 10, a video signal B is created by performing pixel conversion of a predetermined frequency and a predetermined number of pixels in the video range according to the control signal designating the video range from the control circuit 90, and further the frequency is generated. A horizontal synchronizing signal HB and a vertical synchronizing signal VB which are synchronized with the video signal B are created and supplied to the output terminals 11 and 12, respectively.

Here, a method of setting the delay amount Ps of the delay adjusting circuit 7 will be described with reference to FIG. FIG. 3 is a diagram for explaining a method of setting the optimum delay amount of the sampling clock CKA of the analog video signal A.

In FIG. 3, a predetermined image position is set n clocks after the fall (or rise) of the horizontal synchronizing signal HA of the image signal A, and the A / D converter 8 of this pixel is A / D-converted. A video signal A having a video level of 255 and the video levels of pixels before and after the video level of 0 is input from the input terminal 4. Sampling clock CK generated by PLL6
In the delay adjusting circuit 7, the delay adjusting circuit 7 changes the delay amount Ps at several points within the variable range of 1 clock (eight stages of 1/8 clock in each of 0 to 7) and outputs the delayed sampling clock to the A / D converter 8. Supply CKa. The A / D converter 8 performs A / D conversion by the sampling clock CKa and supplies an 8-bit digital format video signal to the video detection circuit 15. In the video detection circuit 15, a predetermined video position (pixel after n clocks from the fall of HA) is set in advance, and the video level of the pixel at this video position is set to the delay amount Ps.
Every time it is changed, and the result is supplied to the control circuit 90.

The control circuit 90 determines whether or not the detection result from the video detection circuit 15 is equal to or higher than a preset detection level which is slightly smaller than the preset level 255 as shown in FIG. The amount of delay when the detection level is exceeded is stored in a storage unit (not shown)
When the above detection operation is completed (in FIG. 3, when eight stages of 0 to 7 for each 1/8 clock is completed), the delay adjustment circuit 7 is provided with an optimum delay amount when the predetermined detection level or more is reached. Set. In the case of FIG. 3, when it becomes equal to or higher than a predetermined detection level, it corresponds to within the optimum range (delay amount 3 to 5), and the optimum delay amount at this time is the average value of the delay amounts 3, 4 and 5 4 And the delay amount 4 is set in the delay adjustment circuit 7.

Next, returning to FIG. 5, the case where the digital video signal D is selected will be described. Usually, for transmitting a digital format video signal, for example, the above-mentioned JP 2001-166A is used.
TMDS (Tra as disclosed in Japanese Patent No. 732
transition Minimized Differen
Tial Signaling) and LVDS (LowV)
oltage Differential Signal
It is common to use a digital interface such as ing), and therefore a video signal of the digital format is converted by a transmitter (not shown) into a signal format suitable for the digital interface, and then the digital interface is used. It is common to transmit. Therefore, a receiver (not shown) for a digital interface is connected to the input terminals 1, 2, and 3 in order to restore the transmitted digital format video signal to the original digital format video signal before conversion. Often.

A video signal D in digital form from the input terminal 1, a horizontal synchronizing signal HD of the video signal D from the input terminal 2, a vertical synchronizing signal VD, a display period signal DED, and a dot clock CKD of the video signal D from the input terminal 3 are respectively provided. It is supplied to the delay circuit 30. The delay circuit 30 delays the input digital video signal D, horizontal synchronizing signal HD, vertical synchronizing signal VD, and display period signal DED with respect to the dot clock CKD, or conversely, the dot clock CKD.
Delay. Here, the dot clock CKD is subjected to a predetermined delay so as not to race, the delayed dot clock CKd is supplied to the terminal b of the switch 21, and the other parts are supplied to the flip-flop circuit 24. The switch 21 selects the terminal b and supplies the dot clock CKd to the flip-flop 24, the signal conversion circuit 10, and the video detection circuit 15.

In the flip-flop circuit 24, the video signal D in digital form, the horizontal synchronizing signal HD, and the vertical synchronizing signal V are generated at the rise of the dot clock CKd from the switch 21.
D and the display period signal DED are fetched and supplied to the terminals b of the switches 22 and 23, respectively. The switches 22 and 23 select the terminal b and supply it to the signal conversion circuit 10 and the video detection circuit 15, respectively. The signal conversion circuit 10 and the video detection circuit 15 perform the same processing as when the analog video signal A is selected. The control circuit 90 uses the video detection circuit 15
A control signal for designating the image range is output to the signal conversion circuit 10 from the result of the image range detection (that is, calculation of the number of pixels). In this case, the control circuit 90 does not control the PLL 6 and the delay control circuit 7.

Here, the delay amount of the delay circuit 30 will be described with reference to FIG. FIG. 4 shows a digital format video signal D.
FIG. 6 is a diagram illustrating a method of setting an optimum delay amount of the dot clock CKD.

In FIG. 4, the digital video signal D shows the level of a pixel at a predetermined video position n dot clocks after the fall of the horizontal synchronizing signal HD. The level of this pixel is 255, and the levels of the pixels before and after it are 0. In the same figure, the dark area shows the lacing range (data
However, the racing will be described below.

Racing is a flip-flop circuit 2
4, video signal D, horizontal sync signal HD, vertical sync signal V
D, the minimum setup time or the minimum hold time of the flip-flop circuit 24 is insufficient when the display period signal DED is taken in at the rising edge of the dot clock CKd. The setup time is the time during which the input data must be fixed before the significant edge (rising in the case of FIG. 4) of the clock supplied to the flip-flop, and the hold time is the flip-flop. This is the time during which the input data must be held behind the significant edge (the rising edge in the case of FIG. 4) of the clock supplied to. The setup time and hold time are defined by the circuit specifications of the flip-flop in the design using the flip-flop. When this racing occurs, the data at that location cannot be captured reliably, resulting in a malfunction such that the original data differs from the original data or the original data timing deviates by one clock.

As mentioned above, the input terminals 1, 2,
Since a receiver for digital interface is often connected to the stage before 3, the input timing of the input terminals 1, 2, 3 is often determined by the output timing of this receiver. In this case, normally, the polarity of the dot clock CKD can be switched, but the delay amount is fixed.

Therefore, when the timing of the input terminals 1, 2, 3 is as shown in FIG. 4 (CKD and D, HD),
From the falling edge of the horizontal sync signal HD to the dot clock CK
At the rising edge of D after n clocks, the data is in the lasing range and cannot be read correctly. Therefore, by inverting the polarity of the dot clock CKD of the receiver or delaying the dot clock CKD by the delay circuit 30 by any one of the delay amounts 2 to 6 within the optimum range, the racing range can be avoided and the optimum timing can be obtained. Become. Usually, the polarity of the dot clock CKD of the above receiver is reversed,
The delay amount 4 is set farthest from the racing range (with a margin). Since the vertical synchronizing signal VD and the display period signal DED (not shown) have the same timing as the video signal D and the horizontal synchronizing signal HD, racing can be avoided and the timing becomes optimum.

Therefore, as shown in FIG. 4, the dot clock CK
When the rising edge of D is in the racing range, it is necessary to avoid the racing like the dot clock CKd, and the delay circuit 30 is provided.

[0025]

However, the digital video signal input to the digital input terminal may differ depending on the type of the receiver for the digital interface connected to the digital input terminal and the frequency of the dot clock.
Input timing of digital input terminal (CKD and D, HD
The phase) is likely to change. In this case, it is necessary to consider racing by changing the delay amount of the delay circuit. However, in the above-described conventional technique described in FIG. 5, when the delay circuit 30 cannot change the delay amount because it is a fixed delay and the input timing of the input terminals 1, 2, 3 changes, racing occurs. There is.

In order to avoid the racing, the delay amount of the delay circuit 30 is fixed. Therefore, the delay circuit 30 is replaced with a delay circuit having an optimum delay amount each time according to the change in the input timing. The trouble of dealing with it occurs.

Further, due to the above-mentioned timing change, if the margin is small even if the racing does not occur in the normal use state, the margin is further reduced due to the influence of the temperature change, the jitter, etc., and the racing is performed. In some cases, racing may occur due to variations in the delay amount of the components themselves.

An object of the present invention is to provide a signal conversion device and a video display device capable of taking in correct data even if the input timing of an input digital video signal changes.

[0029]

According to the present invention, there is provided first delay adjusting means for delaying at least one of a digital input video signal, a synchronizing signal synchronized with the digital input video signal, a display period signal and a dot clock. Data input means for storing the digital input video signal, the synchronizing signal, and the display period signal by the dot clock from the first delay adjusting means and holding the data, and a data value of the data held by the data capturing means. Control means for adjusting the delay amount of the first delay adjusting means according to
A signal conversion device, comprising: a conversion unit that converts data from the data acquisition unit into a video signal having a predetermined frequency and a number of pixels.

According to the present invention, first delay adjusting means for delaying at least one of a digital input video signal, a synchronizing signal synchronized with the digital input video signal, a display period signal and a dot clock, the digital input video signal, A data fetching means for fetching the synchronizing signal and the display period signal with the dot clock from the first delay adjusting means and holding the data, a synchronizing signal synchronized with the analog input video signal, and a second delaying the sampling clock. Delay adjustment means, A / D conversion means for converting the analog input video signal into a digital video signal by the sampling clock from the second delay adjustment means, sampling clock from the second delay adjustment means, and the second A first switch for switching and outputting the dot clock from the delay adjusting means A stage, a second switching means for switching and outputting a synchronization signal from the synchronization signal and the data capturing means from said second delay adjustment means, said A /
Third switching means for switching and outputting the digital video signal from the D converting means and the digital video signal from the data capturing means, a control means, and a converting means,
In the case of the analog input video signal, the first switch means is on the sampling clock side from the second delay adjusting means, and the second switch means is on the synchronizing signal side from the second delay adjusting means. In addition, the third switch means is switched to the digital video signal side from the A / D conversion means, and the second means is controlled by the control means according to the data value of the digital video signal from the A / D conversion means. The delay amount of the delay adjusting means is adjusted, the data from the second delay adjusting means is converted into a video signal of a predetermined frequency and a predetermined number of pixels by the converting means, and in the case of the digital input video signal, the first One switch means is on the clock side from the first delay adjusting means, the second switch means is on the synchronization signal side from the data fetching means, and the third switch means is The delay amount of the first delay adjusting means is adjusted by the control means in accordance with the data value held by the data capturing means and switched to the digital video signal side from the data capturing means. The signal conversion device is characterized in that the conversion means converts the data into a video signal having a predetermined frequency and a predetermined number of pixels.

The present invention comprises delay adjusting means for delaying a sampling clock synchronized with an analog input video signal,
A / which converts the analog input video signal into a digital video signal by the sampling clock from the delay adjusting means
D conversion means, fourth switch means for switching and outputting a sampling clock synchronized with the analog input video signal and a dot clock synchronized with the digital input video signal, and the digital input video signal and the digital input video signal Data fetching means for fetching the synchronized sync signal and display period signal and holding the data; second switch means for switching and outputting the sync signal from the delay adjusting means and the sync signal from the data fetching means; Third switch means for switching and outputting the digital video signal from the A / D conversion means and the digital video signal from the data acquisition means; and a control means,
In the case of the analog input video signal, the fourth switch means is provided on the sampling clock side synchronized with the analog input video signal, and the second switch means is provided with the conversion means. The third switch means is switched to the digital video signal side from the A / D conversion means, and the first switching means is controlled by the control means in accordance with the data value from the A / D conversion means. The delay amount of the delay adjusting means is adjusted, the data from the delay adjusting means is converted by the converting means into a video signal of a predetermined frequency and the number of pixels, and in the case of the digital input video signal, the first switch. Means on the clock side synchronized with the digital input video signal, the second switch means on the synchronization signal side from the delay adjusting means, and the third switch means. The delay amount of the delay adjusting unit is adjusted by the control unit according to the data value held by the data capturing unit, and the data from the data capturing unit is switched to the digital video signal side from the data capturing unit. The signal conversion device is characterized in that the conversion unit converts the video signal into a video signal having a predetermined frequency and a predetermined number of pixels.

The present invention displays a signal converter for converting an input video signal into a frequency and a pixel number of a predetermined video signal, and a video signal converted into a predetermined frequency and the pixel number by the signal converter. A video display device including a display device, wherein the signal conversion device described above is used as the signal conversion device.

[0033]

1 is a block diagram of an embodiment of a signal converter according to the present invention. In the figure, 9 is a control circuit and 25 is a delay adjustment circuit. In FIG. 1, the same blocks as those in FIG. 5 are designated by the same reference numerals. In FIG. 1, the delay circuit 30 of FIG. 5 is replaced with a delay adjusting circuit 25, the control circuit 90 is replaced with a new control circuit 9, and the delay amount of the delay adjusting circuit 25 can be adjusted by a control signal from the control circuit 9. There is. The other operations are the same as those in FIG.

Here, a delay amount adjusting method of the delay adjusting circuit 25 will be described with reference to FIG. The video level of this pixel is 255, and the video levels of the pixels before and after it are 0, which is a predetermined video position after the fall (or rise) of the horizontal synchronizing signal HD of the digital format video signal D. The video signal D is input from the input terminals 1, 2, 3 via the receiver for the digital interface. As the input digital video signal D, for example,
As shown in FIG. 6, white pixels (level 255) and black pixels (level 0) are arranged alternately, and white pixels to be searched are arranged n dot clocks after the fall of HD.

Dot clock CKD from input terminal 3
Is set to several points within the variable range of 1 clock by the delay adjustment circuit 25 (0, 1, 2,
(8 steps of 3, 4, 5, 6, 7) The delay amount Ps is changed, and the delayed dot clock CKd is supplied to the flip-flop circuit 24 via the switch 21. The flip-flop circuit 24 takes in the data by the delayed dot clock CKd and supplies it to the video detection circuit 15.

At this time, when the rising edge of the dot clock CKd is within the optimum range, the data is surely fetched, and therefore the video signal D of the input terminals 1 and 2 and the horizontal synchronizing signal H.
D, the vertical synchronization signal VD, and the display period signal DED are accurately supplied to the video detection circuit 15. Next, dot clock C
When the rising of Kd is within the racing range, H
If the trailing edge of D cannot be detected, the trailing edge of HD is delayed by one clock and the leading edge of CKd after n clocks, that is, a predetermined video position is delayed by one clock, and data cannot be reliably captured. The signal D also changes its value and is supplied to the video detection circuit 15.

Therefore, the video detection circuit 15 detects the video level of the pixel at the preset predetermined video position (n clocks after the fall of HD) each time the delay amount is changed, and the dot clock is detected. If the rising edge of CKd is within the optimum range, accurate data is supplied. Therefore, if the rising edge of dot clock CKd is within the racing range, the predetermined video position may shift by one clock. Since the video signal D also has different values, values other than 255 are eventually supplied to the control circuit 9. The control circuit 9 sets the predetermined detection level to 2
It is possible to detect 2 areas (delay amounts 0, 1 and 7) within 1 clock at a position set to 55 and a value other than 255. The delay amount is set by the average value of both delay amounts (= (1 + 7)
/ 2 = 4) can be set as the optimum delay amount farthest from the racing range (with a margin).

FIG. 7 is a flow chart showing the above delay amount adjustment processing. 7, in step (hereinafter step is abbreviated as S) 101, the digital video signal D shown in FIG. 4 is input to the input terminal 1 of the video signal D in FIG. Next, in step S102, the control circuit 9 sets the delay amount Ps to the minimum value, here 0, and determines in step S103 whether the set delay amount Ps exceeds the maximum delay amount Pmax, here 7. If No, the process goes to S104, and the control circuit 9 outputs the delay amount Ps set in the delay adjusting circuit 25. The video detection circuit 15 detects the video level of the pixel n dot clocks after the trailing edge of the horizontal synchronizing signal HD at this time by a level detector (not shown) incorporated therein (S105). S10
At 6, the control circuit 9 receives the level detection result from the video detection circuit 15 and determines whether it is 255. If No, S1
08, and if Yes, the delay amount Ps at that time is stored in a built-in storage unit (not shown) in S107. Then, in S108, the delay amount Ps is increased by one step, and S1
03, and the same processing is performed.

When the level detection is completed with the delay amount Ps of 8 stages and it is determined Yes in S103, S109
go to. As is apparent from FIG. 4, the delay amount having the level of 255 is 2, 3, 4, 5, 6 and is continuous. Therefore, in order to calculate the optimum delay amount Ps, the control circuit 9 adds all the delay amounts stored in S107 in S109, and divides the added value by the stored delay amount number (ΣN). This calculated value is set as the optimum delay amount of the delay amount Ps, output to the delay adjustment circuit 25 (S110), and the adjustment ends. In this way, the optimum delay amount, here, 4 is set in the delay adjustment circuit 25. In the flow chart of FIG. 7, the optimum range is detected and the lacing range is not detected. However, it is easy to detect the lacing range (when the determination result in S106 is No). (Corresponding to the above), and the description of the flowchart is omitted.

As described above, according to the embodiment of the present invention, when the input timing of the input terminal changes depending on the type of the digital interface receiver connected to the input terminal and the frequency of the dot clock. However, similarly to the case where the analog-format video signal is input, the automatic adjustment of the delay amount of the dot clock to the optimum value can automatically avoid the racing and prevent the malfunction. Although the case where the dot clock CKD is delayed has been described above, another method is HD.
Alternatively, the amount of delay of VD may be changed to avoid racing.

FIG. 2 shows a block configuration of another embodiment of the signal conversion apparatus according to the present invention. FIG. 2 shows a case where the delay adjusting circuit 25 of FIG. 1 is deleted and the delay adjusting circuit 7 is shared. 2, the same blocks as those in FIG. 1 are designated by the same reference numerals. 2, the delay adjusting circuit 25 of FIG. 1 is deleted, the switch 21 of FIG. 1 is shifted in front of the delay adjusting circuit 7, and the dot clock CKD from the input terminal 3 of the video signal D and the sampling clock C from the PLL 6 are provided.
KA is switched and supplied to the delay adjustment circuit 7.

In FIG. 2, when the analog video signal A is selected, the terminal a side of the switch 21 is selected and the sampling clock CKA is supplied to the delay adjustment circuit 7. After that, the same operation as in FIG. 1 is performed.

When the digital format video signal D is selected, the terminal b side of the switch 21 is selected and the delay adjusting circuit 7 is selected.
To the dot clock CKD. The delay adjustment circuit 7 adjusts the delay amount of the dot clock CKD to avoid the racing in the flip-flop circuit 24. After that, the same operation as in FIG. 1 is performed.

As a result, as in the case of FIG. 1, racing can be avoided, and at the same time, the delay adjusting circuit is shared, so that it is not necessary to separately provide a delay adjusting circuit for selecting the digital format video signal D. It can also contribute to cost reduction.

FIG. 8 shows a block configuration of a video display device equipped with the signal conversion device described above. The video display device 81 includes a signal conversion device 82 that performs a desired signal conversion on an input video signal having at least a digital input, and a display device 83 that displays the video signal converted by the signal conversion device. Here, as the signal conversion device 82,
By using the signal conversion device described above, it is possible to obtain a video display device that achieves the above effects.

[0046]

According to the present invention, it is possible to obtain a signal conversion device and a video display device capable of taking in correct data even if the input timing of an input digital video signal changes.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration of an embodiment of a signal conversion device according to the present invention.

FIG. 2 is a diagram showing a block configuration of another embodiment of a signal conversion device according to the present invention.

FIG. 3 is a diagram illustrating a method of setting an optimum delay amount of a sampling clock CKA of an analog video signal A.

FIG. 4 is a dot clock C of a video signal D in digital format.
It is a figure explaining the setting method of the optimal delay amount of KD.

FIG. 5 is a diagram showing a conventional block configuration.

FIG. 6 is a diagram showing an example of an input digital video signal.

FIG. 7 is a flowchart showing a delay amount adjustment process according to the present invention.

FIG. 8 is a diagram showing a block configuration of a video display device including the signal conversion device according to the embodiment of the invention.

[Explanation of symbols]

1 ... Video signal D input terminal, 2 ... Video signal D horizontal sync signal, vertical sync signal, display period signal input terminal, 3 ... Video signal D sampling clock input terminal, 4 ... Video signal A input terminal 5, ... Horizontal sync signal and vertical sync signal input terminals of video signal A, 6 ... PLL, 7, 25 ... Delay adjustment circuit, 8 ... A / D converter, 9 ... Control circuit, 10 ... Signal conversion circuit, 11 ... video signal B output terminal, 12 ... video signal B horizontal sync signal, vertical sync signal output terminal, 15 ...
Video detection circuit 21, 22, 23 ... Switch, 24 ... Flip-flop circuit, 30 ... Delay circuit, 81 ... Video display device, 82 ... Signal conversion device, 83 ... Display device, 90 ... Control circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takaaki Matono             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Hitachi Digital Media System             Within the business division (72) Inventor Haruki Takada             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Hitachi Digital Media System             Within the business division (72) Inventor Katsunobu Kimura             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Hitachi Digital Media System             Within the business division (72) Inventor Ryo Hasegawa             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Hitachi Digital Media System             Within the business division F-term (reference) 5C006 AC24 AF23 AF45 BC16 BF24                       FA03 FA04 FA08                 5C063 AC01 BA01 BA03 BA06 CA09                       CA14 CA23 CA36 CA38 DA07                       EB04                 5C082 AA01 AA39 BA26 BB02 BC03                       BC19 BD09 CA32 CA84 CA85                       DA76 MM01

Claims (4)

[Claims] 1. A first delay adjusting means for delaying at least one of a digital input video signal, a synchronization signal synchronized with the digital input video signal, a display period signal and a dot clock, the digital input video signal and the synchronization. The signal and the display period signal with the dot clock from the first delay adjusting means, and the data capturing means for retaining the data, and the first delay adjustment according to the data value of the data retained by the data capturing means. A signal conversion device comprising: a control means for adjusting the delay amount of the means; and a conversion means for converting the data from the data capturing means into a video signal of a predetermined frequency and a predetermined number of pixels. 2. A first delay adjusting means for delaying at least one of a digital input video signal, a synchronizing signal synchronized with the digital input video signal, a display period signal and a dot clock, the digital input video signal and the synchronization. Signal and the display period signal by the dot clock from the first delay adjusting means, the data capturing means for retaining the data, the synchronizing signal synchronized with the analog input video signal, and the second delay adjusting for delaying the sampling clock Means, an A / D conversion means for converting the analog input video signal into a digital video signal with a sampling clock from the second delay adjusting means, a sampling clock from the second delay adjusting means, and the first First switch means for switching and outputting the dot clock from the delay adjusting means; Second switch means for switching and outputting the synchronizing signal from the second delay adjusting means and the synchronizing signal from the data fetching means, a digital video signal from the A / D converting means and the data fetching means. In the case of the analog input video signal, the first switch means includes the third delay means for switching the digital video signal and outputting the digital video signal, the control means, and the conversion means. On the sampling clock side, the second switch means is on the synchronization signal side from the second delay adjusting means, and the third switch means is on the A side.
Is switched to the digital video signal side from the A / D conversion means, and the control means adjusts the delay amount of the second delay adjustment means according to the data value of the digital video signal from the A / D conversion means, The data from the second delay adjusting means is converted by the converting means into a video signal having a predetermined frequency and the number of pixels, and in the case of the digital input video signal, the first switch means causes the first delay adjusting means. The second switch means is switched to the synchronization signal side from the data fetching means, and the third switch means is switched to the digital video signal side from the data fetching means. The delay amount of the first delay adjusting means is adjusted by the control means according to the data value held by A signal conversion device, wherein the conversion means converts the video signal into a video signal having a predetermined frequency and a predetermined number of pixels. 3. A delay adjusting means for delaying a sampling clock synchronized with an analog input video signal, and an A / D converting means for converting the analog input video signal into a digital video signal with a sampling clock from the delay adjusting means. Fourth switch means for switching and outputting a sampling clock synchronized with the analog input video signal and a dot clock synchronized with the digital input video signal, the digital input video signal, a synchronization signal synchronized with the digital input video signal, and Data capturing means for capturing the display period signal and retaining the data; second switch means for switching and outputting the synchronization signal from the delay adjusting means and the synchronization signal from the data capturing means; and the A / D conversion. From the digital video signal from the means and the data capturing means In the case of the analog input video signal, the fourth switch means is synchronized with the analog input video signal, the third switch means switching the digital video signal and outputting the same. The second switch means is switched to the sampling clock side, the second switch means is switched to the synchronizing signal side from the second delay adjusting means, and the third switch means is switched to the digital video signal side from the A / D converting means. The control unit adjusts the delay amount of the first delay adjusting unit according to the data value from the A / D converting unit, and the converting unit converts the data from the delay adjusting unit into an image of a predetermined frequency and a predetermined number of pixels. In the case of the digital input video signal, the first switch means converts the signal into a signal, and the second switch is connected to the clock side synchronized with the digital input video signal. The switch means is switched to the side of the synchronizing signal from the delay adjusting means, and the third switch means is switched to the side of the digital video signal from the data fetching means, and the control means according to the data value held by the data fetching means. The signal conversion device is characterized in that the delay amount of the delay adjusting means is adjusted by the means, and the data from the data capturing means is converted into a video signal of a predetermined frequency and a predetermined number of pixels by the converting means. 4. A signal conversion device for converting an input video signal into a frequency and a pixel number of a predetermined video signal, and a display device for displaying the video signal converted into the predetermined frequency and the pixel number by the signal conversion device. An image display device comprising: a signal conversion device according to claim 1, wherein the signal conversion device is used as the signal conversion device.