JP2003204266A - Current cell type d/a converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current cell type D/A converter in which accuracy is improved. <P>SOLUTION: Gate voltages VG1, VG0 and VG2 are generated by operational amplifiers 15, 25 and 35 constituting current control circuits 10, 20 and 30 provided for each of partial areas formed by dividing a current cell arrangement area into three areas, and the currents of current cell transistors 41, 51 and 61 in the respective partial areas are controlled by using the resultant gate voltages. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current cell type D which generates an analog signal by merging currents flowing through current cell transistors of a number corresponding to digital data.
Related to the A converter. 2. Description of the Related Art Conventionally, a plurality of current cell transistors are provided in a current cell arrangement region, and among the plurality of current cell transistors, the number of current cell transistors corresponding to digital data flows. 2. Description of the Related Art A current cell type DA converter that generates an analog signal according to digital data by combining currents is known. FIG. 3 is a diagram showing a circuit of a conventional current cell type DA converter. A current cell type DA converter 10 shown in FIG.
0 is provided with a current control circuit 110. The current control circuit 110 includes a power supply Vdd and a ground GND.
PMOS transistor 111 connected in series between
And a PMOS transistor 112.
The gate of the PMOS transistor 112 is connected to the power supply Vdd.
And therefore this PMOS transistor 1
12 is always in the off state. In addition, the current control circuit 1
10, one end has PMOS transistors 111 and 112.
A PMOS transistor 113 connected to a connection point of
The other end of the PMOS transistor 113 and the ground G
A resistor 114 is connected between the PMOS transistor 113 and the ND, and an operational amplifier 115 having a positive-phase input terminal (+) connected to the other end of the PMOS transistor 113 and an output terminal connected to the gate of the PMOS transistor 111. ing. Opposite-phase input terminal (-) of operational amplifier 115 and PMOS
The reference voltage VREF is applied to the gate of the transistor 113. [0005] The current cell type DA converter 100 has a predetermined current cell arrangement region, and the current cell DA converter 100 includes a PMOS transistor connected in series between a power supply Vdd and a ground GND. A transistor 121 and a PMOS transistor 122 are provided. Further, one end is connected to the current cell transistor 121.
And the PMOS connected to the connection point of the PMOS transistor 122
A MOS transistor 123 is also provided. The gate of the current cell transistor 121 is connected to the output terminal of the operational amplifier 115. Also, the PMOS transistor 1
Digital data DATA is input to the gate of the gate 22, and the reference voltage VREF is applied to the gate of the PMOS transistor 123. In the current cell type DA converter 100 configured as described above, the current flowing through the PMOS transistor 111 is converted into a monitor voltage by the resistor 114 and input to the positive terminal of the operational amplifier 115. Operational amplifier 11
5 is such that the monitor voltage input to the positive-phase terminal becomes equal to the reference voltage VREF input to the negative-phase terminal.
The gate voltage VG of the MOS transistor 111 is controlled. Further, the PMOS transistor 111 and the current cell transistor 121 constitute a mirror circuit. Therefore, a current corresponding to the current flowing through the PMOS transistor 111 flows through the current cell transistor 121. Here, the PMOS transistor 122 corresponding to the current cell transistor 121 is turned on / off in accordance with the logic of the digital data DATA, whereby the current IOUT corresponding to the digital data DATA flows out through the PMOS transistor 123. Actually, a plurality of current cell transistors 121 (for example, (2 ⁿ -1); n represents a bit width of digital data) are provided. The currents flowing through the current cell transistors 121 corresponding to DATA are combined via the PMOS transistors 123 and converted into analog signals by resistors (not shown). The above-mentioned current cell type D
In the A converter 100, the gate voltage VG generated by the operational amplifier 115 is applied to the gates of a plurality of current cell transistors 121 arranged in a predetermined current cell region. Here, the characteristics of each of the plurality of current cell transistors 121 may vary due to a difference in layout between the plurality of current cell transistors 121. In this case, even if the same gate voltage VG is applied to the plurality of current cell transistors 121, the current flowing through each of the plurality of current cell transistors 121 varies. Then, the current cell type DA
Digital data DA of converter 100
The linearity (linearity) of the change of the analog signal output with respect to the change of TA is deteriorated. For this reason, it is difficult to perform highly accurate DA conversion. Further, as the number of the current cell transistors 121 increases, the layout area of the current cell transistors 121 also increases, so that variations in the characteristics of the current cell transistors 121 due to differences in the layout arrangement also increase. Therefore, there is a problem that it is more difficult to achieve high accuracy with a multi-bit current cell type DA converter. The present invention has been made in view of the above circumstances, and has as its object to provide a current cell type D / A converter with high accuracy. A current cell type DA converter according to the present invention for achieving the above object has a current cell arrangement region in which a plurality of current cell transistors are arranged. Among the current cell type D / A converters that generate an analog signal corresponding to the digital data by merging the currents flowing through the number of current cell transistors corresponding to the digital data. A current control circuit for generating a control signal for controlling current is provided for each of the partial regions in which the current cell arrangement region is divided into a plurality of regions, and the current control circuit generates a control signal for controlling the current of the current cell transistor in each of the partial regions. Is controlled. The current cell type DA converter according to the present invention is characterized in that the current cell in each partial region is controlled by a control signal generated by a current control circuit provided for each partial region in which the current cell arrangement region is divided into a plurality. Since the current of the transistor is controlled, even if the characteristics of each of the plurality of current cell transistors arranged in the current cell arrangement region vary, the current flowing through the current cell transistor in each partial region is almost equal. Can be
Therefore, in comparison with the conventional technique of controlling the current of the plurality of current cell transistors by applying the same gate voltage to the gates of the plurality of current cell transistors, the layout of each of the plurality of current cell transistors is The variation in current caused by the variation in characteristics due to the difference is reduced, the deterioration of the linearity (linearity) of the change of the output analog signal with respect to the change of the input digital data DATA is reduced, and the D / A conversion with high accuracy is achieved. Is performed. An embodiment of the present invention will be described below. FIG. 1 is a block diagram of a current cell type DA converter according to an embodiment of the present invention. The current cell type DA converter 1 shown in FIG. 1 has a first current control circuit 10 and a second current control circuit 2.
0 and a third current control circuit 30. The first current control circuit 10 has twelve PMOS transistors 11_11,..., 11 each having a drain, a source, and a gate connected in common (in parallel).
_0 (in the figure, one PMOS transistor is exemplarily shown) and a PMOS transistor 12 are provided. 1
Two PMOS transistors 11_11,..., 11_0
Are connected to the power supply Vdd, their drains are also connected to the drain of the PMOS transistor 12, and the source of the PMOS transistor 12 is connected to the ground GND. The gate of the PMOS transistor 12 is connected to the power supply Vdd,
Therefore, the PMOS transistor 12 is always off. One end of the first current control circuit 10 is PM
OS transistors 11_11,..., 11_0 and PMOS
A PMOS transistor 13 connected to a connection point of the transistor 12, a resistor 14 connected between the other end of the PMOS transistor 13 and the ground GND, and a positive-phase input terminal (+) connected to the other end of the PMOS transistor 13
, And an operational amplifier 15 whose output terminal is connected to the gates of the PMOS transistors 11_11,..., 11_0. The reference voltage VREF is applied to the negative-phase input terminal (−) of the operational amplifier 15 and the gate of the PMOS transistor 13. The second current control circuit 20 has the same configuration as that of the first current control circuit 10. The second current control circuit 20 is connected in series between a power supply Vdd and a ground GND. Twelve PMOS transistors 21 whose drain, source, and gate are connected in common
_11,..., 21_0 and the PMOS transistor 22
, One end of which is a PMOS transistor 21_11,.
_0 and a PMOS transistor 22 connected to a connection point of the PMOS transistor 22, a resistor 24 connected between the other end of the PMOS transistor 23 and the ground GND, and a positive-phase input terminal connected to the other end of the PMOS transistor 23. (+) Is connected and the output terminal is PMO
, 21_0, and an operational amplifier 25 connected to the gates of the S transistors 21_11,..., 21_0. PMOS
The gate of the transistor 22 is connected to the power supply Vdd, and the negative-phase input terminal (−) of the operational amplifier 25 and the PMOS
The reference voltage VREF is applied to the gate of the transistor 23. The third current control circuit 30 has the same configuration as that of the first current control circuit 10. The third current control circuit 30 is connected in series between a power supply Vdd and a ground GND. Twelve PMOS transistors 31 whose drain, source, and gate are connected in common
_11,..., 31_0 and the PMOS transistor 32
, One end of which is a PMOS transistor 31_11,.
_0, a PMOS transistor 33 connected to a connection point of the PMOS transistor 32, a resistor 34 connected between the other end of the PMOS transistor 33 and the ground GND, and a positive-phase input terminal connected to the other end of the PMOS transistor 33. (+) Is connected and the output terminal is PMO
, 31_0, and an operational amplifier 35 connected to the gates of the S transistors 31_11,..., 31_0. PMOS
The gate of the transistor 32 is connected to the power supply Vdd. The negative-phase input terminal (−) of the operational amplifier 35 and the PMOS
The reference voltage VREF is applied to the gate of the transistor 33. The current cell type DA converter 1 has a current cell region in which a plurality of current cell transistors are arranged. Here, the current cell region will be described with reference to FIG. FIG. 2 is a schematic diagram of a current cell region included in the current cell type DA converter shown in FIG. The current cell region 2 shown in FIG. 2 is divided into three partial regions 2_1, 2_2, and 2_3. The partial area 2_1 includes the partial area 2_1
At the left end; at the center; at the right end, the PM shown in FIG.
, 11_0; 11_7,
, 11_4; 11_11, ..., 11_8 are arranged. A current cell transistor 41 which is a PMOS transistor shown in FIG. 1 is arranged in a portion of the partial region 2_1 except for the left end, the center, and the right end. A gate voltage VG1, which is a control signal from the operational amplifier 15, is applied to the current cell transistor 41. In the partial area 2_2, the partial area 2_2
At the left end; at the center; at the right end, a PMOS transistor 2
1_3, ..., 21_0; 21_7, ..., 21_4; 21
_11, ..., 21_8 are arranged. The current cell transistor 51 shown in FIG. 1 is arranged in a portion of the partial region 2_2 except the left end, the center, and the right end. The operational amplifier 2 is connected to the current cell transistor 51.
5 is applied as a control signal. The partial area 2_3 includes the partial area 2_3
At the left end; at the center; at the right end, a PMOS transistor 3
31_0, 31_7, ..., 31_4; 31
_11, ..., 31_8 are arranged. The current cell transistor 61 shown in FIG. 1 is arranged in a portion of the partial region 2_3 except for the left end, the center, and the right end. The operational amplifier 3 is connected to the current cell transistor 61.
5 is applied as a control signal. Since the resistors 14, 24, 34 and the operational amplifiers 15, 25, 35 are composed of devices arranged in a relatively narrow range on the layout, variations due to the characteristics of these devices are suppressed. I have. In the current cell type DA converter 1, in the first current control circuit 10, the current flowing through the PMOS transistors 11_11,.
, And is input to the positive-phase terminal of the operational amplifier 15. Here, the PMOS transistor 11_
, 11_0 are the partial areas 2_ as described above.
1 are evenly divided and arranged at the left end portion; the center portion; and the right end portion, so that a monitor voltage with high accuracy can be obtained. , 11_0 so that the monitor voltage input to the positive terminal is equal to the reference voltage VREF input to the negative terminal.
Is controlled. , 11_0 and the current cell transistor 41 form a mirror circuit. Therefore, the current cell transistor 41 includes the PMOS transistor 11_1.
A current corresponding to the current flowing through 11, ..., 11_0 flows. Here, PM corresponding to the current cell transistor 41
The OS transistor 42 is turned on and off in accordance with the logic of the digital data DATA, so that a current corresponding to the digital data DATA is supplied to the PMOS transistor 43.
Spill via In the second current control circuit 20, the PM
The current flowing through the OS transistors 21_11,..., 21_0 is converted into a monitor voltage by the resistance element 24 and input to the positive terminal of the operational amplifier 25. The monitor voltage input to the positive terminal of the operational amplifier 25 is input to the negative terminal. The PMOS is set to be equal to the reference voltage VREF.
The gate voltages V of the transistors 21_11,..., 21_0
G0 is controlled. PMOS transistors 21_11,
, 21_0 are equally divided and arranged at the left end portion; the center portion; and the right end portion of the partial region 2_2, so that a monitor voltage with high accuracy can be obtained. Here, the PMOS transistor 52 corresponding to the current cell transistor 51 is turned on and off according to the logic of the digital data DATA, so that the current corresponding to the digital data DATA is changed to PM.
It flows out through the OS transistor 53. Further, in the third current control circuit 30, P
The current flowing through the MOS transistors 31_11,..., 31_0 is converted into a monitor voltage by the resistance element 34 and input to the positive-phase terminal of the operational amplifier 35.
So that the monitor voltage input to the positive-phase terminal becomes equal to the reference voltage VREF input to the negative-phase terminal.
The gate voltages VG2 of the S transistors 31_11,..., 31_0 are controlled. PMOS transistor 31_1
1,..., 31_0 are equally divided and arranged at the left end, the center, and the right end of the partial region 2_3, so that a monitor voltage with high accuracy can be obtained. Here, the PMOS transistor 62 corresponding to the current cell transistor 61 is
It is turned on and off in accordance with the digital data DATA.
It flows out through the OS transistor 63. Furthermore, P
The currents flowing out through the MOS transistors 43, 53, 63 are combined into a combined current IOUT, and the combined current IOUT is converted into an analog signal by a resistor (not shown). As described above, the current cell type DA of this embodiment
Converter 1 includes current control circuits 10, 20, and 30 provided for each of partial regions 2_1, 2_2, and 2_3 obtained by dividing current cell arrangement region 2 into three parts.
Current cell transistors 41, 5 in 1, 2, 2 and 3
1 and 61, respectively, the current cell transistors 4 arranged in the current cell arrangement region 2
Even when the characteristics of the transistors 1, 51, 61 vary, the currents flowing through the current cell transistors 41, 51, 61 can be made substantially equal in the respective partial regions 2_1, 2_2, 2_3. Therefore, in comparison with the conventional technique of controlling the current of the current cell transistor by applying the same gate voltage to the gates of the plurality of current cell transistors,
Variations in current caused by variations in characteristics due to differences in layout of current cell transistors are reduced, and the linearity (linearity) of changes in analog signals output in response to changes in input digital data DATA is reduced. Deterioration is reduced and highly accurate DA conversion is performed. Although the present embodiment has been described with reference to an example in which the current cell arrangement region is divided into three partial regions, the present invention is not limited to this. In the present invention, the current cell arrangement region is divided into a plurality of regions. Just do it. In this embodiment, each partial area has one
Although an example in which one current cell transistor is provided has been described, a plurality of current cell transistors may be provided in each partial region. Furthermore, in the present embodiment, an example has been described in which each partial region is provided with twelve PMOS transistors, but the present invention is not limited to this. For example, one PMOS transistor is provided in each partial region. May be provided. As described above, according to the present invention,
Even when the characteristics of the plurality of current cell transistors vary, the current flowing through the plurality of current cell transistors can be suppressed to a small value, so that a highly accurate current cell type converter can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a current cell type DA converter according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a current cell region included in the current cell type DA converter shown in FIG. FIG. 3 is a diagram showing a circuit of a conventional current cell type DA converter. [Description of Signs] 1 Current cell type DA converter 2 Current cell areas 2_1, 2_2, 2_3 Partial areas 10, 20, 30 Current control circuits 11_11,..., 11_0, 12, 13, 21_11,
..., 21_0, 22, 23, 31_11, ..., 31_
0, 32, 33, 42, 43, 52, 53, 62, 63
PMOS transistors 14, 24, 34 Resistance 15, 25, 35 Operational amplifiers 41, 51, 61 Current cell transistors (PMOS transistors)

Claims (1)

The present invention has a current cell arrangement region in which a plurality of current cell transistors are arranged, and among the plurality of current cell transistors, a number of current cell transistors corresponding to digital data flows. In a current cell type DA converter that generates an analog signal according to the digital data by merging currents, a current control circuit that generates a control signal for controlling a current flowing through each of the plurality of current cell transistors,
A current cell type DA converter, wherein the current cell arrangement region is provided for each of a plurality of divided partial regions, and each current control circuit controls a current of a current cell transistor in each partial region.