JP2003204258A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which impedance matching in an output buffer circuit is rightly performed within the dummy cycles of a prescribed number regardless of the ON sequence of a power source. <P>SOLUTION: The semiconductor device has a clock input circuit for outputting a first internal clock signal by amplifying differentially inputted external clock signals, a clock control circuit for outputting a second internal clock signal having substantially the same cycle as the first internal clock signal only while the voltage of a power source for output buffer is applied, an output buffer circuit having a plurality of transistors connected in parallel, and a programmable impedance circuit to be operated according to the second internal clock signal for matching the impedance of the output buffer circuit by design of a circuit with the voltage of the power source for output buffer as a reference. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an output buffer circuit for outputting data to an input / output terminal, and more particularly to a memory having an adjusting function for adjusting the impedance of the output buffer circuit to an external impedance. Semiconductor device of.

[0002]

2. Description of the Related Art As the performance of MPUs (microprocessors) has improved, the data transfer rate required for storage devices (memory) has also been increasing, and the operating frequency of external cache memories and the like has reached the level of several hundred MHz. ing. In data transfer performed at such high frequency, MPU
Also, the influence of signal reflection on the data bus on the board on which the memory is mounted cannot be ignored, and impedance matching between the output buffer circuit on the memory side and the data bus is required. As the operating frequency increases, the impedance matching accuracy becomes severe. Therefore, the size (driving force) of the transistors that make up the output buffer circuit
Is used as a circuit to adjust the impedance of the output buffer circuit to a desired value (programmable impedance control function).

The programmable impedance control function is the ISSCC 96 FA 9.3: A 300MHz, 3.3V 1Mb SRAM Fabri.
It is embodied by the programmable impedance circuit disclosed in cated in a 0.5um CMOS Process. In this circuit, an external resistor RQ for specifying the impedance of the data bus to be fitted is externally attached to the VZQ terminal. Then, the transistor size of the replica buffer circuit having the same circuit form as the output buffer circuit (or the size of which is a constant multiple) is changed to match the impedance of the replica buffer circuit with the external resistance RQ. Then, by reflecting the value of the counter that determines the transistor size of the replica buffer circuit in the output buffer circuit, the impedance of the output buffer circuit can be matched with the resistance RQ.

For example, when a high-speed memory such as a synchronous high-speed SRAM is provided with a programmable impedance control function, it is specified that a predetermined number of dummy cycles should be inserted after power-on to match the impedance of the output buffer circuit. Required in. That is, using the period of this dummy cycle, the transistor size of the replica buffer circuit is changed and adjusted to the resistor RQ, and the adjustment result is reflected in the output buffer circuit.

When the replica buffer circuit is composed of N bits, that is, N transistors, the impedance of the replica buffer circuit has a resolution of 2 ^N steps, and the counter has a value of 2 ^N steps. Will be taken. Also, the counter value that changes in one dummy cycle is one of 2 ^N steps. Therefore, if the initial state of the replica buffer circuit after power-on is undefined, the worst ^2N cycles of dummy cycles are required. In other words, the impedance must actually be set to the maximum value, but when the initial state of the counter happens to be the minimum value, the counter value must be changed by 2 ^N cycles from the minimum value to the maximum value. .

Further, in a high speed memory to which an external clock signal of several hundred MHz level is input, the programmable impedance circuit cannot operate at such a high speed. This is because, in one dummy cycle, after the transistor size is changed, the analog circuit stabilizes, the external resistance RQ and the replica buffer circuit impedance are compared, and the transistor size is changed based on the comparison result. . Therefore, the external clock signal must be internally divided and used for controlling the programmable impedance circuit. Set the number of cycles of the external clock signal included in one dummy cycle to 32
When the number of cycles is N = 6, the number of cycles of the external clock signal included in the dummy cycle of 2 ⁶ cycles is 32 × 2 ⁶ = 2048 cycles.

In order to reduce the dummy cycle period,
The initial value of the transistor size of the replica buffer circuit is set exactly at the intermediate value. This is because if the initial value is in the middle, the transition to the maximum value and the transition to the minimum value can be completed in half the cycle.

[0008]

Now, consider turning on the power. The programmable impedance circuit has
There are a part driven by a normal power supply (VDD) and a part driven by an output buffer power supply (VDDQ). In a state where the normal power supply is turned on first and the output buffer power supply is not turned on, impedance comparison cannot be normally performed, and impedance matching is impossible.

However, let us consider a state in which only the normal power supply is turned on and the external clock signal is not turned on yet. For example, High Speed Transistor Logic
(HSTL) input, the external clock signal is differential input (C
K, / CK), if CK and / CK are at almost the same level but fluctuates due to the open state, the sense amplifier may pick up a subtle potential difference due to noise and oscillate the internal clock signal. There is a nature.

Then, the programmable impedance circuit starts the impedance matching operation according to the internal clock signal. As described above, the impedance comparison is not normally performed before the power supply for the output buffer is turned on, and the counter value is adjusted toward the minimum value or the maximum value. That is, the counter value initially set to the intermediate value after power-on fluctuates toward the minimum or maximum value. Therefore, when the power supply for the output buffer is turned on and the user starts the clock operation, the counter value is not set to the intermediate value, so it is possible that the desired impedance matching has not been completed even if the necessary dummy cycle is performed. There is a possibility that it will malfunction.

As described above, the impedance of the output buffer circuit may deviate from the initial setting value depending on the timing of turning on the power supply for the output buffer in addition to the normal power supply.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and its object is to prevent the output buffer circuit from being operated during a predetermined number of dummy cycles regardless of the power-on sequence. An object of the present invention is to provide a semiconductor device in which impedance matching is performed correctly.

[0013]

To achieve the above object, the present invention is characterized by a clock input circuit for amplifying a differential input external clock signal and outputting a first internal clock signal, and for an output buffer. A clock control circuit that outputs a second internal clock signal having a signal cycle substantially the same as the first internal clock signal only when the voltage of the power supply is applied, and a plurality of transistors connected in parallel are provided. And a programmable impedance circuit that operates according to the second internal clock signal and that matches the impedance of the output buffer circuit in circuit with reference to the voltage of the output buffer power supply. is there.

The programmable impedance circuit is provided only when the voltage of the output buffer power supply is applied.
It operates according to the second internal clock signal. Therefore, the impedance matching operation based on the voltage of the output buffer power supply can be normally performed. In other words, the programmable impedance circuit does not start the impedance matching operation even if the clock input circuit outputs the first internal clock signal when the power supply for the output buffer is not turned on.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

<Overall Structure of Memory Chip> As shown in FIG. 5, the semiconductor device according to the embodiment of the present invention includes a board (PCB) 1, a memory chip 2 and an MPU 3 mounted on the board 1. , And a data bus 4 that connects the memory chip 2 and the MPU 3. The data bus 4 connects between the input / output terminal 5 of the memory chip 2 and the input / output terminal of the MPU 3. The memory chip 2 includes an internal circuit that realizes a predetermined function and an output buffer circuit that outputs the output data from the internal circuit to the input / output terminal 5. The internal circuit is a memory circuit for realizing a memory function which is a main function of the semiconductor device.

As shown in FIG. 6, the memory chip 2 includes a memory array 21 having a plurality of memory cells arranged in rows and columns, and a row decoder 2 for selecting a desired memory cell.
2 and column selector 23, sense amplifier 24, write buffer 25, address terminal 26 to which address data is input, address terminal 26, row decoder 2
2, an address buffer circuit 27 connected to the column selector 23, an input / output terminal 5 connected to the data bus, an input buffer circuit 28 and an output buffer circuit 8 connected to the input / output terminal 5, and an output buffer. A programmable impedance circuit 9 that automatically adjusts the impedance of the circuit 8, a control terminal 30, a timing control circuit 29 that controls the operation timing during writing or reading, a clock terminal 31 to which an external clock signal is input, and an external clock. A clock input circuit 6 for converting the signal into an internal clock signal (CK _in ).

Address data is input from the address terminal 26 and supplied to the row decoder 22 and the column selector 23 via the address buffer circuit 27. A desired write memory cell or read memory cell in the memory array 21 is selected by the address data.

In FIG. 6, in order to simplify the explanation,
The address terminal 26 and the address buffer circuit 27 are shown one by one. However, the actual address data is composed of n-bit row address data and m-bit column address data. Therefore, the address terminal 26 is n
There are + m address buffer circuits 27, and the address buffer circuit 27 is composed of n row address buffer circuits and m column address buffer circuits. Then, n row address buffer circuits are connected to the row decoder 22, and m column address buffer circuits are connected to the column selector 23.

Similarly, in FIG. 6, the input / output terminals 5,
The input buffer circuit 28 and the output buffer circuit 8 are shown one by one. However, in reality, assuming that the data bus has k bits, correspondingly, the input / output terminal 5, the input buffer circuit 28, and the output buffer circuit 8 respectively have k bits.
There will be an individual.

At the time of writing, the write data input from the input / output terminal 5 is given to the write buffer 25 via the input buffer circuit 28 and written in a desired write cell in the memory array 21. On the other hand, at the time of reading, read data read from the selected read cell is given to the output buffer circuit 8 through the sense amplifier 24, and the output buffer circuit 8 outputs the read data to the input / output terminal 5.
It is driven to the outside of the memory chip 2 via.

The timing control signal input from the control terminal 30 is supplied from the timing control circuit 29 to the row decoder 22, the column selector 23, the sense amplifier 24, and the write buffer 25 to write or read data. The operation timing is controlled.

The programmable impedance circuit 9 is
It has a replica buffer circuit and a ZQ terminal 32. Z
The Q terminal 32 is connected to an external resistor RQ for designating the impedance to be matched. The ground potential is applied to the other end of the external resistor RQ. The programmable impedance circuit 9 automatically searches for a transistor size such that the impedance of the replica buffer circuit becomes equal to the external resistance RQ. Then, the result is reflected in the output buffer circuit 8. The external resistance RQ has a resistance value equal to or a constant multiple of the impedance of the data bus that the user wants to match.

The clock terminal 31 has a differential input external clock.
A lock signal is input. Where the external clock signal
The interface is HSTL specification. HSTL specifications
And two signals (V_inAnd V_ref)
Is a specification for determining the clock level. Clock input
The circuit 6 amplifies a differential input external clock signal and
Internal clock signal (CK_in) Is output. The first
Part clock signal (CK _in) Is the row decoder 22,
RAM selector 23, sense amplifier 24, write buffer
25, address buffer circuit 27, input buffer circuit 2
8, output buffer circuit 8, control circuit 29, and
It is supplied to the clock control circuit 10. these
The circuit includes a first internal clock signal (CK_in) According to
Operate.

The clock control circuit 10 has a second internal clock signal having a signal pattern substantially the same as that of the first internal clock signal (CK _in ) only when the output buffer power supply (VDDQ) is turned on. (/ CK _in ) is output. The programmable impedance circuit 9 operates according to the second internal clock signal (/ CK _in ) output from the clock control circuit 10. The clock control circuit 10 will be described later with reference to FIGS. 1 to 4.

<Structure of Output Buffer Circuit> Next, the detailed structure of the output buffer circuit 8 in the memory chip 2 will be described with reference to FIG. The output buffer circuit 8 has a pull-up transistor group and a pull-down transistor group. The pull-up transistor group includes an offset transistor P0 and a predetermined unit channel width of 2
⁰ times and a five PMOS transistors each having a channel width of up to ^{2 4} times (P1 to P5). The PMOS transistors (P0 to P5) are connected in parallel, one end of the current path is connected to the input / output terminal 5, and the other end of the current path is connected to the high-level output buffer power supply voltage (VDD
Q) is being applied.

The pull-down transistor group, the offset transistor N0, 2 ⁰ of a predetermined unit channel width
Times from and a five NMOS transistors each having a channel width of up to ^{2 4} times (N1-N5). Each N
MOS transistors (N0 to N5) are connected in parallel,
One end of the current path is connected to the input / output terminal 5, and the low level output buffer power supply voltage (VSSQ) is applied to the other end of the current path. Hereinafter, the voltage (VDDQ) of the high-level output buffer power supply will be simply referred to as the "output buffer power-supply voltage (VDDQ)" with the low-level output buffer power supply voltage (VSSQ) as the ground potential.

The PMOS transistors (P0 to P5) and the NMOS transistors (N0 to N5) are counters (43, 4 and 4) in the programmable impedance circuit 9.
4) Conducted by the impedance signal output from /
Each non-conduction is controlled. Each PMOS transistor (P0 to P5) and each NMOS transistor (N0 to N)
The impedance (transistor size) of the output buffer circuit 8 is determined by the conduction / non-conduction of 5). Counter (4 in programmable impedance circuit 9
3, 44) will be described later with reference to FIG.

Since the pull-up transistor group and the pull-down transistor group are composed of different types of transistors, it is necessary to perform impedance matching of two different systems. That is, for one output buffer circuit 8, it is necessary to prepare two systems of programmable impedance circuits 9 including a pull-up control system and a pull-down control system.

<Configuration of Programmable Impedance Circuit> Next, the programmable impedance circuit 9 will be described with reference to FIG. The programmable impedance circuit 9 includes a replica buffer circuit (40, 41) having a plurality of transistors connected in parallel, and an external resistor RQ and a replica buffer circuit (40, 41) based on the voltage (VDDQ) of the output buffer power supply. 41) using the comparison result of the comparison circuit 42 for comparing the impedances of the replica buffer circuit (40, 4).
A counter (4) for individually controlling ON / OFF of a plurality of transistors included in the replica buffer circuit (40, 41) so that the impedance of 1) and the external resistance RQ are matched.
3, 44).

The replica buffer circuit (40, 41) is
It has a circuit configuration similar to that of the output buffer circuit 8 or a circuit configuration having a transistor size that is a constant multiple. That is, a plurality of transistors (N1
1~N15, P11~P15) has respectively a channel width of up to ^{2 4} times ^{2 0} times the predetermined unit channel width. In addition, the counters (43, 44) are provided with a second internal clock signal (/ CK output from the clock control circuit.
_in ). The programmable impedance circuit 9 controls the impedance of the output buffer circuit 8 using the on / off information of the plurality of transistors included in the counters (43, 44).

The programmable impedance circuit 9 includes a pull-up control system for matching the impedance of the pull-up transistor group (P0 to P5) of the output buffer circuit 8 and a pull-down transistor group (N0).
˜N5) and a pull-down control system for matching impedance. Therefore, the replica buffer circuit (4
0, 41) is a pull-up replica buffer circuit 41
And a pull-down replica buffer circuit 40.
The counters (43, 44) have a pull-up counter 44 and a pull-down counter 43.

First, the pull-down control system will be described. The comparison circuit 42 includes an NMOS transistor N21 having one end of the current path connected to the ZQ terminal 32, and a PMO having the other end of the current path of the NMOS transistor N21.
S transistor P21 and PMOS transistor P21
And a PMOS transistor P23 having a common gate. The voltage (VDD) of the normal power supply is applied to the drains of the PMOS transistors (P21, P23). The gate of the NMOS transistor N21 is connected to the output terminal of the operational amplifier OP1. Operational amplifier OP1
The inverting input terminal of is connected to the ZQ terminal 32, and the voltage level of VDDQ / 2 is applied to the non-inverting input terminal.
Therefore, the gate level of the NMOS transistor N21 is controlled by the operational amplifier OP1 so that the voltage VZQ of the ZQ terminal 32 becomes VDDQ / 2.

The source of the PMOS transistor P23 is connected to the inverting input terminal of the operational amplifier OP2, and the node RE
VDDQ / 2 is supplied to the FIU. On the other hand, the voltage VZQ is supplied to the non-inverting input terminal of the operational amplifier OP2. The counter 43 uses the output data (D0 to D4) to output the NMOS of the pull-down side replica buffer circuit 40.
Conduction and non-conduction are selectively controlled for the transistor groups (N11 to N15). NMOS transistor group (N1
The drains of 1 to N15) are fed back to the inverting input terminal of the operational amplifier OP2 via the node REFIU. The voltage VZQ and the voltage of the node REFIU are the operational amplifier OP.
2 compared. The comparison result is input to the counter 43 as a U / D signal. The operational amplifier OP2 is VDD
The voltage comparison is performed based on Q / 2. Therefore, the operational amplifier OP2 cannot operate normally when the output buffer power supply (VDDQ) is not turned on.

The counter 43 has a voltage VZQ and a node R.
Each transistor (N11 included in the pull-down side replica buffer circuit 40 is configured so that the EFIU voltages match.
Up to N15), up / down counting is performed.
The counter value (D0 to D5) of the counter 43 indicates the buffer size (impedance) of the pull-down replica buffer circuit 40 and is supplied to the output buffer circuit 8.

Next, the pull-up control system will be described. The comparison circuit 42 further includes a PMOS transistor P21 and a PMOS transistor P22 having a common gate. The voltage (VDD) of the normal power supply is applied to the drain of the PMOS transistor P22. The source of the PMOS transistor P22 is the NMOS transistor N2.
3 is connected to the gate. NMOS transistor N
The ground potential is applied to the source of 23, and the drain is connected to the inverting input terminal of the operational amplifier OP3. Therefore, VDDQ / 2 is supplied to the node REFID.
On the other hand, the voltage VZ is applied to the non-inverting input terminal of the operational amplifier OP3.
Q is being supplied.

The counter 44 outputs the output data (U0-U
By 4), the PMOS transistor group (P11 to P15) of the pull-up side replica buffer circuit 41 is selectively controlled to be conductive or non-conductive. The drains of the PMOS transistor groups (P11 to P15) are connected to the node REFID.
Is fed back to the inverting input terminal of the operational amplifier OP3. The voltage VZQ and the voltage of the node REFID are compared by the operational amplifier OP3. The comparison result is input to the counter 44 as a U / D signal. Operational amplifier OP3
Performs voltage comparison based on VDDQ / 2.
Therefore, when the output buffer power supply (VDDQ) is not turned on, the operational amplifier OP3 cannot operate normally.

The counter 44 has a voltage VZQ and a node R.
Each transistor (P11) included in the pull-up side replica buffer circuit 41 is arranged so that the EFID voltages match.
Up to P15), up / down counting is performed.
The counter value (U0 to U5) of the counter 44 indicates the buffer size (impedance) of the pull-up side replica buffer circuit 41 and is supplied to the output buffer circuit 8.

The up / down count is a dummy.
It is performed every cycle. Immediately after turning on the power
Repeated up / down count during cycle
By executing the replica buffer circuit (40, 4
Resistor R by changing the transistor size of 1) stepwise
Adjust to Q. In addition, the replica buffer circuit (40,
41) consists of 5 transistors each
Therefore, the counter value is 2 ⁵It will take the value of the stage.
The initial value of the counter value is 2⁵Just in the middle of the stage
Is set to the value of.

<Regarding Clock Control Circuit> FIG. 1 is a block diagram for explaining the function of the clock control circuit 10. External clock signal (CK, / CK) of differential input
Are input to the clock input circuit 6. The clock input circuit 6 is a differential input external clock signal (CK, / CK).
Is a differential amplifier that amplifies and converts it into a first internal clock signal (CK _in ). The clock input circuit 6 compares the levels of the differential input external clock signals (CK, / CK) and amplifies the level difference to the power supply voltage level (VDD) to generate the first clock signal (CK _in ). . As shown in FIG. 6, the first clock signal (CK _in ) is supplied to other circuits 7 in the memory chip 2 except the programmable impedance circuit 9. The other circuit 7 operates according to the first clock signal (CK _in ). The clock input circuit 6 is a circuit that operates on condition that the normal power supply (VDD) is turned on. Therefore, if the normal power supply (VDD) is turned on, the first clock signal (CK _in ) is output regardless of whether or not the output buffer power supply (VDDQ) is turned on. The read data output from the sense amplifier 24, which is one of the other circuits 7, is driven by the output buffer circuit 8 and output from the input / output terminal 5.

On the other hand, programmable impedance circuit
The first clock signal (CK _in) Is entered directly
It is not. Clock control circuit 10
Connected between path 6 and program impedance circuit 9
ing. Programmable impedance circuit 9
Second internal clock signal output from the clock control circuit 10.
Issue (/ CK_{in '}). Second internal black
Clock signal (/ CK_{in '}) Is the first clock signal (C
K_in) Has almost the same signal pattern. Here, "the same
The same signal pattern has the same clock signal period.
The signal level does not matter.

The clock control circuit 10 is provided only when the voltage (VDDQ) of the output buffer power supply is applied.
The second internal clock signal (/ CK _{in '} ) is output.
Therefore, only when the normal power supply (VDD) and the output buffer power supply (VDDQ) are also turned on,
The second clock signal (/ CK _{in '} ) is output. That is, if neither VDD nor VDDQ is applied, the second clock signal (/ CK _{in '} ) is not output.

As shown in FIG. 2A, as the clock control circuit 10, a NAND circuit 11 which receives the first internal clock signal (CK _in ) and the output buffer power supply voltage (VDDQ) is used. it can. In particular,
As shown in FIG. 2B, the NAND circuit 11 includes two PMOS transistors (61, 62) connected in parallel.
And two NMOS transistors (6
3, 64). PMOS transistor (61,
The drain of the NMOS transistor 63 is connected to the source of 62). PMOS transistor (6
A normal power supply voltage (VDD) is applied to the drains of (1, 62) and the ground potential is applied to the source of the NMOS transistor 64. That is, the NAND circuit 11 is a circuit driven by a normal power supply voltage (VDD).

The first internal clock signal (CK _in ) is
PMOS transistor 61 and NMOS transistor 6
It is input to each of the 3 gates. The output buffer power supply voltage (VDDQ) is input to the gates of the PMOS transistor 62 and the NMOS transistor 64, respectively. The second clock signal (/ CK _{in '} ) is P
It is output from the sources of the MOS transistors (61, 62).

When the voltage (VDDQ) of the power supply for the output buffer is not turned on and is at the low level, the second clock signal (/ CK _{in '} ) is generated even if the first internal clock signal (CK _in ) operates. Fixed at high level.

When VDD> VDDQ, in the NAND circuit 11 shown in FIGS. 2A and 2B, after VDDQ is turned on, the PMOS transistor 62 is not completely turned off and a through current flows. There is a possibility that it will end up. In such a case, the inverter circuit 12 as shown in FIG. 3 may be used as the clock control circuit 10. The inverter circuit 12 is a circuit that receives the first internal clock signal (CK _in ) as an input and is driven by the output buffer power supply (VDDQ). If the voltage (VDDQ) of the power supply for the output buffer is not applied, the second clock signal (/ CK _{in '} )
Is fixed to low level. Also, VDD> VDDQ
In such a case, a through current does not flow after VDDQ is turned on.

On the contrary, when VDD <VDDQ, a through current may flow through the inverter circuit 12 shown in FIG. In such a case, the level shift circuit 13 as shown in FIG. 4 may be used as the clock control circuit 10. The level shift circuit 13 is a circuit that changes the voltage level of the first internal clock signal (CK _in ) to the voltage level (VDDQ) of the output buffer power supply.

The level shift circuit 13 has two PMOSs.
Transistors (65, 66) and two NMOS transistors
And transistors (67, 68). First internal clock
Signal (CK_in) Is the current of the NMOS transistor 67
One end of the path and the gate of the NMOS transistor 68
It has been entered. Current path of NMOS transistor 67
The other end of the source of the PMOS transistor 65 and P
Connected to the gate of the MOS transistor 66
There is. Drain of PMOS transistor (65, 66)
The output buffer power supply voltage (VDDQ) is applied to
There is. PMOS transistor gate, PMOS transistor
The source of the transistor 66 and the NMOS transistor 68
The drains are connected together and the second internal clock signal
(/ CK _{in '}) Is output. Level shift circuit 13
Is the second internal clock signal (/ CK_{in '}) To VDD
It can be output at the Q level.

As described above, the comparison circuit 42 has V
The impedance is compared with DDQ / 2 as a reference. Further, the pull-up side counter 41 and the pull-down side counter 40 have the second internal clock signal (/ CK
_{in '} ). The second internal clock signal (/ CK _{in '} ) is output from the clock control circuit 10 only when the voltage of the output buffer power supply is applied. Therefore, the programmable impedance circuit 9
Is the second internal clock signal (/ CK only when the voltage (VDDQ) of the power supply for the output buffer is applied.
_{in '} ). Therefore, the impedance matching operation based on the voltage (VDDQ) of the output buffer power supply can be normally performed. In other words,
Even if the clock input circuit 6 outputs the first internal clock signal (CK _in ) while the power supply for output buffer (VDDQ) is not turned on, the programmable impedance circuit 9 starts the impedance matching operation. There is no.

In the semiconductor memory device equipped with the programmable impedance control function, when the power supply for the output buffer (VDDQ) is not turned on, the second clock signal for controlling the programmable impedance circuit 9 is kept in a fixed state, so that the impedance is controlled. The control function can be kept inactive.

Therefore, the power supply for the output buffer (VDDQ)
It becomes possible to prevent the programmable impedance circuit 9 from starting to operate before the input of, and adjust the counter value whose initial value is set to the intermediate value toward the minimum value or the maximum value. Therefore, the matching of the desired impedance can be surely completed by the predetermined number of dummy cycles.

[0052]

As described above, according to the present invention,
It is possible to provide a semiconductor device in which impedance matching of an output buffer circuit is correctly performed during a predetermined number of dummy cycles regardless of a power-on sequence.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a function of a clock control circuit according to an embodiment of the present invention.

FIG. 2A is a NAN as a clock control circuit.
FIG. 2B is a logic circuit diagram showing a D circuit, and FIG.
It is a concrete circuit diagram of a circuit.

FIG. 3 is a circuit diagram of an inverter circuit as a clock control circuit.

FIG. 4 is a circuit diagram of a level shift circuit as a clock control circuit.

FIG. 5 is a plan view showing an overall configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a memory chip in the semiconductor device.

FIG. 7 is a circuit diagram showing a configuration of an output buffer circuit in the memory chip.

FIG. 8 is a circuit diagram showing a configuration of a programmable impedance circuit in a memory chip.

[Explanation of symbols]

1 board (PCB) 2 memory chip 3 MPU 4 data bus 5 input / output terminal 6 clock input circuit 7 other circuit 8 output buffer circuit 9 programmable impedance circuit 10 clock control circuit 11 NAND circuit 12 inverter circuit 13 level shift circuit 40 pull-down side Replica buffer circuit 41 Pull-up side replica buffer circuit 42 Comparison circuits 43, 44 Counter CK _in First internal clock signal / CK _{in '} Second internal clock signal RQ External resistance VDD Normal power supply VDDQ Power supply for output buffer

Claims (6)

[Claims] 1. A clock input circuit for amplifying an external clock signal of a differential input to output a first internal clock signal, and the first internal circuit only when a voltage of a power supply for an output buffer is applied. A clock control circuit for outputting a second internal clock signal having substantially the same signal cycle as the clock signal; an output buffer circuit having a plurality of transistors connected in parallel; and an operating circuit according to the second internal clock signal. And a programmable impedance circuit for circuit-matching the impedance of the output buffer circuit with the voltage of the output buffer power supply as a reference. 2. The programmable impedance circuit compares the impedances of a replica buffer circuit having a plurality of transistors connected in parallel with each other and an external resistance and the impedance of the replica buffer circuit on the basis of the voltage of the output buffer power supply. A comparator circuit, which operates according to the second internal clock signal, and uses the comparison result of the comparator circuit, and the plurality of transistors included in the replica buffer circuit so that the impedance of the replica buffer circuit and the external resistance match. 2. The semiconductor device according to claim 1, further comprising a counter for individually controlling ON / OFF of the output buffer circuit, the ON / OFF information of the plurality of transistors included in the counter being used to control the impedance of the output buffer circuit. 3. The clock control circuit comprises a NAND circuit that receives the first internal clock signal and the voltage of the output buffer power supply, respectively, and the second internal clock signal is output from the NAND circuit. 3. The semiconductor device according to claim 1, which is an output signal of 4. The clock control circuit comprises an inverter circuit which receives the first internal clock signal as an input and is driven by the power supply for the output buffer, and the second internal clock signal is supplied from the inverter circuit. It is an output signal, The semiconductor device of Claim 1 or 2 characterized by the above-mentioned. 5. The clock control circuit comprises a level shift circuit for changing the voltage level of the first internal clock signal to the voltage level of the output buffer power supply, and the second internal clock signal is 3. The output signal from the level shift circuit, according to claim 1 or 2.
The semiconductor device described. 6. The semiconductor device according to claim 1, wherein the interface of the external clock signal has HSTL specifications.