JP2003204129A - Printed wiring board and its manufacturing method - Google Patents
Printed wiring board and its manufacturing methodInfo
- Publication number
- JP2003204129A JP2003204129A JP2002003046A JP2002003046A JP2003204129A JP 2003204129 A JP2003204129 A JP 2003204129A JP 2002003046 A JP2002003046 A JP 2002003046A JP 2002003046 A JP2002003046 A JP 2002003046A JP 2003204129 A JP2003204129 A JP 2003204129A
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- wiring board
- line conductor
- printed wiring
- ground layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高周波回路用とし
て好適なプリント配線基板及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board suitable for high frequency circuits and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】プリント配線基板上で高周波信号を伝送
する場合、信号線導体間でクロス・トーク（漏話）が起
こり易いので、その低減手段が種々と提案されている。2. Description of the Related Art When transmitting a high frequency signal on a printed wiring board, cross talk (crosstalk) is likely to occur between signal line conductors, and various means for reducing it have been proposed.
【０００３】前記クロス・トークを回避するには、信号
線導体間の電気的結合を疎にすれば良く、例えば、信号
線導体間隔を拡げる、信号線導体近傍に接地導体を設け
るなどの手段が知られている。In order to avoid the cross talk, the electrical coupling between the signal line conductors may be made sparse, and, for example, means such as widening the signal line conductor interval or providing a ground conductor in the vicinity of the signal line conductors are available. Are known.
【０００４】前記手段を基本とするプリント配線基板の
構造として、信号線導体の回路パターン層をグランド線
パターン層で挟んだストリップ・ライン構造やマイクロ
・ストリップ・ライン構造を用いることが知られ、これ
に依って、所望の特性インピーダンスを実現し、また、
クロス・トークの低減を図っている。As a structure of a printed wiring board based on the above means, it is known to use a strip line structure or a micro strip line structure in which a circuit pattern layer of a signal line conductor is sandwiched by ground line pattern layers. To achieve the desired characteristic impedance, and
We are trying to reduce cross talk.
【０００５】また、高周波信号の伝播特性はプリント配
線基板材料の比誘電率に依存しているので、伝播損失が
少ない信号線導体を実現するには、低誘電率材料を用い
ることが必要であることは良く知られている。Further, since the propagation characteristics of high frequency signals depend on the relative dielectric constant of the printed wiring board material, it is necessary to use a low dielectric constant material in order to realize a signal line conductor with a small propagation loss. It is well known.
【０００６】前記クロス・トークを回避する為、信号線
導体間隔を拡げる手段を採った場合には、配線密度の低
下、或いは、信号伝送損失などが問題となり、また、信
号線導体間に接地導体を設ける手段を採った場合には、
同一信号を伝播する信号線導体間でのクロス・トークは
改善されるのであるが、異なる信号を伝播する信号線導
体間でのクロス・トークを防止することは殆ど不可能で
ある。[0006] In order to avoid the cross talk, if a means for expanding the distance between the signal line conductors is adopted, a decrease in wiring density or signal transmission loss becomes a problem, and a ground conductor is provided between the signal line conductors. When the means to provide
Although cross talk between signal line conductors that propagate the same signal is improved, it is almost impossible to prevent cross talk between signal line conductors that propagate different signals.
【０００７】また、プリント配線基板自体にはシールド
層がない為、外来ノイズの影響を受け易く、その影響を
排除するには、導電性シールド・ケースなどを設けて遮
蔽することが必要であった。Further, since the printed wiring board itself has no shield layer, it is easily affected by external noise, and in order to eliminate the effect, it is necessary to provide a conductive shield case or the like for shielding. .
【０００８】更にまた、近年、クロック周波数がギガヘ
ルツの程度になっている高周波デバイスでは、ポリイミ
ドなど比誘電率が３程度のプリント配線基板材料を用い
ているが、そのプリント配線基板材料を更に低誘電率化
するには限界がある。Furthermore, in recent years, in a high frequency device whose clock frequency is in the order of gigahertz, a printed wiring board material having a relative dielectric constant of about 3 such as polyimide is used. There is a limit to rationalization.
【０００９】[0009]
【発明が解決しようとする課題】本発明では、高周波デ
バイスを高密度で実装することが可能であり、また、ク
ロス・トークがなく、高周波信号を取り扱う回路に好適
なプリント配線基板を従来の技術に於ける製造工程を変
更することなく実現しようとする。SUMMARY OF THE INVENTION In the present invention, it is possible to mount a high frequency device at a high density, and there is no cross talk, so that a printed wiring board suitable for a circuit that handles a high frequency signal is provided in the prior art. I will try to realize it without changing the manufacturing process.
【００１０】[0010]
【課題を解決するための手段】本発明では、金属からな
る信号線導体の周囲に於ける上面及び左右両側面に空洞
が形成され且つ該空洞の上方には１／４波長以下の長さ
及び間隔をもって形成された開口が形成されたシールド
導体層が配設された同軸構造をプリント配線基板に組み
込むことが基本になっている。According to the present invention, a cavity is formed on the upper surface and both left and right side surfaces around a signal line conductor made of metal, and a cavity having a length of 1/4 wavelength or less is formed above the cavity. Basically, a coaxial structure in which a shield conductor layer having openings formed at intervals is arranged is incorporated into a printed wiring board.
【００１１】前記したように、シールド導体層に１／４
波長以下の長さ及び間隔をもって開口を形成したことに
依って、信号線導体のインピーダンス低減、信号線間に
於ける電磁誘導に依る干渉防止、外部からの静電誘導ノ
イズの低減を実現させ、高周波特性の劣化を抑制するこ
とができ、また、前記同軸構造は、従来の薄膜多層配線
基板を作製する為の従来の加工技術を適用することで容
易に作製することができるので、既存の技術で容易に対
応することが可能である。As described above, the shield conductor layer has a 1/4
By forming the openings with a length and spacing less than the wavelength, it is possible to reduce the impedance of the signal line conductor, prevent interference due to electromagnetic induction between the signal lines, and reduce electrostatic induction noise from the outside. Since the deterioration of high frequency characteristics can be suppressed, and the coaxial structure can be easily manufactured by applying a conventional processing technique for manufacturing a conventional thin film multilayer wiring board, the existing technology can be used. Can be dealt with easily.
【００１２】[0012]
【発明の実施の形態】図１は本発明の一実施の形態であ
るプリント配線基板を表す要部説明図であって、（Ａ）
は要部平面を、また、（Ｂ）は要部切断側面をそれぞれ
示している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a main part of a printed wiring board which is an embodiment of the present invention.
Shows a plane of a main part, and (B) shows a side surface for cutting a main part.
【００１３】図に於いて、１は基板、２は第１グランド
層、３は第１遮蔽壁、４は第１絶縁層、５は信号線導
体、６は第２遮蔽壁、８は第３遮蔽壁、９は第２絶縁
層、１１は第２グランド層、１１Ａは開口をそれぞれ示
している。In the figure, 1 is a substrate, 2 is a first ground layer, 3 is a first shielding wall, 4 is a first insulating layer, 5 is a signal line conductor, 6 is a second shielding wall, and 8 is a third. A shielding wall, 9 is a second insulating layer, 11 is a second ground layer, and 11A is an opening.
【００１４】図２乃至５は本発明の一実施の形態である
プリント配線基板を製造する工程を説明する為の工程要
所に於けるプリント配線基板を表す要部切断側面図であ
り、以下、図を参照しつつ説明する。尚、図１に於いて
用いた記号と同記号は同部分を表すか或いは同じ意味を
持つものとする。2 to 5 are side sectional views showing the principal part of the printed wiring board in the process steps for explaining the steps of manufacturing the printed wiring board according to the embodiment of the present invention. Description will be made with reference to the drawings. The same symbols as those used in FIG. 1 represent the same parts or have the same meanings.
【００１５】図２（Ａ）参照
（１）スパッタリング法を適用することに依り、ほうけ
い酸ガラス（ｐｈｏｓｐｈｏ−ｓｉｌｉｃａｔｅ ｇｌ
ａｓｓ：ＰＳＧ）からなる基板１の表面に電解銅めっき
する為のＣｒ／Ｃｕからなるシード層を形成する。尚、
シード層は厚さが０．０８〔μｍ〕／０．０８〔μｍ〕
と大変薄いものであるから図示していない。See FIG. 2A. (1) By applying the sputtering method, borosilicate glass (phospho-silicate gl)
A seed layer made of Cr / Cu for electrolytic copper plating is formed on the surface of the substrate 1 made of (ass: PSG). still,
The seed layer has a thickness of 0.08 [μm] /0.08 [μm]
It is not shown because it is very thin.
【００１６】（２）電解めっき法を適用することに依
り、シード層表面に厚さ５〔μｍ〕の銅からなる第１グ
ランド層２を形成する。(2) The first ground layer 2 made of copper and having a thickness of 5 [μm] is formed on the surface of the seed layer by applying the electrolytic plating method.
【００１７】図２（Ｂ）参照
（３）リソグラフィ技術に於けるレジスト・プロセスを
適用することに依り、厚さ１０〔μｍ〕のレジスト膜を
形成する。Referring to FIG. 2B, (3) a resist film having a thickness of 10 [μm] is formed by applying a resist process in the lithography technique.
【００１８】（４）所要のマスク・パターンが形成され
ているガラス・マスクを介し、水銀ランプを用いて４０
０〔Ｍｍｊ／ｃｍ2 〕の露光を行ってから、アルカリ現
像液を用いて露光領域を溶解除去してレジスト膜をパタ
ーニングする。(4) 40 using a mercury lamp through a glass mask on which a required mask pattern is formed.
After exposure of 0 [Mmj / cm 2 ] is performed, the exposed region is dissolved and removed by using an alkali developing solution to pattern the resist film.
【００１９】図２（Ｃ）参照
（５）電解めっき法を適用することに依り、第１グラン
ド層２の表面に厚さ５〔μｍ〕の銅からなる第１遮蔽壁
３を形成する。Referring to FIG. 2 (C) (5), by applying the electrolytic plating method, the first shielding wall 3 made of copper and having a thickness of 5 [μm] is formed on the surface of the first ground layer 2.
【００２０】（６）スピン・コート法を適用することに
依り、第１遮蔽壁３及び第１グランド層２の全面に非感
光性のポリイミド（ｐｏｌｙｉｍｉｄｅ：ＰＩ）を塗布
して厚さ１０〔μｍ〕の樹脂絶縁層を形成する。(6) By applying the spin coating method, a non-photosensitive polyimide (PI) is applied on the entire surfaces of the first shielding wall 3 and the first ground layer 2 to form a thickness of 10 μm. ] The resin insulating layer is formed.
【００２１】（７）温度８０〔℃〕、時間３０〔分〕の
乾燥、引き続き温度３５０〔℃〕、時間３０〔分〕の加
熱を行って樹脂絶縁層を硬化させて第１絶縁層４とす
る。(7) Drying at a temperature of 80 [° C.] for a time of 30 [minutes] and then heating at a temperature of 350 [° C.] for a time of 30 [minutes] to cure the resin insulating layer to form the first insulating layer 4. To do.
【００２２】図３（Ａ）参照
（８）化学機械研磨（ｃｈｅｍｉｃａｌ ｍｅｃｈａｎ
ｉｃａｌ ｐｏｌｉｓｈｉｎｇ：ＣＭＰ）法を適用する
ことに依り、第１絶縁層４を研磨し、第１遮蔽壁３の頂
面を表出させる。See FIG. 3 (A) (8) Chemical mechanical polishing (chemical mechanical polishing)
The first insulating layer 4 is polished by applying the chemical polishing (CMP) method to expose the top surface of the first shielding wall 3.
【００２３】（９）スパッタリング法を適用することに
依り、第１絶縁層４上を含めた全面に電解銅めっきを行
う為のＣｒ／Ｃｕからなるシード層を形成する。尚、シ
ード層は図示していない。(9) By applying the sputtering method, a seed layer made of Cr / Cu for electrolytic copper plating is formed on the entire surface including the first insulating layer 4. The seed layer is not shown.
【００２４】図３（Ｂ）参照
（１０）リソグラフィ技術に於けるレジスト・プロセス
を適用することに依り、全面に厚さ１０〔μｍ〕のレジ
スト膜を形成する。Referring to FIG. 3B (10), by applying a resist process in the lithography technique, a resist film having a thickness of 10 [μm] is formed on the entire surface.
【００２５】（１１）所要のマスク・パターンが形成さ
れているガラス・マスクを介し、前記レジスト膜に水銀
ランプを用いて４００〔Ｍｍｊ／ｃｍ2 〕の露光を行っ
てから、アルカリ現像液を用いて露光領域を溶解除去
し、第１遮蔽壁３上及び信号線導体形成予定部分に開口
を形成する。(11) The resist film is exposed to 400 [Mmj / cm 2 ] with a mercury lamp through a glass mask on which a required mask pattern is formed, and then an alkaline developer is used. Then, the exposed region is dissolved and removed, and an opening is formed on the first shield wall 3 and a portion where the signal line conductor is to be formed.
【００２６】（１２）電解めっき法を適用することに依
り、第１遮蔽壁３上の開口内及び第１絶縁層４上の信号
線導体形成予定部分の開口内に厚さ５〔μｍ〕の銅をめ
っきして第２遮蔽壁６及び信号線導体５を形成する。(12) By applying the electroplating method, a thickness of 5 [μm] is formed in the opening on the first shield wall 3 and the opening in the portion where the signal line conductor is to be formed on the first insulating layer 4. The second shield wall 6 and the signal line conductor 5 are formed by plating copper.
【００２７】図３（Ｃ）参照
（１３）リソグラフィ技術に於けるレジスト・プロセス
を適用することに依り、全面に厚さ１０〔μｍ〕のレジ
スト膜７（犠牲膜）を形成する。Referring to FIG. 3C (13), by applying a resist process in the lithography technique, a resist film 7 (sacrificial film) having a thickness of 10 [μm] is formed on the entire surface.
【００２８】（１４）所要のマスク・パターンが形成さ
れているガラス・マスクを介し、レジスト膜７に水銀ラ
ンプを用いて４００〔Ｍｍｊ／ｃｍ2 〕の露光を行って
から、アルカリ現像液を用いて露光領域を溶解除去し、
第２遮蔽壁６上に開口を形成する。(14) The resist film 7 is exposed to 400 [Mmj / cm 2 ] through a glass mask on which a required mask pattern is formed, using a mercury lamp, and then an alkaline developing solution is used. To dissolve and remove the exposed area,
An opening is formed on the second shielding wall 6.
【００２９】（１５）電解めっき法を適用することに依
り、第２遮蔽壁６上の開口内に厚さ５〔μｍ〕の銅をめ
っきして第３遮蔽壁８を形成する。(15) By applying the electrolytic plating method, copper having a thickness of 5 [μm] is plated in the opening on the second shield wall 6 to form the third shield wall 8.
【００３０】図４（Ａ）参照
（１６）所要のマスク・パターンが形成されているガラ
ス・マスクを介し、レジスト膜７に水銀ランプを用いて
４００〔Ｍｍｊ／ｃｍ2 〕の露光を行ってから、アルカ
リ現像液を用いて露光領域を溶解し、第１、第２、第３
と積層されてなる遮蔽壁の間に在って、且つ、信号線導
体５が存在しない領域を覆っているレジスト膜７を除去
して空所を形成する。See FIG. 4A. (16) After exposing the resist film 7 to 400 [Mmj / cm 2 ] using a mercury lamp through a glass mask on which a required mask pattern is formed, , The exposed area is dissolved using an alkaline developer, and the first, second, and third
The resist film 7 which covers the region where the signal line conductor 5 does not exist and which is present between the shielding walls formed by laminating is formed a void.
【００３１】図４（Ｂ）参照
（１７）スピン・コート法を適用することに依り、全面
に非感光性ＰＩを塗布して厚さ１０〔μｍ〕の樹脂絶縁
層を形成する。4 (B) (17) By applying the spin coating method, non-photosensitive PI is applied to the entire surface to form a resin insulating layer having a thickness of 10 μm.
【００３２】（１８）温度８０〔℃〕、時間３０〔分〕
の乾燥、引き続き温度３５０〔℃〕、時間３０〔分〕の
加熱を行って樹脂絶縁層を硬化させて第２絶縁層９とす
る。(18) Temperature 80 [° C.], time 30 [min]
And subsequently, heating is performed at a temperature of 350 ° C. for a time of 30 minutes to cure the resin insulating layer to form the second insulating layer 9.
【００３３】図４（Ｃ）参照
（１９）ＣＭＰ法を適用することに依り、レジスト膜７
及び第２絶縁層９を研磨し、第３遮蔽壁８の頂面を表出
させると共に全面を平坦化する。See FIG. 4C. (19) By applying the CMP method, the resist film 7 is formed.
Then, the second insulating layer 9 is polished to expose the top surface of the third shielding wall 8 and planarize the entire surface.
【００３４】図５（Ａ）参照
（２０）スパッタリング法を適用することに依り、全面
に電解銅めっきを行うためのＣｒ／Ｃｕからなるシード
層を形成する。尚、シード層は図示していない。See FIG. 5A (20) By applying the sputtering method, a seed layer made of Cr / Cu for electrolytic copper plating is formed on the entire surface. The seed layer is not shown.
【００３５】（２１）電解めっき法を適用することに依
り、シード層上に厚さ５〔μｍ〕の銅からなる第２グラ
ンド層１１を形成する。(21) By applying the electrolytic plating method, the second ground layer 11 made of copper and having a thickness of 5 [μm] is formed on the seed layer.
【００３６】（２２）リソグラフィ技術に於けるレジス
ト・プロセス、及び、エッチャントを過硫酸アンモニウ
ム水溶液とするウエット・エッチング法を適用すること
に依り、遮蔽壁の間に在って、且つ、信号線導体５が存
在している領域、即ち、レジスト層７が存在している領
域上の第２グランド層１１を選択的にエッチングして多
数の開口１１Ａを形成する。(22) By applying the resist process in the lithography technique and the wet etching method using an ammonium persulfate aqueous solution as an etchant, the signal line conductor 5 is present between the shield walls. The second ground layer 11 on the region where the resist layer 7 exists, that is, the region where the resist layer 7 exists, is selectively etched to form a large number of openings 11A.
【００３７】図５（Ｂ）参照
（２３）レジスト剥離液中に浸漬し、開口１１Ａからレ
ジスト剥離液を侵入させることに依って、レジスト層
７、即ち、犠牲層を除去することに依って空洞１２を生
成させる。(23) See FIG. 5B. (23) By immersing the resist in the resist stripping solution and letting the resist stripping solution enter through the opening 11 A, the cavity is formed by removing the resist layer 7, that is, the sacrificial layer. 12 is generated.
【００３８】前記のようにして作成されたプリント配線
基板において、信号線導体５は上面及び両側面が空気
（誘電体）で覆われ，且つ、第１グランド層２及び第１
遮蔽壁３と第２遮蔽壁６と第３遮蔽壁８とからなる積層
遮蔽壁及び第２グランド層１１で囲まれた構造、即ち、
同軸構造になっていることが理解されよう。In the printed wiring board manufactured as described above, the signal line conductor 5 has its upper surface and both side surfaces covered with air (dielectric), and the first ground layer 2 and the first ground layer 2
A structure surrounded by a laminated shield wall composed of the shield wall 3, the second shield wall 6, and the third shield wall 8 and the second ground layer 11, that is,
It will be understood that it has a coaxial structure.
【００３９】本発明に於いて用いる金属材料としては、
銅の他に金やアルミニウムなど半導体装置に普通に用い
られている金属は全て用いることができ、また、絶縁材
料としては、エポキシ樹脂、ポリイミド樹脂、ポリベン
ゾオキサゾール樹脂、ベンソシクブテン樹脂など多くの
材料を用いることができる。As the metal material used in the present invention,
In addition to copper, all metals commonly used in semiconductor devices such as gold and aluminum can be used, and as the insulating material, many materials such as epoxy resin, polyimide resin, polybenzoxazole resin, and benzisobutene resin can be used. Can be used.
【００４０】[0040]
【発明の効果】本発明に依るプリント配線基板及びその
製造方法では、基板上に展延する第１グランド層を選択
的に覆う第１絶縁層上に形成された信号線導体、該信号
線導体の両側に間隔をおいて延在し且つ第１グランド層
に導電接続された遮蔽壁、該遮蔽壁に導電接続され且つ
該信号線導体上と間隔をおいて展延すると共に該信号線
導体上では取り扱い周波数の１／４波長以下の長さと間
隔をもつ複数の開口が形成された第２グランド層を備え
たプリント配線基板の実現が基本になっている。According to the printed wiring board and the method of manufacturing the same according to the present invention, the signal line conductor formed on the first insulating layer selectively covering the first ground layer extending on the substrate and the signal line conductor. On both sides of the signal line conductor and conductively connected to the first ground layer, conductively connected to the shield wall and extended on the signal line conductor at a distance, and on the signal line conductor Then, it is basically based on the realization of a printed wiring board provided with a second ground layer in which a plurality of openings having a length and intervals equal to or less than a quarter wavelength of a handling frequency are formed.
【００４１】前記構成を採ることに依り、信号線導体の
周囲に空洞を形成することが可能となり、そして、その
実現を可能にする第２グランド層の開口は１／４波長以
下の長さ及び間隔をもって形成してあるので、信号線導
体のインピーダンス低減、信号線導体間に於ける電磁誘
導に依る干渉防止、外部からの静電誘導ノイズの低減に
充分に機能して高周波特性の劣化を抑制することがで
き、また、その同軸構造は、薄膜多層配線基板を作製す
る為の従来の加工技術を適用することで容易に作製する
ことができるので、既存の技術で容易に対処することが
可能である。By adopting the above-mentioned configuration, it becomes possible to form a cavity around the signal line conductor, and the opening of the second ground layer which enables the realization thereof has a length of 1/4 wavelength or less and Since they are formed with intervals, they function sufficiently to reduce the impedance of the signal line conductors, prevent interference due to electromagnetic induction between the signal line conductors, and reduce electrostatic induction noise from the outside to suppress deterioration of high frequency characteristics. Moreover, since the coaxial structure can be easily manufactured by applying a conventional processing technique for manufacturing a thin film multilayer wiring board, it is possible to easily deal with the existing technique. Is.
【図１】本発明の一実施の形態であるプリント配線基板
を表す要部説明図である。FIG. 1 is an explanatory view of essential parts showing a printed wiring board that is an embodiment of the present invention.
【図２】本発明の一実施の形態であるプリント配線基板
を製造する工程を説明する為の工程要所に於けるプリン
ト配線基板を表す要部切断側面図である。FIG. 2 is a side sectional view showing a principal part of the printed wiring board at a process step for explaining a step of manufacturing the printed wiring board according to the embodiment of the present invention.
【図３】本発明の一実施の形態であるプリント配線基板
を製造する工程を説明する為の工程要所に於けるプリン
ト配線基板を表す要部切断側面図である。FIG. 3 is a side sectional view showing a principal part of the printed wiring board at a process step for explaining a step of manufacturing the printed wiring board according to the embodiment of the present invention.
【図４】本発明の一実施の形態であるプリント配線基板
を製造する工程を説明する為の工程要所に於けるプリン
ト配線基板を表す要部切断側面図である。FIG. 4 is a side sectional view showing a principal part of the printed wiring board at a process step for explaining a step of manufacturing the printed wiring board according to the embodiment of the present invention.
【図５】本発明の一実施の形態であるプリント配線基板
を製造する工程を説明する為の工程要所に於けるプリン
ト配線基板を表す要部切断側面図である。FIG. 5 is a side sectional view showing a principal part of the printed wiring board at a process key point for explaining a step of manufacturing the printed wiring board according to the embodiment of the present invention.
１ 基板 ２ 第１グランド層 ３ 第１遮蔽壁 ４ 第１絶縁層 ５ 信号線導体 ６ 第２遮蔽壁 ８ 第３遮蔽壁 ９ 第２絶縁層 １１ 第２グランド層 １１Ａ 開口 1 substrate 2 First ground layer 3 First shielding wall 4 First insulating layer 5 Signal line conductor 6 Second shielding wall 8 Third shielding wall 9 Second insulating layer 11 Second ground layer 11A opening
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山岸 康男 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 Ｆターム(参考） 5E338 AA03 CC06 EE13 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Yasuo Yamagishi 4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 within Fujitsu Limited F-term (reference) 5E338 AA03 CC06 EE13
Claims (6)
に覆う第１絶縁層上に形成された信号線導体と、 該信号線導体の両側に間隔をおいて延在し且つ第１グラ
ンド層に導電接続された遮蔽壁と、 該遮蔽壁に導電接続され且つ該信号線導体上と間隔をお
いて展延すると共に該信号線導体上では取り扱い周波数
の１／４波長以下の長さと間隔をもつ複数の開口が形成
された第２グランド層とを備えてなることを特徴とする
プリント配線基板。1. A signal line conductor formed on a first insulating layer that selectively covers a first ground layer extending on a substrate, and a signal line conductor extending at intervals on both sides of the signal line conductor. 1 a shield wall that is conductively connected to the ground layer, and a conductor that is conductively connected to the shield wall and that extends at a distance from the signal line conductor and that has a length of 1/4 wavelength or less of the handling frequency on the signal line conductor And a second ground layer having a plurality of openings formed at intervals.
体は全て別個に空洞内に在ると共に第１グランド層と遮
蔽壁と第２グランド層とで囲まれた構造であることを特
徴とする請求項１記載のプリント配線基板。2. A plurality of signal line conductors are formed, and each signal line conductor has a structure in which the signal line conductors are all separately inside the cavity and are surrounded by a first ground layer, a shielding wall and a second ground layer. The printed wiring board according to claim 1, wherein the printed wiring board is a printed wiring board.
の１／４波長以下の長さと間隔を持つ開口は方形をなし
且つ碁盤目状のアレイをなすことを特徴とする請求項１
記載のプリント配線基板。3. An opening formed in the second ground layer and having a length and a spacing equal to or less than ¼ wavelength of a handling frequency has a square shape and forms a grid-shaped array.
The printed wiring board described.
在することを特徴とする請求項１記載のプリント配線基
板。4. The printed wiring board according to claim 1, wherein there is a cavity around each signal line conductor.
を特徴とする請求項１記載のプリント配線基板。5. The printed wiring board according to claim 1, wherein a plurality of signal line conductors are present in the cavity.
第１グランド層に導電接続されて信号線導体形成予定領
域の両側に間隔をおいて延在する第１遮蔽壁を形成する
工程と、 次いで、該第１遮蔽壁間を埋める第１絶縁層を形成する
工程と、 次いで、該第１遮蔽壁に導電接続された第２遮蔽壁を形
成すると共に該第１絶縁層上の該信号線導体形成予定領
域に信号線導体を形成する工程と、 次いで、信号線導体を覆う犠牲層を形成する工程と、 次いで、該第２遮蔽壁に導電接続された第３遮蔽壁を形
成してから全面を平坦化する工程と、 次いで、全面に展延する第２グランド層を形成してから
前記信号線導体に対向する領域に取り扱い周波数の１／
４波長以下の長さと間隔をもつ複数の開口を形成する工
程と、 次いで、該第２グランド層の開口を介して該犠牲層の溶
解除去を行って空洞を形成する工程とが含まれてなるこ
とを特徴とするプリント配線基板の製造方法。6. A first ground layer is formed on a substrate, and then first shield walls are formed that are conductively connected to the first ground layer and extend on both sides of a signal line conductor formation-scheduled region at intervals. A step of forming a first insulating layer that fills the space between the first shielding walls, and a second shielding wall that is conductively connected to the first shielding wall, and on the first insulating layer. A step of forming a signal line conductor in the signal line conductor formation planned region, a step of forming a sacrificial layer covering the signal line conductor, and a step of forming a third shielding wall conductively connected to the second shielding wall And then flattening the entire surface, and then forming a second ground layer extending over the entire surface, and then applying 1 / s of the handling frequency to a region facing the signal line conductor.
The method comprises the steps of forming a plurality of openings having a length and spacing of 4 wavelengths or less, and then performing a dissolution removal of the sacrificial layer through the openings of the second ground layer to form a cavity. A method of manufacturing a printed wiring board, comprising:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002003046A JP2003204129A (en) | 2002-01-10 | 2002-01-10 | Printed wiring board and its manufacturing method |
| US10/338,646 US6943447B2 (en) | 2002-01-10 | 2003-01-09 | Thin film multi-layer wiring substrate having a coaxial wiring structure in at least one layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002003046A JP2003204129A (en) | 2002-01-10 | 2002-01-10 | Printed wiring board and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003204129A true JP2003204129A (en) | 2003-07-18 |
Family
ID=27642739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002003046A Pending JP2003204129A (en) | 2002-01-10 | 2002-01-10 | Printed wiring board and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003204129A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7411598B2 (en) | 2004-09-30 | 2008-08-12 | Seiko Epson Corporation | Line head and image forming apparatus |
| JP2017028164A (en) * | 2015-07-24 | 2017-02-02 | 富士通株式会社 | Wiring board and manufacturing method of wiring board |
| US11439009B2 (en) | 2019-12-11 | 2022-09-06 | Samsung Electronics Co., Ltd. | Printed circuit board and electronic device including the same |
-
2002
- 2002-01-10 JP JP2002003046A patent/JP2003204129A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7411598B2 (en) | 2004-09-30 | 2008-08-12 | Seiko Epson Corporation | Line head and image forming apparatus |
| CN100462854C (en) * | 2004-09-30 | 2009-02-18 | 精工爱普生株式会社 | Line head and image forming apparatus |
| JP2017028164A (en) * | 2015-07-24 | 2017-02-02 | 富士通株式会社 | Wiring board and manufacturing method of wiring board |
| US11439009B2 (en) | 2019-12-11 | 2022-09-06 | Samsung Electronics Co., Ltd. | Printed circuit board and electronic device including the same |
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