JP2003204036A - Electrode plate for composite semiconductor device - Google Patents

Electrode plate for composite semiconductor device

Info

Publication number
JP2003204036A
JP2003204036A JP2002003368A JP2002003368A JP2003204036A JP 2003204036 A JP2003204036 A JP 2003204036A JP 2002003368 A JP2002003368 A JP 2002003368A JP 2002003368 A JP2002003368 A JP 2002003368A JP 2003204036 A JP2003204036 A JP 2003204036A
Authority
JP
Japan
Prior art keywords
electrode plate
boundary groove
upper electrode
sealing material
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002003368A
Other languages
Japanese (ja)
Inventor
Teruhiko Sonoda
輝彦 園田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP2002003368A priority Critical patent/JP2003204036A/en
Publication of JP2003204036A publication Critical patent/JP2003204036A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404Connecting portions
    • H01L2224/40475Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40491Connecting portions connected to auxiliary connecting means on the bonding areas being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode plate for composite semiconductor device in which stress due to heat generated from a pair of semiconductor elements can be relaxed without increasing the quantity of insulation sealing material, and discharge between the element electrodes can be prevented by eliminating residual bubbles in a boundary groove between elements being filled with the insulation sealing material. <P>SOLUTION: An electrode plate 11 is formed in slab form in order to avoid increase in the injection quantity of an insulation sealing material due to presence of a projecting part. A plurality of through holes 11a being bored side by side in the direction along the boundary groove in a region corresponding to a boundary groove being filled with the insulation sealing material have an arcuate shape and the direction between the opposite ends thereof is set to intersect the direction along the boundary groove so that each through hole 11a is imparted with a stress relaxing function and a function for discharging bubbles in the insulation sealing material. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、応力緩和機能及び
気泡排出機能を有する複合半導体デバイス用電極板に関
するものである。
TECHNICAL FIELD The present invention relates to an electrode plate for a composite semiconductor device having a stress relaxation function and a bubble discharging function.

【0002】[0002]

【従来の技術】従来の応力緩和機能を有する電極板が適
用された複合半導体デバイスを図8に示す。図中、81
は、上下面に、相互に導通する電極パターン(図示せ
ず)が形成された1枚の絶縁基板である。この絶縁基板
81上、より詳しくは絶縁基板81上面の電極パターン
(上面電極パターン)上には、後述する絶縁封止材が充
填される境界溝82を挟んで一対の半導体素子83,8
4が接続固定されている。
2. Description of the Related Art FIG. 8 shows a conventional composite semiconductor device to which an electrode plate having a stress relaxation function is applied. 81 in the figure
Is a single insulating substrate having electrode patterns (not shown) formed on the upper and lower surfaces thereof. On the insulating substrate 81, more specifically, on the electrode pattern (upper surface electrode pattern) on the upper surface of the insulating substrate 81, a pair of semiconductor elements 83, 8 is sandwiched with a boundary groove 82 filled with an insulating sealing material described later.
4 is connected and fixed.

【0003】一対の半導体素子83,84は複合半導体
デバイスの要部を構成するものであり、この一対の半導
体素子83,84上には、共通の上部電極板85が接続
固定され、両半導体素子83,84相互間を電気的に接
続している。ここでは、半導体素子83はIGBT、半
導体素子84はフリーホイールダイオードで、印加電圧
が650V程度の高電圧素子である。
A pair of semiconductor elements 83, 84 constitutes an essential part of a composite semiconductor device, and a common upper electrode plate 85 is connected and fixed on the pair of semiconductor elements 83, 84, so that both semiconductor elements are connected. 83 and 84 are electrically connected to each other. Here, the semiconductor element 83 is an IGBT, the semiconductor element 84 is a freewheel diode, and is a high voltage element with an applied voltage of about 650V.

【0004】上記絶縁基板81は、熱伝導性及び導電性
を有する放熱板86上に位置決め固定されている。この
絶縁基板81の上面電極パターンと半導体素子83,8
4の間、半導体素子83,84と上部電極板85の間の
接続固定は半田87によりなされている。
The insulating substrate 81 is positioned and fixed on a heat dissipation plate 86 having thermal conductivity and conductivity. The upper surface electrode pattern of the insulating substrate 81 and the semiconductor elements 83, 8
4, the semiconductor elements 83, 84 and the upper electrode plate 85 are fixedly connected by the solder 87.

【0005】絶縁基板81下面の電極パターン(下面電
極パターン)と放熱板86の間の固定も半田87により
なされ、したがって、絶縁基板81と放熱板86とは電
気的かつ機械的に接続固定される。また、上述したよう
に絶縁基板81の上下面電極パターン(図示せず)は相
互に導通しているので、一対の半導体素子83,84の
下面(電極)と放熱板86とは導通状態となり、放熱板
86は複合半導体デバイスの下部電極板として機能し得
る。
Fixing between the electrode pattern (lower surface electrode pattern) on the lower surface of the insulating substrate 81 and the heat radiating plate 86 is also performed by the solder 87. Therefore, the insulating substrate 81 and the heat radiating plate 86 are electrically and mechanically connected and fixed. . Moreover, since the upper and lower electrode patterns (not shown) of the insulating substrate 81 are electrically connected to each other as described above, the lower surfaces (electrodes) of the pair of semiconductor elements 83 and 84 and the heat dissipation plate 86 are electrically connected to each other. The heat sink 86 can function as a lower electrode plate of the composite semiconductor device.

【0006】以上の上部電極板85、半導体素子83,
84、絶縁基板81及び放熱板86からなる組立体は、
パッケージ内部88(図中、一点鎖線はパッケージ側壁
を示す。)に収納され、そのパッケージ内部88にはシ
リコーン等の絶縁封止材89が注入される。
The upper electrode plate 85, the semiconductor element 83,
The assembly consisting of 84, the insulating substrate 81 and the heat dissipation plate 86 is
The package is housed in a package interior 88 (indicated by a one-dot chain line indicates a package side wall), and an insulating sealant 89 such as silicone is injected into the package interior 88.

【0007】絶縁封止材89がパッケージ内部88に満
たされると、その絶縁封止材89が、境界溝82の両端
開口部分(境界溝82の図示面に垂直な方向の両端部
分)から境界溝82内に回り込み流入し、境界溝82内
に満たされる。
When the package 89 is filled with the insulating encapsulant 89, the insulating encapsulant 89 is filled with the insulating encapsulant 89 from the opening portions at both ends of the boundary groove 82 (both end portions in the direction perpendicular to the illustrated surface of the boundary groove 82). It flows around into the groove 82 and fills the boundary groove 82.

【0008】ここで、上記上部電極板85は、応力緩和
機能を有して形成されている。すなわち、図8中の半導
体素子83,84が実際に動作すると、その半導体素子
83,84は多量の熱を発生する。発生熱の多くは放熱
板86側に伝わって空中に放出されるが、上部電極板8
5側に伝わった熱は上部電極板85部分に蓄積されやす
く、上部電極板85には図中矢印イ,ロに示す方向に応
力が働く。
Here, the upper electrode plate 85 is formed to have a stress relaxation function. That is, when the semiconductor elements 83 and 84 in FIG. 8 actually operate, the semiconductor elements 83 and 84 generate a large amount of heat. Most of the generated heat is transmitted to the heat radiating plate 86 side and radiated into the air, but the upper electrode plate 8
The heat transmitted to the No. 5 side is easily accumulated in the upper electrode plate 85 portion, and stress acts on the upper electrode plate 85 in the directions indicated by arrows a and b in the figure.

【0009】そこで、従来の上部電極板85では、図示
するように、発熱源である一対の半導体素子83,84
の相互間部分の対応箇所、つまり境界溝82に対応する
領域に、境界溝82側とは反対側(図中上方)に突出す
る下向きコ字状の屈曲部85aを形成した。この屈曲部
85aによれば、応力発生時に下方の開口部分が閉じる
方向に撓み、応力、特に矢印ロ方向の応力を緩和し、ひ
いては矢印イ方向の応力も緩和する。
Therefore, in the conventional upper electrode plate 85, as shown in the figure, a pair of semiconductor elements 83, 84 which are heat sources.
A downward U-shaped bent portion 85a projecting to the side opposite to the boundary groove 82 side (upper side in the drawing) is formed in the corresponding portion of the mutual groove portion, that is, in the region corresponding to the boundary groove 82. According to the bent portion 85a, when a stress is generated, the lower opening portion is bent in a closing direction to relax stress, particularly stress in the arrow B direction, and in turn, stress in the arrow A direction.

【0010】[0010]

【発明が解決しようとする課題】しかしながら上記従来
の上部電極板85では、境界溝82の内壁部分におい
て、上部電極板85と絶縁基板81の上面電極パターン
の間で放電(図中、上向き矢印参照)が発生し、半導体
素子83,84の上下面電極間が短絡(半導体素子8
3,84の非接地電極が地絡)するという問題があっ
た。
However, in the above-mentioned conventional upper electrode plate 85, discharge occurs between the upper electrode plate 85 and the upper surface electrode pattern of the insulating substrate 81 at the inner wall portion of the boundary groove 82 (see the upward arrow in the figure). ) Occurs, and a short circuit occurs between the upper and lower electrodes of the semiconductor elements 83 and 84 (semiconductor element 8
There was a problem that the non-grounded electrodes 3, 84 were grounded.

【0011】すなわち図8に示す上部電極板85では、
その屈曲部85aの開口端縁部分の下方側に、トンネル
状の空洞90が形成されることが少なくない。これは、
絶縁封止材89のパッケージ内部88への注入時に、境
界溝82内に絶縁封止材89が充分満たされず、気泡が
境界溝82内に残ってしまうことが最大の原因であると
考えられる。いずれにしても、トンネル状の空洞90が
形成されると、その部分で絶縁耐力が低下して放電が生
じやすくなり、上述したような問題が生じた。
That is, in the upper electrode plate 85 shown in FIG.
A tunnel-shaped cavity 90 is often formed below the opening edge of the bent portion 85a. this is,
It is considered that the largest cause is that when the insulating sealing material 89 is injected into the package interior 88, the insulating sealing material 89 is not sufficiently filled in the boundary groove 82 and bubbles remain in the boundary groove 82. In any case, when the tunnel-shaped cavity 90 is formed, the dielectric strength is reduced at that portion, and discharge easily occurs, causing the above-described problem.

【0012】また図8に示す上部電極板85では、図中
上方に突出する屈曲部85aを形成したので、全体を平
板状に形成した場合に比べて絶縁封止材89を多く必要
とするという問題もあった。これを図9を用いて説明す
ると、上部電極板85に絶縁を施す場合には、そのうち
パッケージ外部側に最も突出する部分を基準に絶縁層の
厚さが設定される。このため、突出する部分が上部電極
板85面の一部であっても、その部分に必要な絶縁層厚
さt1が得られる深さd1まで絶縁封止材89を注入し
なければならず、パッケージ内部88への絶縁封止材注
入量が多くなるという問題もあった。
Further, in the upper electrode plate 85 shown in FIG. 8, since the bent portion 85a protruding upward in the drawing is formed, more insulating sealing material 89 is required as compared with the case where the whole is formed in a flat plate shape. There was also a problem. This will be described with reference to FIG. 9. When insulating the upper electrode plate 85, the thickness of the insulating layer is set on the basis of the portion most protruding to the outside of the package. Therefore, even if the protruding portion is a part of the surface of the upper electrode plate 85, the insulating sealing material 89 must be injected to the depth d1 at which the required insulating layer thickness t1 is obtained. There is also a problem that the amount of insulating sealing material injected into the package interior 88 increases.

【0013】図8に示す上部電極板85における、境界
溝82内への気泡の残存問題に対処するためには、従来
から、境界溝82に対応する領域の該境界溝82に沿う
方向に、図10に示すように、複数個の円形貫通孔91
aを穿設した上部電極板91がある。これによれば、図
8において、パッケージ内部88への絶縁封止材89の
注入時あるいは注入後に、境界溝82内の空気、気泡は
図10に示す複数個の円形貫通孔91aから外部へ排出
される。したがって、上記トンネル状の空洞90が境界
溝82内に形成されることが防止され、上述した問題は
解消される。
In order to deal with the problem of bubbles remaining in the boundary groove 82 in the upper electrode plate 85 shown in FIG. 8, conventionally, in a direction along the boundary groove 82 in a region corresponding to the boundary groove 82, As shown in FIG. 10, a plurality of circular through holes 91
There is an upper electrode plate 91 having a formed therein. According to this, in FIG. 8, the air and bubbles in the boundary groove 82 are discharged to the outside from the plurality of circular through holes 91a shown in FIG. 10 when or after the insulating sealing material 89 is injected into the package inside 88. To be done. Therefore, the tunnel-shaped cavity 90 is prevented from being formed in the boundary groove 82, and the above-mentioned problem is solved.

【0014】しかし、図10に示す上部電極板91は、
応力緩和機能を積極的にもつものではない。したがっ
て、図中矢印イ,ロに示す方向に働く応力が緩和され
ず、同矢印イ,ロの先端部分、特に矢印イの先端部分に
おいて応力集中が起こり、上部電極板91に剥がれ等を
生じさせる虞があった。これは、図11に示すように、
応力発生時、円形貫通孔91a部分には図中左右方向か
ら各々矢印ハ,ニに示すように応力が働くが、各円形貫
通孔91aが、それら左右からの応力を適宜の方向に逃
がすように作用しないからであり、したがって、図10
中の矢印イの先端部分において応力集中が起こった。
However, the upper electrode plate 91 shown in FIG.
It does not have a positive stress relaxation function. Therefore, the stress acting in the directions indicated by arrows a and b in the figure is not relaxed, and stress concentration occurs at the tip portions of the arrows a and b, particularly at the tip portion of the arrow a, causing peeling or the like on the upper electrode plate 91. I was afraid. This is as shown in FIG.
When a stress is generated, stress acts on the circular through holes 91a from the left and right directions in the drawing as indicated by arrows c and d, respectively. However, each circular through hole 91a is designed to allow the stress from the left and right to escape in an appropriate direction. It does not work, and therefore FIG.
Stress concentration occurred at the tip of arrow a in the figure.

【0015】本発明は、上記のような実情に鑑みなされ
たもので、デバイスのパッケージ内部への絶縁封止材の
量を増加させることなく、半導体素子からの発生熱によ
って生ずる応力を積極的に緩和し得、しかも、絶縁封止
材が充填される境界溝内への気泡の残存をなくして半導
体素子の電極相互間での放電を防止することが可能な複
合半導体デバイス用電極板を提供することを目的とす
る。
The present invention has been made in view of the above situation, and positively reduces stress generated by heat generated from a semiconductor element without increasing the amount of insulating sealing material inside the package of the device. (EN) Provided is an electrode plate for a composite semiconductor device, which can be relaxed and which can prevent discharge between electrodes of a semiconductor element by preventing bubbles from remaining in a boundary groove filled with an insulating sealing material. The purpose is to

【0016】[0016]

【課題を解決するための手段】上記目的を達成するため
に、請求項1に記載の複合半導体デバイス用電極板は、
共通の基板上に絶縁封止材が充填される境界溝を挟んで
配置固定された、複合半導体デバイスの要部を構成する
対の半導体素子の前記基板とは反対側の面に接続固定さ
れ、それら半導体素子相互間を電気的に接続する共通の
平板状の電極板であって、その板面の前記境界溝に対応
する領域の該境界溝に沿う方向に、各々両端間方向を境
界溝に沿う方向と交差する方向に向けられたほぼ弧状な
いしU字状の貫通孔が複数個並べて形成されたことを特
徴とする。
In order to achieve the above object, the electrode plate for a composite semiconductor device according to claim 1 is
Placed and fixed on both sides of a boundary groove filled with an insulating encapsulant on a common substrate, connected and fixed to a surface opposite to the substrate of a pair of semiconductor elements forming a main part of the composite semiconductor device, A common flat electrode plate for electrically connecting the semiconductor elements to each other, in a direction along the boundary groove in a region corresponding to the boundary groove of the plate surface, and a direction between both ends is defined as a boundary groove. It is characterized in that a plurality of substantially arcuate or U-shaped through-holes oriented in a direction intersecting with the along direction are formed side by side.

【0017】請求項2に記載の発明は、請求項1に記載
の複合半導体デバイス用電極板において、貫通孔のほぼ
弧状ないしU字状の凹又は凸の向きが、境界溝に沿う方
向のほぼ中央位置を挟んで相互に逆向きに形成されたこ
とを特徴とする。
According to a second aspect of the present invention, in the electrode plate for a composite semiconductor device according to the first aspect, the direction of the arcuate or U-shaped concave or convex of the through hole is substantially in the direction along the boundary groove. It is characterized in that they are formed in opposite directions with the central position sandwiched therebetween.

【0018】請求項3に記載の発明は、請求項1又は2
に記載の複合半導体デバイス用電極板において、境界溝
に沿う方向に並んだ貫通孔のうちの端に位置する貫通孔
に対応する端部分の板面形状が、前記端に位置する貫通
孔の凹又は凸の向きと同方向に凹又は凸状に形成された
ことを特徴とする。
The invention described in claim 3 is the invention according to claim 1 or 2.
In the composite semiconductor device electrode plate according to, the plate surface shape of the end portion corresponding to the through hole located at the end of the through holes arranged in the direction along the boundary groove is a recess of the through hole located at the end. Alternatively, it is characterized in that it is formed in a concave or convex shape in the same direction as the convex direction.

【0019】[0019]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づき説明する。図1は本発明の電極板が適用された
複合半導体デバイスの一例を示す断面図である。図中、
11が本発明の電極板(ここでは上部電極板という。)
を示すが、この上部電極板11を除いた各部の構成は、
図8と特に変わるところはない。したがって、図1にお
いて、図8と同一又は相当部分には同一符号を付してそ
の説明を省略し、主に上部電極板11について説明す
る。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an example of a composite semiconductor device to which the electrode plate of the present invention is applied. In the figure,
11 is the electrode plate of the present invention (herein referred to as the upper electrode plate).
The configuration of each part except the upper electrode plate 11 is
There is no particular difference from FIG. Therefore, in FIG. 1, the same or corresponding portions as those in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted, and the upper electrode plate 11 will be mainly described.

【0020】図2(a)、(b)及び(c)は、図1中
の上部電極板11を取り出して示す平面図、右側面図及
び図2(a)中のc−c線断面矢視図である。図2
(a)から分かるように、上部電極板11には、ほぼ弧
状ないしU字状(以下単に弧状と記す。)の貫通孔11
aが複数個形成されている。この場合、複数個の貫通孔
11aは、上部電極板11の板面の、図1に示す境界溝
82に対応する領域の該境界溝82に沿う方向(図2
(a)中、上下方向)に、各々両端間方向を境界溝82
に沿う方向と交差する方向(同、左右方向)に向けて並
べられている。
2 (a), 2 (b) and 2 (c) are a plan view showing the upper electrode plate 11 in FIG. 1 taken out, a right side view and a cross-section line cc line in FIG. 2 (a). It is a perspective view. Figure 2
As can be seen from (a), the upper electrode plate 11 has a substantially arc-shaped or U-shaped (hereinafter simply referred to as “arc-shaped”) through hole 11.
A plurality of a are formed. In this case, the plurality of through-holes 11a are formed on the plate surface of the upper electrode plate 11 in a direction along the boundary groove 82 in a region corresponding to the boundary groove 82 shown in FIG.
(A) Middle and up and down direction)
Are arranged in the direction intersecting with the direction (the same, left and right direction).

【0021】弧状の貫通孔11aは、抜き加工のみによ
って形成してもよいし、その他の方法によって形成して
もよい。例えば、最初に、上部電極板材上の、弧状の貫
通孔11aの形成予定位置に、各々短冊状の貫通孔を横
向きに抜き加工しておく。次に、その短冊状の貫通孔内
に各々棒状の工具を差し込み、その工具又は上部電極板
材を短冊状の貫通孔の配列方向に僅かに押圧移動させて
弧状の貫通孔11aを得るようにしてもよい。
The arc-shaped through hole 11a may be formed only by punching, or may be formed by another method. For example, first, strip-shaped through holes are laterally punched at the positions where the arc-shaped through holes 11a are to be formed on the upper electrode plate material. Next, a rod-shaped tool is inserted into each of the strip-shaped through holes, and the tool or the upper electrode plate material is slightly pressed and moved in the arrangement direction of the strip-shaped through-holes to obtain the arc-shaped through-holes 11a. Good.

【0022】図1、図2に示すように、貫通孔11a
を、上部電極板11板面の境界溝82に対応する領域の
境界溝82に沿う方向に複数個並べて形成したことによ
れば、図10に示す従来の上部電極板91と同様の効果
が得られる。
As shown in FIGS. 1 and 2, the through hole 11a
By arranging a plurality of them in a direction along the boundary groove 82 in a region corresponding to the boundary groove 82 on the plate surface of the upper electrode plate 11, the same effect as that of the conventional upper electrode plate 91 shown in FIG. 10 can be obtained. To be

【0023】すなわち、図3に示すように、絶縁封止材
89のパッケージ内部88への注入時に、境界溝82内
に絶縁封止材89が充分満たされず、気泡31が境界溝
82内に残ることがあっても、その気泡31は矢印ホに
示すように浮上して貫通孔11aから外部へ排出され
る。これにより、トンネル状の空洞90(図8参照)が
境界溝82内に形成されることがなくなり、その部分で
絶縁耐力が低下して放電が生じやすくなるということも
なくなる。したがって、上部電極板11と絶縁基板81
の上面電極パターン(図示せず)の間で放電が発生し、
半導体素子83,84の上下面電極間が短絡(半導体素
子83,84の非接地電極が地絡)するという問題は解
消される。
That is, as shown in FIG. 3, when the insulating sealing material 89 is injected into the package inside 88, the insulating sealing material 89 is not sufficiently filled in the boundary groove 82, and the bubbles 31 remain in the boundary groove 82. In that case, the bubble 31 floats as shown by the arrow E and is discharged from the through hole 11a to the outside. As a result, the tunnel-shaped cavity 90 (see FIG. 8) is not formed in the boundary groove 82, and the dielectric strength at that portion is not lowered, so that discharge is not likely to occur. Therefore, the upper electrode plate 11 and the insulating substrate 81
Discharge occurs between the upper electrode patterns (not shown) of
The problem that the upper and lower electrodes of the semiconductor elements 83 and 84 are short-circuited (the non-grounded electrodes of the semiconductor elements 83 and 84 are grounded) is solved.

【0024】また、上部電極板11の貫通孔11aの形
状は、図2(a)に示すように各々弧状に形成され、積
極的な応力緩和機能を有するようになされている。すな
わち、図1に示すように構成された複合半導体デバイス
の半導体素子83,84が実際に動作すると、同半導体
素子83,84は多量の熱を発生して高温になる。発生
熱の多くは放熱板86側に伝わり、放熱板86表面から
空中に放出されるが、上部電極板11側に伝わった熱は
上部電極板11部分に蓄積されやすく、上部電極板11
には図中矢印イ,ロに示す方向に応力が働く。図4はこ
の様子を上部電極板11の平面図を用いて示している。
The shape of the through hole 11a of the upper electrode plate 11 is formed in an arc shape as shown in FIG. 2A so as to have a positive stress relaxation function. That is, when the semiconductor elements 83 and 84 of the composite semiconductor device configured as shown in FIG. 1 actually operate, the semiconductor elements 83 and 84 generate a large amount of heat and reach a high temperature. Most of the generated heat is transmitted to the heat radiating plate 86 side and is radiated into the air from the surface of the heat radiating plate 86. However, the heat transmitted to the upper electrode plate 11 side is likely to be accumulated in the upper electrode plate 11 portion, and the upper electrode plate 11
In the figure, stress acts in the directions indicated by arrows a and b in the figure. FIG. 4 shows this state using a plan view of the upper electrode plate 11.

【0025】本発明の上部電極板11では、上述した位
置と並び方向にて複数個形成した貫通孔11aの形状
が、図2(a)、図4に示すように各々弧状に形成され
ている。このような弧状の貫通孔11aによれば、応力
発生時、その貫通孔11a部分に働く図4中の矢印ロ方
向の応力が一方向に逃がされて緩和され、ひいては矢印
イ方向の応力も緩和される。
In the upper electrode plate 11 of the present invention, a plurality of through-holes 11a formed in the above-mentioned position and arrangement direction are formed in an arc shape as shown in FIGS. . With such an arc-shaped through hole 11a, when a stress is generated, the stress acting on the through hole 11a portion in the arrow B direction in FIG. 4 is released in one direction to be relaxed, and the stress in the arrow A direction is also reduced. Will be alleviated.

【0026】これを、図4中の一点鎖線で囲んだ部分α
を拡大して示す図5を併用して述べると、応力発生時、
弧状の貫通孔11a部分には、上述したように図4中の
矢印ロ方向の応力が働く。このとき、弧状の貫通孔11
aが、点線で示す元の形状から実線で示す形状に撓み、
その部分で図4中の矢印ロ方向の応力を端部分11c方
向に逃がす(図中、矢印ヘ参照)。すなわち、貫通孔1
1a部分に働く図4中の矢印ロ方向の応力が、弧状の貫
通孔11aの変形作用によって積極的に緩和され、ひい
ては矢印イ方向の応力も緩和され、上部電極板11に剥
がれ等を生じさせることを防ぐ。
A portion α surrounded by the one-dot chain line in FIG.
FIG. 5 which is an enlarged view of FIG.
As described above, the stress in the arrow B direction in FIG. 4 acts on the arc-shaped through hole 11a. At this time, the arc-shaped through hole 11
a bends from the original shape shown by the dotted line to the shape shown by the solid line,
At that portion, stress in the direction of arrow B in FIG. 4 is released in the direction of the end portion 11c (see arrow F in the figure). That is, the through hole 1
The stress acting on the portion 1a in the direction of arrow B in FIG. 4 is positively relaxed by the deforming action of the arc-shaped through hole 11a, and in turn the stress in the direction of arrow a is also relaxed, causing the upper electrode plate 11 to peel off or the like. Prevent that.

【0027】本実施形態では、図2(a)に示すよう
に、上部電極板11は一方向に並んだ貫通孔11a…の
うちの端に位置する貫通孔11a,11aに対応する端
部分11b,11cの板面形状が、上記端に位置する弧
状の貫通孔11a,11aの凹又は凸の向きと同方向に
凹又は凸状に形成されている。これによれば、弧状の貫
通孔11a部分に働く応力が、図5中の矢印ヘに示すよ
うに端部分11c方向に逃がされようとしたときに、そ
れを上部電極板11の端縁部分に負担をかけることなく
吸収し得、その端縁部分の損傷を極力抑止できる。
In this embodiment, as shown in FIG. 2A, the upper electrode plate 11 has end portions 11b corresponding to the through holes 11a, 11a located at the ends of the through holes 11a arranged in one direction. , 11c are formed in a concave or convex shape in the same direction as the concave or convex direction of the arc-shaped through holes 11a, 11a located at the end. According to this, when the stress acting on the arc-shaped through hole 11a is about to escape in the direction of the end portion 11c as shown by the arrow in FIG. 5, the stress acts on the edge portion of the upper electrode plate 11. Can be absorbed without imposing a burden on the outer edge, and damage to the edge portion can be suppressed as much as possible.

【0028】上部電極板11の一方向に並んだ貫通孔1
1a…のうちの端に位置する貫通孔11a,11aに対
応する端部分11b,11cの板面形状を凹又は凸状に
形成するか否かに拘わらず、上部電極板11は平板状に
形成されている。したがって、図8に示す従来の上部電
極板85における絶縁封止材89を多く必要とするとい
う問題は解消される。
Through-holes 1 arranged in one direction on the upper electrode plate 11.
The upper electrode plate 11 is formed in a flat plate shape regardless of whether the plate surface shape of the end portions 11b, 11c corresponding to the through holes 11a, 11a located at the end of 1a ... Is formed to be concave or convex. Has been done. Therefore, the problem of requiring a large amount of insulating sealing material 89 in the conventional upper electrode plate 85 shown in FIG. 8 is solved.

【0029】これを図6を用いて説明すると、上部電極
板11に絶縁を施す場合には、そのうちパッケージ外部
側に最も突出する部分を基準に絶縁層の厚さが設定され
る。このため、図8に示す従来の上部電極板85のよう
に板面に突出する部分があると、図9に示したように、
その部分に必要な絶縁層厚さt1が得られる深さd1
(t1<d1)まで絶縁封止材89を注入しなければな
い。しかし、本発明の上部電極板11は平板状であるの
で、図6に示すように、必要な絶縁層厚さt1と、その
厚さを得るための絶縁封止材89の注入深さd1とが等
しく(t1=d1)、したがって、絶縁封止材89を多
く必要とすることはない。
This will be described with reference to FIG. 6. When the upper electrode plate 11 is insulated, the thickness of the insulating layer is set with reference to the most projecting portion on the outside of the package. Therefore, if there is a portion projecting on the plate surface like the conventional upper electrode plate 85 shown in FIG. 8, as shown in FIG.
Depth d1 at which the required insulating layer thickness t1 is obtained
The insulating sealing material 89 must be injected until (t1 <d1). However, since the upper electrode plate 11 of the present invention has a flat plate shape, as shown in FIG. 6, the required insulating layer thickness t1 and the injection depth d1 of the insulating sealing material 89 for obtaining the thickness t1 are set. Are equal to each other (t1 = d1), and therefore a large amount of insulating encapsulant 89 is not required.

【0030】なお上述実施形態では、上部電極板11に
形成される貫通孔11aの弧状(U字状)の凹又は凸の
向きを一方向に揃えたが、これのみに限定されることは
ない。例えば、図7に示すように、上記凹又は凸の向き
を、上部電極板11面上の境界溝に沿う方向(図7中、
上下方向)のほぼ中央位置を挟んで相互に逆向きに形成
してもよい。これによれば、応力は相反する方向に等分
に逃がされることになり、応力緩和を一方向に偏らせる
ことなく実現できるという利点がある。なおこの例の場
合、中央に位置する貫通孔11dは、図示するように、
端部分11c(図2参照)形状を一対向かい合わせに結
合した形状に形成することが望ましい。なお、上掲図に
おいて、同一符号は同一又は相当部分を示す。
In the above embodiment, the arcuate (U-shaped) concave or convex direction of the through hole 11a formed in the upper electrode plate 11 is aligned in one direction, but the invention is not limited to this. . For example, as shown in FIG. 7, the direction of the concave or convex may be the direction along the boundary groove on the surface of the upper electrode plate 11 (in FIG. 7,
They may be formed in mutually opposite directions with a substantially central position (up and down direction) interposed therebetween. According to this, the stress is evenly released in opposite directions, and there is an advantage that the stress relaxation can be realized without being biased in one direction. In the case of this example, the through hole 11d located at the center is, as shown in the figure,
It is desirable to form the end portion 11c (see FIG. 2) into a shape in which a pair of end portions 11c are joined face-to-face. In the above figures, the same symbols indicate the same or corresponding parts.

【0031】[0031]

【発明の効果】以上述べたように請求項1の発明では、
複合半導体デバイス用電極板を平板状の電極板で構成し
た。そして、その板面の絶縁封止材が充填される境界溝
に対応する領域の該境界溝に沿う方向に、各々両端間方
向を境界溝に沿う方向と交差する方向に向けたほぼ弧状
ないしU字状の貫通孔を複数個並べて形成し、応力緩和
機能と絶縁封止材中の気泡排出機能を両立させた。この
ような構成によれば、電極板上部における絶縁層厚さの
低減が図れ、デバイスのパッケージ内部への絶縁封止材
量を増加させることなく、半導体素子からの発生熱によ
って生ずる応力を積極的に緩和し得る。加えて、絶縁封
止材が充填される境界溝内への気泡の残存をなくし、半
導体素子の電極相互間での放電を防止することができ
る。
As described above, according to the invention of claim 1,
The electrode plate for a composite semiconductor device was composed of a flat electrode plate. Then, in a direction along the boundary groove in a region corresponding to the boundary groove filled with the insulating sealing material on the plate surface, a substantially arcuate shape or a U direction in which a direction between both ends is oriented in a direction intersecting a direction along the boundary groove. A plurality of V-shaped through-holes were formed side by side to achieve both a stress relaxation function and a bubble discharging function in the insulating sealing material. With such a structure, the thickness of the insulating layer on the upper part of the electrode plate can be reduced, and the stress generated by the heat generated from the semiconductor element can be positively increased without increasing the amount of the insulating sealing material inside the device package. Can be relaxed. In addition, it is possible to prevent bubbles from remaining in the boundary groove filled with the insulating sealing material and prevent discharge between the electrodes of the semiconductor element.

【0032】請求項2に記載の発明によれば、貫通孔の
ほぼ弧状ないしU字状の凹又は凸の向きを、境界溝に沿
う方向のほぼ中央位置を挟んで相互に逆向きに形成した
ので、応力緩和を一方向に偏らせることなく実現でき
る。
According to the second aspect of the invention, the direction of the arcuate or U-shaped concave or convex of the through hole is formed to be opposite to each other with the substantially central position along the boundary groove interposed. Therefore, the stress relaxation can be realized without being biased in one direction.

【0033】請求項3に記載の発明によれば、端に位置
する貫通孔に対応する電極板の端部分の板面形状を、貫
通孔の向きと同方向に向けて形成したので、応力緩和
時、貫通孔部分に働く応力が上記端部分側に逃がされる
ときに、それをその端縁部分に負担をかけることなく吸
収し得る。
According to the third aspect of the invention, since the plate surface shape of the end portion of the electrode plate corresponding to the through hole located at the end is formed in the same direction as the direction of the through hole, stress relaxation is achieved. At this time, when the stress acting on the through hole portion is released to the end portion side, it can be absorbed without putting a load on the end edge portion.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電極板が適用された複合半導体デバイ
スの一例を示す断面図である。
FIG. 1 is a sectional view showing an example of a composite semiconductor device to which an electrode plate of the present invention is applied.

【図2】図1中の上部電極板を取り出して示す図であ
る。
FIG. 2 is a diagram showing an upper electrode plate taken out in FIG.

【図3】同上部電極板における気泡排出機能の説明図で
ある。
FIG. 3 is an explanatory diagram of a bubble discharging function in the upper electrode plate.

【図4】同上部電極板に応力が働く様子を示す図であ
る。
FIG. 4 is a diagram showing how stress acts on the upper electrode plate.

【図5】同上部電極板における応力緩和機能を説明する
ための図4中のα部分の拡大図である。
FIG. 5 is an enlarged view of an α part in FIG. 4 for explaining a stress relaxation function in the upper electrode plate.

【図6】同上部電極板が適用された複合半導体デバイス
における絶縁封止材の必要量の説明図である。
FIG. 6 is an explanatory diagram of a required amount of an insulating sealing material in a composite semiconductor device to which the upper electrode plate is applied.

【図7】同上部電極板への弧状の貫通孔の他の形成例の
説明図である。
FIG. 7 is an explanatory diagram of another example of forming an arc-shaped through hole in the upper electrode plate.

【図8】従来の電極板が適用された複合半導体デバイス
の断面図である。
FIG. 8 is a cross-sectional view of a composite semiconductor device to which a conventional electrode plate is applied.

【図9】同上部電極板が適用された複合半導体デバイス
における絶縁封止材の必要量の説明図である。
FIG. 9 is an explanatory diagram of a required amount of an insulating encapsulant in a composite semiconductor device to which the upper electrode plate is applied.

【図10】同上部電極板に応力が働く様子を示す図であ
る。
FIG. 10 is a diagram showing how stress acts on the upper electrode plate.

【図11】同上部電極板の応力緩和機能を説明するため
の部分拡大図である。
FIG. 11 is a partial enlarged view for explaining the stress relaxation function of the upper electrode plate.

【符号の説明】[Explanation of symbols]

11 上部電極板(電極板) 11a 弧状の貫通孔(弧状ないしU字状の貫通孔) 11b,11c 上部電極板の端部分 81 絶縁基板(基板) 82 境界溝 83,84 半導体素子 89 絶縁封止材 11 Upper electrode plate (electrode plate) 11a Arc-shaped through hole (arc-shaped or U-shaped through hole) 11b, 11c Edge part of upper electrode plate 81 Insulating substrate (substrate) 82 boundary groove 83,84 Semiconductor element 89 Insulation sealing material

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 共通の基板上に絶縁封止材が充填される
境界溝を挟んで配置固定された、複合半導体デバイスの
要部を構成する対の半導体素子の前記基板とは反対側の
面に接続固定され、それら半導体素子相互間を電気的に
接続する共通の平板状の電極板であって、その板面の前
記境界溝に対応する領域の該境界溝に沿う方向に、各々
両端間方向を境界溝に沿う方向と交差する方向に向けら
れたほぼ弧状ないしU字状の貫通孔が複数個並べて形成
されたことを特徴とする複合半導体デバイス用電極板。
1. A surface of a pair of semiconductor elements opposite to the substrate, which is arranged and fixed on a common substrate with a boundary groove filled with an insulating encapsulating material sandwiched therebetween, and which constitutes a main part of a composite semiconductor device. A common plate-shaped electrode plate that is fixedly connected to and electrically connects the semiconductor elements to each other, in a direction along the boundary groove in a region corresponding to the boundary groove on the plate surface, between both ends. An electrode plate for a composite semiconductor device, wherein a plurality of substantially arcuate or U-shaped through holes oriented in a direction intersecting a direction along a boundary groove are formed side by side.
【請求項2】 貫通孔のほぼ弧状ないしU字状の凹又は
凸の向きが、境界溝に沿う方向のほぼ中央位置を挟んで
相互に逆向きに形成されたことを特徴とする請求項1に
記載の複合半導体デバイス用電極板。
2. A substantially arcuate or U-shaped concave or convex direction of the through hole is formed in opposite directions with a substantially central position in a direction along the boundary groove being sandwiched therebetween. 7. The electrode plate for a composite semiconductor device according to.
【請求項3】 境界溝に沿う方向に並んだ貫通孔のうち
の端に位置する貫通孔に対応する端部分の板面形状が、
前記端に位置する貫通孔の凹又は凸の向きと同方向に凹
又は凸状に形成されたことを特徴とする請求項1又は2
に記載の複合半導体デバイス用電極板。
3. The plate surface shape of the end portion corresponding to the through hole located at the end of the through holes arranged in the direction along the boundary groove,
3. The concave or convex shape is formed in the same direction as the concave or convex direction of the through hole located at the end.
7. The electrode plate for a composite semiconductor device according to.
JP2002003368A 2002-01-10 2002-01-10 Electrode plate for composite semiconductor device Pending JP2003204036A (en)

Priority Applications (1)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186890A (en) * 2007-01-29 2008-08-14 Denso Corp Semiconductor device
US10978366B2 (en) 2017-05-11 2021-04-13 Mitsubishi Electric Corporation Power module having a hole in a lead frame for improved adhesion with a sealing resin, electric power conversion device, and method for producing power module
DE102018214904B4 (en) 2017-10-25 2024-03-28 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186890A (en) * 2007-01-29 2008-08-14 Denso Corp Semiconductor device
US10978366B2 (en) 2017-05-11 2021-04-13 Mitsubishi Electric Corporation Power module having a hole in a lead frame for improved adhesion with a sealing resin, electric power conversion device, and method for producing power module
DE102018214904B4 (en) 2017-10-25 2024-03-28 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing a semiconductor device

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