JP2003203969A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in the case of isolation of semiconductor elements, such as deterioration of characteristics due to deterioration in crystallinity, increase of leakage current due to contact of an active layer with electrode metal, and step cut of the electrode metal and wiring metal in a step difference part. <P>SOLUTION: In a method for forming an active layer in an element part of a semiconductor wafer by using an ion implanting method or a diffusion method, or an element isolation method of a semiconductor element, by increasing electrical resistance of a part except an element part after the active layer is formed over the whole semiconductor wafer, this method for manufacturing a semiconductor device includes a process for forming the active layer on a semiconductor substrate, a process for forming a spacer layer for lift-off on an upper layer of the active layer, a process for anisotropically working the spacer layer, a process for working a semiconductor layer containing the active layer, by using the spacer layer or mask material for working the spacer layer as a mask, a process for directivity-depositing an insulating film on the spacer layer and on the entire surface of an exposed semiconductor layer, and a process for eliminating the spacer layer, by using an etching agent for etching and eliminating only the spacer layer. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an element isolation structure.

[0002]

2. Description of the Related Art Separation of semiconductor elements is indispensable for eliminating unnecessary electrical influences between elements. The method of separation is roughly divided into the element part of the wafer,
A method of forming an active layer by an ion implantation method or a diffusion method,
After forming the active layer on the entire surface of the wafer, there is a method of electrically increasing the resistance only in the portion other than the element portion. The former is difficult to control the film thickness of the ion-implanted layer and the diffusion layer, and requires high-temperature heat treatment for activation and diffusion, and is not suitable for a thermally unstable element such as a compound semiconductor. The latter uses a method of increasing the resistance by implanting ions in parts other than the element part, or a mesa type element isolation method, but in the case of the ion implantation method, in order to obtain the high resistance required for element isolation, high temperature Heat treatment is required, and the deterioration of characteristics becomes a problem due to the deterioration of crystallinity. Also, in the case of mesa type element isolation,
After the mesa processing, a leak current is generated between the active layer exposed on the processed side surface and the electrode metal deposited on the side surface, which causes characteristic deterioration. In order to prevent this, only the active layer exposed on the side surface is selectively etched to prevent contact with the electrode metal.However, due to the space generated by the etching of the active layer, the electrode metal is stepped. There remains a problem that it breaks and causes an increase in resistance. Further, in the mesa type element isolation, since the conductive layer portion is etched, a large step is generated between the etching exposed layer and the outermost surface layer of the semiconductor element.
This may cause a problem such as step breakage in a step portion of a wiring layer formed later. A flattening step is required to prevent this, and the process becomes complicated.

[0003]

SUMMARY OF THE INVENTION The present invention provides a simple method for characteristic deterioration due to high temperature heat treatment, generation of leak current due to contact between an electrode metal and an active layer, increase in resistance due to electrode metal step breakage, and wiring layer formation due to a high step. It is an object of the present invention to provide an element isolation process that prevents step breakage and the like.

[0004]

In order to solve the above problems, according to the present invention, a method of forming an active layer on an element portion of a semiconductor wafer by an ion implantation method or a diffusion method, or
The following steps are performed in the element isolation method for a semiconductor element, which is performed by forming an active layer on the entire surface of a semiconductor wafer and then electrically increasing the resistance of the portion other than the element portion. First, an active layer is formed on a semiconductor substrate, a lift-off spacer layer is formed above the active layer, and the lift-off spacer layer is anisotropically processed. Next, the semiconductor layer including the active layer is processed by using the spacer layer or a mask material for processing the spacer layer as a mask, and an insulating film is directionally deposited on the entire surface of the spacer layer and the exposed semiconductor layer. Next, the spacer layer is removed by using an etchant that removes only the spacer layer, so that the insulating film is embedded only in the upper portion of the exposed semiconductor layer. By embedding an insulating film in the semiconductor removed portion,
It is possible to prevent contact between the electrode layer and the active layer on the exposed side surface where the semiconductor is removed by etching. Further, by making the thickness of the insulating film to be buried almost equal to the thickness of the removed semiconductor, step breakage of the electrode metal does not occur and increase in resistance can be prevented. Moreover, since the material to be embedded is an insulating film, insulation between elements is sufficient. Further, since the step portion etched for isolation is buried, the step difference between the element isolation etching exposed layer and the outermost surface layer of the semiconductor element can be reduced.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on Examples.
Reveal Example 1: FIG. 1 shows strain relaxation HEMT (High of Example 1 of the present invention.
Electron Mobility Transistor) plane structure and cross section
The structure is shown. N-In for element isolation_0.5Ga_0.5As cap
Layer 11, InP Layer 10, In_0.5Al_0.5As layer 9, n-In_0.5Al_0.5As Cat
Rear supply layer 8, In_0.5Al_0.5As layer 7, In_0.5Ga_0.5As active layer 6
And In_0.5Al_0.5A part of the As barrier layer 5 is etched and its
Is filled with the AlN film 14. Genuine gate power
The connection part between the pole part and the extraction pad part is on the AlN film 14.
It has a structure formed in. Next, in Fig. 2, the same strain relaxation H
The manufacturing process of EMT is shown. Manufacturing of strain relaxation HEMT according to Fig. 2 below
The process will be described. 28nm thick undoped G on GaAs substrate 1
aAs buffer layer 2, 20 nm thick undoped AlAs buffer layer
3, 600nm thick undoped InAlAs step graded
Layer 4 (InAs molar ratio varying from 0.15 to 0.45), thickness 200 nm
Undoped In_0.5Al _0.5As barrier layer 5, 20 nm thick
Dope In_0.5Ga_0.5As active layer 6, 2 nm thick undoped In
_0.5Al_0.5As layer 7, 12 nm thick Si-doped n-In_0.5Al_0.5As key
Carrier supply layer 8 (5x10¹⁸cm^-3), 10 nm thick undoped I
n_0.5Al_0.5As layer 9, 7 nm thick undoped InP layer 10, thickness 12
0 nm Si-doped n-In_0.5Ga_0.5As cap layer 11 (5x10¹⁹cm
^-3) Are sequentially formed by an epitaxial growth method. next,
200nm thick PSG film for lift-off spacers on the entire surface of the wafer 12
Are formed by a CVD (Chemical Vaper Deposision) method.
Next, a photoresist pattern 13 is formed on the portion where the HEMT is formed.
(Fig. 2 (a)). Using photoresist 13 as a mask
PSG film 12 and n-In_0.5Ga_0.5As cap layer 11, InP layer
10, In_0.5Al_0.5As layer 9, n-In_0.5Al_0.5As carrier supply layer
8, In_0.5Al_0.5As layer 7, In_0.5Ga_0.5As active layer 6 and In_0.5Al
_0.5Part of As barrier layer 5 is RIE (Reactive Ion Etching)
Method is used to perform anisotropic etching (Fig. 2 (b)). Resist
After removal, ECR (Electron Cyclotron Resonance)
A 200nm thick AlN film 14 is formed on the entire surface by the putting method.
(Fig. 2 (c)). The ECR sputtering method at this time
Deposition conditions are RF power 500W, μ wave power 800W, Ar gas / N2
With a gas flow ratio of 23 / 6.5 sccm, a film with strong directivity under these conditions
Can be formed and the thickness of the AlN film 14 is half
If it is smaller than the step of the conductor layer, the AlN film is formed on the side surface of the PSG film 12.
Has a feature that is not formed. 1/100 HF in this state
Immerse the wafer in the aqueous solution for about 60 minutes. AlN film is strong against HF
It is resistant to etching during this time.
Yes. In contrast, the PSG film can be easily etched with HF.
You can The side surface of the PSG film 12 is covered with the AlN film 14.
Since there is no PSG film, etching of the PSG film 12 proceeds from there,
By etching the film 12, the AlN film 14 on the PSG film 12 is removed.
It can be removed (Fig. 2 (d)). Next resist
The source electrode 15 and the drain electrode 16 are formed using the lift-off method.
Form. Next, n-In between the source and drain electrodes_0.5Ga_0.5
Part of the As cap layer 11 is removed by etching to expose the exposed In
The gate electrode 17 is formed on the P layer 10 to complete the HEMT (Fig. 2
(E)). Intrinsic gate electrode part formed on InP layer 10
The connection part between the lead-out pad and the lead-out pad is formed on the AlN film.
In the connection part and the side of the mesa_0.5Ga_0.5As active layer 6
There is no contact with, and the leakage current caused by the contact is prevented.
Can be stopped. The surface of the InP layer 10 and the surface of the AlN film 14 are almost the same.
Since it is on a flat surface, step breaks in the connection part due to steps
do not do. Example 2: FIG. 3 shows the InGaP / GaAs heterojunction of Example 2 of the present invention.
HBT: Hetero Bipore Transi
stor) cross-section structure. For element isolation,
Part of the rectifier layer 19 and the GaAs substrate 18 is etched,
The structure is such that a portion is embedded with the SiN film 28. Next
Fig. 4 shows the same InGaP / GaAs heterojunction bipolar transistor.
The manufacturing process of a star is shown. InGaP / GaAs
The manufacturing process of the junction bipolar transistor will be described.
A 700 nm thick Si-doped GaAs subcollector is formed on the GaAs substrate 18.
Layer 19 (5x10¹⁸cm^-3), 150 nm thick Si-doped GaAs core
Kuta layer 20 (5x10¹⁸cm^-3), A C-doped GaAs substrate with a thickness of 30 nm
Layer 21 (2x10²⁰cm^-3), Si-doped In with a thickness of 50 nm_0.5Ga_0.5
P emitter layer 22 (1x10¹⁸cm^-3), Si-doped Ga with a thickness of 100 nm
As cap layer 23 (5x10¹⁸cm^-3,) And a 50 nm thick step
Graded Si-doped InGaAs cap layer 24 (InAs module
Change from 0 to 0.5, 8x10¹⁸cm^-3From 4x10¹⁹cm^-3)
The layers are sequentially formed by the epitaxial method. Next, the InGaAs key
A WSi film with a thickness of 700 nm is deposited on the cap layer 24, and
Vertical processing of the WSi film with a mask
Form (Fig. 4 (a)). Next, mask the emitter electrode 25
InGaAs cap layer 24 and GaAs cap layer 23 and
Etch the miter layer 22 to expose the GaAs base layer 21.
(Fig. 4 (b)). Next, the entire surface of the wafer is SiO₂Forming a film,
SiO 2 with side wall length = 1.0 μm by anisotropic dry etching₂Side wall
Forming 26. Next, the emitter electrode 25 and SiO₂Side wall
Etch the GaAs base layer 21 and the GaAs collector layer 20.
To expose the GaAs subcollector layer 19 (FIG. 4 (c)).
Resist is applied on the entire surface and element isolation resist pattern
Forming 27. Next, using the resist pattern 27 as a mask, Ga
RIE method up to the middle of As subcollector layer 19 and GaAs substrate 18
Anisotropically etched at (Fig. 4 (d)). Then ECR (E
lectron Cyclotron Resonance) Sputtering method
To form a 800 nm thick SiN film 28 on the entire surface (see FIG. 4).
(E)). The deposition conditions of the ECR sputtering method at this time are
RF power 500W, μ wave power 500W, Ar gas / N2 gas flow ratio 2
At 0/8 sccm, a film with strong directivity can be formed under these conditions.
Yes, the thickness of the SiN film 28 is the step of the etched semiconductor layer
If it is smaller, the SiN film is formed on the side surface of the resist pattern 27.
Has a feature that is not formed. Next, use a resist stripper
Dip the air and remove the resist. At this time on the resist
The SiN film formed on the surface is removed and the SiN film is lifted off.
Is possible (Fig. 4 (f)). This allows the GaAs subcollection
Of about 800 nm formed between the laser layer 19 and the GaAs substrate 18.
The step portion can be filled with the SiN film 28. Then SiO₂
The side wall 26 is removed, and the base electrode 29 on the GaAs base layer 21 is
Reforming the collector electrode 30 on the GaAs subcollector layer 19
The HBT is completed by the soft-off method (Fig. 4 (g)). Elementary
The SiN film 28 is
Is embedded, so element isolation etching exposure
It is possible to reduce the step difference between the layer and the outermost surface layer of the semiconductor device.
It is possible and the wiring metal step that was caused by the step
It is possible to prevent breakage and omit other flattening heights
Becomes

[0006]

According to the present invention, it is possible to form a semiconductor element with high flatness without causing deterioration of element characteristics by burying an insulating film in the step portion of the isolation portion in the element isolation step of the semiconductor element. Become.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view of a strain relaxation HEMT according to the present invention.

FIG. 2 is a sectional view of a strain relaxation HEMT according to the present invention.

FIG. 3 is a cross-sectional view of an InGaP / GaAs heterojunction bipolar transistor according to the present invention.

FIG. 4 is a cross-sectional view of an InGaP / GaAs heterojunction bipolar transistor according to the present invention.

[Explanation of symbols]

1 ... GaAs substrate, 2 ... undoped GaAs buffer layer, 3 ... undoped AlAs buffer layer, 4 ... undoped InAlAs step graded layer, 5 ... undoped In _0.5 Al _0.5 As barrier layer, 6 ... undoped In _0.5 Ga _0.5 As active layer, 7 ... Undoped
In _0.5 Al _0.5 As layer, 8 ... Si-doped n-In _0.5 Al _0.5 As carrier supply layer, 9 ... Undoped In _0.5 Al _0.5 As layer, 10 ... Undoped InP layer, 11 ... Si-doped n-In _0.5 Ga _0.5 As cap Layer, 12
… PSG film for lift-off spacer, 13… Photoresist pattern, 14… AlN film, 15… Source electrode, 16… Drain electrode, 17… Gate electrode, 18… GaAs substrate, 19… Si-doped GaAs
Sub collector layer, 20 ... Si-doped GaAs collector layer, 21 ... C
Doped GaAs base layer, 22 ... Si-doped In _0.5 Ga _0.5 P emitter layer, 23 ... Si-doped GaAs cap layer, 24 ... Step graded Si-doped InGaAs cap layer, 25 ... Emitter electrode, 26 ... SiO ₂ sidewall, 27 ... Resist Pattern, 28 ... SiN
Membrane, 29 ... Base electrode, 30 ... Collector electrode.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/812 (72) Inventor Hiroshi Ota 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Stock company Hitachi Ultra LSI Systems (72) Inventor Koji Hirata 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ultra LSI Systems (72) Inventor Ken Kikawa 1-280, Higashi Koigokubo, Kokubunji, Tokyo F-Term (Central), Central Research Laboratory, Hitachi, Ltd. (reference) 5F003 AP03 BA23 BA27 BA92 BF06 BM03 BP12 BP93 5F032 AA35 AA46 AA54 CA16 CA18 DA07 DA21 DA23 DA24 DA25 DA30 5F102 GB01 GC01 GD01 G05 GK05 GK06 GK08 GL04 GM04 GM08 GN04

Claims (4)

[Claims] 1. A method of forming an active layer on an element portion of a semiconductor wafer by an ion implantation method or a diffusion method, or after forming an active layer on the entire surface of the semiconductor wafer, a portion other than the element portion has an electrically high resistance. In the element isolation method of a semiconductor element performed by forming a semiconductor layer, a step of forming an active layer on a semiconductor substrate,
Forming a lift-off spacer layer above the active layer; anisotropically processing the spacer layer; and using the spacer layer or a mask material for processing the spacer layer as a mask. A step of processing a semiconductor layer containing, a step of directionally depositing an insulating film on the entire surface of the spacer layer and the exposed semiconductor layer, and a step of removing the spacer layer using an etching agent for etching and removing only the spacer layer. A method of manufacturing a semiconductor device, comprising: 2. The insulating film directional deposition step is performed by an ECR sputtering method.
A method for manufacturing a semiconductor device as described above. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the element isolation step is an element isolation step of a field effect transistor. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the element isolation step is an element isolation step of a hetero bipolar transistor.