JP2003198266A - Circuit and method for generating control voltage, circuit and method for generating control current, and portable terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To limit the bandwidth of noise to be outputted, and to prevent NF characteristics in a variable gain circuit from being affected in a bandwidth that is detuned from an output frequency. <P>SOLUTION: A low-pass filter 115 is added to the output of a control voltage generation circuit for converting the differential voltage between voltage obtained by attenuating a control voltage that is given from the outside by an attenuator 101 and a reference voltage outputted from a reference voltage generator 102 so that the differential voltage becomes a voltage that is proportional to thermoelectric voltage, thus limiting the bandwidth of noise outputted from the control voltage generation circuit and preventing NF characteristics in a variable gain circuit from being affected in the bandwidth that is detuned from the output frequency. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control voltage generating circuit and method, a control current generating circuit and method, and a control voltage for controlling a variable gain circuit suitable for use in, for example, a transceiver used in a mobile communication system. The present invention relates to a mobile terminal using a generation circuit.

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram showing a conventional general variable gain circuit. As shown in FIG. 11, the input signal V
The id is input between the bases of the transistors 601 and 610 and the bases of the transistors 602 and 611. Each of the emitters of the transistors 601 and 602 has a resistor 6
03, and grounded via current sources 604 and 605. Further, the emitters of the transistors 610 and 611 are connected via a resistor 612, and the current source 61
It is grounded via 3, 614.

The emitter of transistors 606 and 607 is connected to the collector of the transistor 601, and the collectors of the transistor 602 are connected to the transistors 608 and 60.
Nine emitters are connected. The collector of the transistor 610 is connected to the emitters of the transistors 615 and 616, and the collector of the transistor 611 is connected to the emitters of the transistors 617 and 618.

The control voltage Vcd is the same as that of the transistor 6
It is inputted between the bases of 06, 609, 616 and 617 and the bases of the transistors 607, 608, 615 and 618. The collectors of the transistors 606 and 615 are connected to the power supply 621 via the resistor 619, and the collectors of the transistors 609 and 618 are connected to the power supply 621 via the resistor 620. Transistor 60
The collectors of 7, 608, 616, and 617 are power sources 621.
The output signal Vod is output from between the collectors of the transistors 615 and 618.

Next, the operation of the variable gain circuit shown in FIG. 11 will be described. The gain of the variable gain circuit shown in FIG.
When (= Vod / Vid), the gain G6 is expressed by (Equation 1). G6 = R63 (M · gm61 + gm62) / (1 + M) (Equation 1) where R63 is the resistance value of the resistors 619 and 620, and gm61, gm62, and M are (Equation 2), (Equation 3), and (Equation 4), respectively. ) Is given. gm61 = 1 / (VT / I61 + R61 / 2) (Equation 2) gm62 = 1 / (VT / I62 + R62 / 2) (Equation 3) M = exp (Vcd / VT) (Equation 4)

VT is a thermal voltage given by (Equation 5), I61 is a current value of the current sources 604 and 605, and I62 is a current value of the current sources 613 and 614.
Further, R61 is the resistance value of the resistor 603, and R62 is the resistance value of the resistor 612. VT = kT / q (Equation 5) Here, k is the Boltzmann constant, T is the absolute temperature, and q is the charge amount.

M is a control voltage V as shown in (Equation 4).
Since the term of cd is included, the gain G6 can be changed with respect to the control voltage Vcd. The gain G6 given by (Equation 1) is M or gm61, which is a variable depending on temperature.
Includes gm62.

Further, assuming that the variable gain circuit of FIG. 11 is integrated into a circuit, the resistance inside the integrated circuit has a temperature coefficient, so that R63 in (Equation 1) is also a variable depending on temperature.
Among these variables depending on temperature, for gm61 and gm62 given by (Equation 2) and (Equation 3), the current values of the current sources 604, 605, 613 and 614 are set to VT /
By setting so as to be proportional to R, gm61, gm6
It is easy to set the temperature characteristic of 2 to R proportionality, that is, the temperature coefficient of resistance, and it can be set so as to cancel out the temperature coefficient of R63 in (Equation 1).

Regarding M, the temperature dependence of the control voltage Vcd is set to VT proportional, that is, the temperature coefficient of the thermal voltage so that there is no temperature dependence, and the gain G6 given by (Equation 1) is given. Does not have temperature dependence.

Next, FIG. 12 is a circuit diagram showing an example of a control voltage generating circuit capable of setting the temperature characteristic of the control voltage Vcd in proportion to VT. A circuit example similar to this is disclosed in JP-A-8-265.
It is also shown in the 068 publication. Control voltage input Vcin
Are applied to the attenuator 101, and the output of the attenuator 101 is applied to the base of the transistor 103. The output of the reference voltage generator 102 is provided to the base of the transistor 104.

The emitters of the transistors 103 and 104 are connected via a resistor 105, and current sources 106 and 107 are connected.
Grounded through. The collector of the transistor 103 is connected to the emitter of the transistor 108 whose base and collector are connected to the power supply 117 and the transistor 111.
Of the transistor 104, and the collector of the transistor 104 is connected to the emitter of the transistor 109 whose base and collector are connected to the power supply 117 and the base of the transistor 110.

The emitters of the transistors 110 and 111 are grounded via a current source 112. The collector of the transistor 110 is connected to the power supply 117 via the resistor 113, and the collector of the transistor 111 is connected to the power supply 117 via the resistor 114. Transistor 11
The collector-to-collector voltages of 0 and 111 are output as the control voltage Vcd via the buffer 116.

Next, the operation of the circuit shown in FIG. 12 will be described. The control voltage input Vcin actually given from the outside is often input in a wide voltage range from GND to the power supply voltage. Therefore, Vcin is compressed to 1 / k by the attenuator 101 and then applied to the base of the transistor 103 in order to facilitate input to the circuits in the subsequent stages. Here, a case where Vcin is input at 0 to 3 V assuming a single 3 V power supply will be described.

When Vcin is input at 0 to 3V, it is desirable to set the output Vref7 of the reference voltage generator 102 as shown in (Equation 6). Center voltage of Vcin 1.5
This is because the circuits can be operated most efficiently if the bases of the transistors 103 and 104 are set to the same potential when V is input. Vref7 = 1.5 / k (Equation 6)

The potential difference ΔV [103, 104] generated between the bases of the transistors 103, 104 is ΔV [1
[03, 104] = Vcin / k-Vref7, and therefore is represented by (Equation 7) when (Equation 6) is considered. ΔV [103, 104] = (Vcin−1.5) / k (Equation 7)

Although the transistors 103 and 104 output a differential current due to the potential difference ΔV [103, 104], it is very difficult to express this differential current as a DC transfer characteristic because of the resistor 105. Therefore, this differential current will be expressed by a small signal transfer characteristic.

Due to the potential difference ΔV [103, 104], the collector current of the transistor 103 becomes (I71 + ΔI [1
03]), the collector current of the transistor 104 becomes (I71−ΔI [103]). ΔI [103]
Is expressed by (Equation 8), where the resistance value of the resistor 105 is Ri7. ΔI [103] = ΔV [103, 104] / (2VT / I71 + Ri7) (Equation 8) Here, I71 is each current value of the current sources 106 and 107.

The collector current of the transistor 103 (I7
1 + ΔI [103]) flows into the transistor 108 and the collector current (I71−ΔI) of the transistor 104.
[103]) flows into the transistor 109,
The potential difference ΔV [110, 111] generated between the emitters of the transistors 108 and 109, that is, between the bases of the transistors 110 and 111 is given by (Equation 9). ΔV [110, 111] = VT · ln {(I71 + ΔI [103]) / (I71−ΔI [103])} (Equation 9)

Due to the potential difference ΔV [110, 111], the collector current of the transistor 110 becomes (I72 + ΔI [1
10]), the collector current of the transistor 111 becomes (I72−ΔI [110]), so ΔV [11
0,111] can also be expressed as in (Expression 10). ΔV [110, 111] = VT · ln {(I72 + ΔI [110]) / (I72−ΔI [110])} (Formula 10) Here, I72 is 1/2 of the current value of the current source 112.

From (Equation 9) and (Equation 10), the equation (Equation 11) is obtained. ΔI [110] = ΔI [103] · I72 / I71 (Equation 11) The voltage generated between the collectors of the transistors 110 and 111 is generated as the control voltage output Vcd via the buffer. Vcd is represented by (Equation 12) when the resistance values of the resistors 113 and 114 are Ro7. Vcd = 2ΔI [110] · Ro7 (Equation 12)

When Formula 12 is rearranged in consideration of Formula 7, Formula 8 and Formula 11, Vcd / (Vcin-1.5) = 2Ro7 · I72 / {k · I71 (2VT / I71 + Ri7)} (Equation 13), but if Ri7 >> 2VT / I71 (Equation 14) holds, (Equation 13) can be easily expressed as (Equation 15). Vcd / (Vcin-1.5) = 2Ro7 · I72 / (k · Ri7 · I71) (Equation 15)

Here, the current value of the current source 112 (2 · I7
2) is proportional to VT / R and the current value I of the current sources 106 and 107
71 is 1 / R proportional, Vcd is (Vcin-1.
It can be set to be proportional to VT with respect to 5).

The above equation is derived on the assumption that the transistors 103 and 104 operate in the small signal mode in the circuit of FIG. Therefore, the transistor 10
The potential difference ΔV [10
Considering that the maximum value of [3, 104] is 1.5 V from (Equation 7), it is premised that the condition of (Equation 16) is satisfied. I71 ・ Ri7 >> 1.5 / k (Formula 16)

VT in (Equation 14) is about 26 m at room temperature.
Since it is V, the value of k in (Equation 16) is about 30 (=
In the range smaller than 1500/52), it is clear that the condition of (Equation 16) is stricter than that of (Equation 14), and the current value I71 of the current sources 106 and 107 and the resistance value Ri7 of the resistor 105 are (Equation 16). ) Is often restricted by. Increasing k to relax the constraint according to (Equation 16) means that Vcin is input after being greatly attenuated, which is not preferable because the circuit is required to operate with high accuracy. I can say.

[0025]

However, as can be seen from the fact that the variable gain circuit as shown in FIG. 11 has a configuration similar to that of a Gilbert type mixer which is often used as a general mixer circuit, It has a function of multiplying a signal and a control voltage and outputting. Therefore, when the control voltage output Vcd from the control voltage generating circuit shown in FIG. 12 is small, the gain as the mixer becomes large, and the noise added to the control voltage output Vcd is multiplied by the input signal and output, There is a problem that the NF characteristic of the variable gain circuit is deteriorated.

In particular, when the variable gain circuit is used in the output stage of the transmitter, the input signal becomes large, so that the output multiplied by the noise contained in the control voltage output Vcd also becomes large and the NF characteristic Degradation is noticeable. Generally, in a transmitter, noise in the reception band must be reduced in order not to affect the input of the receiver.

Therefore, the NF characteristic of the variable gain circuit in the reception band is often emphasized, but when the control voltage generating circuit shown in FIG. 12 is used, the noise from the control voltage generating circuit covers a wide band. , The NF characteristic of the variable gain circuit in the reception band is affected. For example, there is a problem that the NF characteristic at a distance of 1 MHz from the transmission frequency becomes as shown in FIG. 13 (in FIG. 13, the larger the control voltage, the larger the gain).

The present invention has been made to solve the above-mentioned problems, and limits the band of noise to be output, and N of the variable gain circuit in the band detuned from the output frequency.
An object of the present invention is to provide a control voltage generation circuit and method, a control current generation circuit and method, and a mobile terminal using the control voltage generation circuit, which can prevent the F characteristic from being affected.

[0029]

A control voltage generation circuit according to the present invention is a differential voltage between a voltage obtained by attenuating an externally applied control voltage by an attenuator and a reference voltage output from a reference voltage generator. Is converted into a voltage proportional to the thermal voltage and output through a low pass filter.
Thus, by limiting the band of noise added to the control voltage, it is possible to prevent the NF characteristic of the variable gain circuit in the band detuned from the output frequency from being affected.

Further, a control voltage generating circuit according to another invention converts a differential voltage between a control voltage applied from the outside and a reference voltage output from a reference voltage generator into a current and then a voltage proportional to a thermal voltage. It is converted so that it will be output through a low pass filter. As a result, the band of noise added to the control voltage can be further limited by not using the attenuator, and the NF characteristic of the variable gain circuit in the band detuned from the output frequency is not affected. be able to.

The control current generating circuit according to the present invention is
The output obtained by the control voltage generating circuit described above is output in the state of current. As a result, the current consumption can be reduced as compared with the control voltage generating circuit by not using the buffer.

In the control voltage generating method according to the present invention, the difference voltage between the voltage obtained by attenuating the control voltage applied from the outside by the attenuator and the reference voltage output from the reference voltage generator is a voltage proportional to the thermal voltage. It is converted so that it is output through a low pass filter. Thus, by limiting the band of noise added to the control voltage, it is possible to prevent the NF characteristic of the variable gain circuit in the band detuned from the output frequency from being affected.

Further, in a control voltage generating method according to another invention, a differential voltage between a control voltage applied from the outside and a reference voltage output from a reference voltage generator is converted into a current and then a voltage proportional to a thermal voltage is generated. It is converted so that it will be output through a low pass filter. As a result, the band of noise added to the control voltage can be further limited by not using the attenuator, and the NF characteristic of the variable gain circuit in the band detuned from the output frequency is not affected. be able to.

The control current generating method according to the present invention is
The output obtained by the control voltage generating circuit described above is output in the state of current. As a result, the current consumption can be reduced as compared with the control voltage generating circuit by not using the buffer.

Further, the portable terminal according to the present invention is a portable terminal using the control voltage generating circuit described above, and can realize a high-performance portable terminal.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram showing a control voltage generating circuit according to a first embodiment of the present invention. Figure 1
The control voltage generating circuit shown in (1) has a form in which a low-pass filter 115 is inserted before the buffer 116 in the control voltage generating circuit shown in FIG. That is, the voltage between the collectors of the transistors 110 and 111 is controlled by the control voltage Vcd via the low-pass filter 115 and the buffer 116.
By limiting the band of noise added to the control voltage Vcd, the NF characteristic of the variable gain circuit in the band detuned from the output frequency is not affected.

FIG. 2 shows the noise level output from the control voltage generation circuit shown in FIG. 1 (solid line) and the noise level output from the control voltage generation circuit shown in FIG. 12 (dotted line) to 1M.
It is the figure compared in the frequency of Hz. As shown in FIG. 2, the noise level output from the control voltage generation circuit of FIG. 1 can be greatly reduced with respect to the noise level output from the control voltage generation circuit of FIG. The NF characteristic of the gain circuit is not affected.

Therefore, while the NF characteristic of the variable gain circuit when the control voltage generating circuit of FIG. 12 is used is shown in FIG. 13, the NF characteristic of the variable gain circuit when the control voltage generating circuit of FIG. 1 is used is shown. The NF characteristic is as shown by the solid line in FIG. 3 (for comparison, the result of FIG. 13 is also shown by a dotted line), and is greatly improved.

As described above, according to the first embodiment, the attenuator 10 receives a wide range of control voltage from the outside.
Voltage obtained by attenuating by 1 and reference voltage generator 102
The difference voltage from the reference voltage output from the
It is converted so that it becomes a (proportional) voltage, and the low-pass filter 1
By outputting the noise through the buffer 15 and the buffer 116, the band of noise added to the control voltage can be limited, and the NF of the variable gain circuit in the band detuned from the output frequency.
It is possible to prevent the characteristics from being affected.

(Second Embodiment) FIG. 4 is a circuit diagram showing a control voltage generating circuit according to a second embodiment of the present invention. In the control voltage generation circuit shown in FIG. 4, the control voltage input V
Cin is given to the base of a transistor 303 commonly connected to the collector via a resistor 301. The output of the reference voltage generator 302 is the transistors 304, 311.
Given to each base of. Transistors 303 and 304
Each emitter of is connected to the ground via a current source 305.
The collector of the transistor 303 is the transistor 306.
Connected to the collector of and the base of transistor 310,
The collector of the transistor 304 is the transistor 306.
Of the transistor 307 and the base and collector of the transistor 307.

The emitter of the transistor 306 is connected to the power source 317 via the resistor 308, and the emitter of the transistor 307 is connected to the power source 317 via the resistor 309. The emitters of the transistors 310 and 311 are grounded via the current source 312. The collector of the transistor 310 is connected to the power supply 317 via the resistor 313, and the collector of the transistor 311 is the resistor 314.
Is connected to the power source 317 via. Transistor 3
The voltage between the collectors 10 and 311 is low-pass filter 3
15, and is output as the control voltage Vcd via the buffer 316.

Next, the operation of the circuit shown in FIG. 4 will be described. Again, assuming a single 3V power supply, 0-3V
The case where the control voltage Vcin is input will be described. If the resistance value of the resistor 301 is Ri3 and the output of the reference voltage generator 302 is Vref3, Vcin becomes (Equation 1
It is converted into the current ΔIcin represented by 7). ΔIcin = (Vcin−Vref3−ΔV [303, 304]) / Ri3 (Equation 17)

Here, ΔV [303, 304] is ΔIc
When in occurs, the transistors 303 and 30
4 is a potential difference generated between each base. That is, Δ
The transistors 303 and 304 operate so that Icin is the difference between the current flowing through the transistor 303 and the current flowing through the transistor 306. When Vcin is input at 0 to 3 V, it is desirable to set Vref3 as in (Equation 18). This is because if the bases of the transistors 303 and 304 have the same potential when the center voltage of Vcin of 1.5 V is input, the circuit can be operated most efficiently. Vref3 = 1.5 (Equation 18)

ΔV [303, 304] is ΔIci
When n is generated, the current flowing through the transistor 303 becomes (I31 + ΔIcin / 2) and the current flowing through the transistor 304 becomes (I31−ΔIcin / 2), which can be expressed as (Expression 19). ΔV [303, 304] = VT · ln {(I31 + ΔIcin / 2) / (I31−ΔIcin / 2)} (Formula 19) Here, I31 is 1/2 of the current value of the current source 305.

ΔV [303, 304] is the transistor 3
The potential difference ΔV [31] generated between the bases 10 and 311
0,311], and ΔV [310,311] causes the current flowing in the transistor 310 to be (I32 + ΔI
[310]) and the current flowing through the transistor 311 becomes (I32−ΔI [310]), so ΔV [30
3, 304] can also be expressed as in (Equation 20). ΔV [303, 304] = VT · ln {(I32 + ΔI [310]) / (I32−ΔI [310])} (Equation 20) Here, I32 is 1/2 of the current value of the current source 312.

The equation (21) is obtained from the equations (19) and (20). ΔI [310] = ΔIcin · I32 / (2 · I31) (Equation 21) The voltage generated between the collectors of the transistors 310 and 311 is generated as the control voltage output Vcd via the low-pass filter 315 and the buffer 316. If the resistance value of the resistors 313 and 314 is Ro3, Vcd can be calculated by
It is represented by 2). Vcd = ΔIcin · Ro3 · I32 / I31 (Formula 22)

Considering (Equation 17) and (Equation 18), (Equation 2
When 2) is rearranged, it is expressed as Vcd / (Vcin-1.5-ΔV [303, 304]) = Ro3 · I32 / (I31 · Ri3) (Equation 23), where ΔV [303, 304] ] Becomes a value that can be ignored with respect to (Vcin-1.5) if (Equation 24) holds, and (Equation 23) can be easily expressed as (Equation 25). 2 · I31 >> ΔIcin (Equation 24) Vcd / (Vcin−1.5) = Ro3 · I32 / (I31 · Ri3) (Equation 25)

Further, the maximum value of ΔIcin is (Equation 24)
If it is satisfied that (1.5 / Ri3) is satisfied, then (Expression 24) can be expressed as (Expression 26). I31 · Ri3 >> 0.75 (Equation 26) In (Equation 25), the current value (2 · I32) of the current source 312 is proportional to VT / R, and the current value (2 · I31) of the current source 305 is 1 / R. If proportional, Vcd can be set to be VT proportional to (Vcin-1.5).

FIG. 4 differs from FIG. 1 in that the control voltage input Vc
Since in is processed by current conversion using the resistor 301 instead of the attenuator 101, the circuit scale can be reduced as compared with the control voltage generation circuit shown in FIG. 1, so that the generated noise can also be reduced.

FIG. 5 is a diagram comparing the noise level output from the control voltage generation circuit shown in FIG. 4 (solid line) with the noise level output from the control voltage generation circuit shown in FIG. 1 (dotted line) at a frequency of 1 MHz. is there. As shown in FIG. 5, the noise level output from the control voltage generation circuit of FIG.
The noise level output from the control voltage generation circuit can be reduced.

FIG. 6 shows the NF characteristic of the variable gain circuit when the control voltage generating circuit shown in FIG. 4 is used (solid line) and the NF characteristic of the variable gain circuit when using the control voltage generating circuit shown in FIG. Although it is a comparison of (dotted line), it can be seen that it is improved by using the control voltage generating circuit shown in FIG.

(Third Embodiment) FIG. 7 is a circuit diagram showing a control current generating circuit according to a third embodiment of the present invention. The control current generation circuit shown in FIG. 7 is a circuit suitable for controlling the variable gain circuit as shown in FIG.
Unlike the variable gain circuit shown in FIG. 11, FIG. 14 is generally known as a current-controlled variable gain circuit.

First, the variable gain circuit shown in FIG. 14 will be described.
It is input between each base of 804 and each base of transistors 802 and 805. Transistors 801, 802
The respective emitters of are connected via a resistor 803 and are connected to the output terminals of the two-output current mirror circuit 81, respectively. The 2-output current mirror circuit 81 has an input current α
It outputs double the current.

The emitters of the transistors 804 and 805 are connected via a resistor 806, and are connected to the output terminals of the 2-output current mirror circuit 82, respectively.
The two-output current mirror circuit 82 outputs a current that is β times the input current. The collectors of the transistors 801 and 804 are connected to the power supply 809 via the resistor 807, and the collectors of the transistors 802 and 805 are connected to the resistor 8 respectively.
It is connected to the power source 809 via 08. The output signal Vod is output between the collectors of the transistors 804 and 805. The control currents Ic and Icx are connected to the input terminals of the 2-output current mirror circuits 81 and 82.

Next, the operation of the circuit shown in FIG. 14 will be described. The gain of the circuit shown in FIG. 14 is set to G8 (= Vod / Vi
Assuming d), the gain G8 is expressed by (Equation 27). G8 = R83 (gm81 + gm82) (Equation 27) where R83 is the resistance value of the resistors R807 and R808, and gm81 and gm82 are (Equation 28) and (Equation 2), respectively.
Given in 9). gm81 = 1 / {VT / (α · Ic) + R81 / 2} (Equation 28) gm82 = 1 / {VT / (β · Icx) + R82 / 2} (Equation 29) Note that VT is given by (Equation 5). Is the thermal voltage applied. Further, R81 is the resistance value of the resistor 803, and R82 is the resistance value of the resistor 806.

FIG. 4 described in the second embodiment described above.
By using the control voltage generating circuit shown in FIG.
A control current generating circuit shown in FIG. 8 is generally used as a circuit for generating x. In the control current generating circuit shown in FIG. 8, the function of the low-pass filter 315 in FIG. 4 is obtained by the capacitor 415 and the resistors 413 and 414, and the output of the buffer 416 is given between the bases of the transistors 418 and 419.

The emitters of the transistors 418 and 419 are connected to the power supply 417 via the current source 420,
The control current outputs Ic and Icx are obtained from the collectors of the transistors 418 and 419. Ic and Icx are calculated by the equation (3) by the control voltage output Vcd obtained from the buffer 416.
0) and (Expression 31). Ic = 2 · I43 · M / (1 + M) (Equation 30) Icx = 2 · I43 / (1 + M) (Equation 31) Note that M includes the term of the control voltage Vcd as shown in (Equation 4). , G8 can be changed with respect to the control voltage Vcd.

The gain G8 given by (Equation 27) includes gm81 and gm82 as variables depending on temperature. Further, if the variable gain circuit shown in FIG. 14 is integrated into a circuit, the resistance inside the integrated circuit has a temperature coefficient, and therefore R83 in (Equation 27) is also a variable depending on temperature.
Among these temperature-dependent variables, gm81 and gm82 given by (Equation 28) and (Equation 29) are
Ic and Icx represented by (Equation 30) and (Equation 31) are represented by VT.
By setting to be proportional to / R, gm81, gm
It is easy to set the temperature characteristic of 82 to R proportionality, that is, the temperature coefficient of resistance, and it can be set so as to cancel out the temperature coefficient of R83 in (Equation 27). Also, (Equation 3
0) and M included in (Equation 31), the temperature dependence of the temperature dependence of the control voltage Vcd is set to VT proportional, that is, the temperature coefficient of the thermal voltage, as shown in (Equation 4). In this case, the gain G8 given by (Equation 27) does not have temperature dependence.

The control current generating circuit shown in FIG. 7, which is the third embodiment of the present invention, differs from the control current generating circuit shown in FIG. 8 in the portions after the collectors of transistors 510 and 511. There is. The collector of the transistor 510 is connected to the base of the transistor 515, and is also connected to the collector of the transistor 515 via the resistor 513. The collector of the transistor 511 is connected to the base of the transistor 516 and via the resistor 514. It is connected to the collector of the transistor 516. The bases of the transistors 515 and 516 are connected via a capacitor 518, and the emitters are connected to a power supply 522 via a resistor 517.

In the circuit shown in FIG. 7, as in FIG.
The function of the low-pass filter 315 in FIG. 4 is obtained by the capacitor 518 and the resistors 513 and 514. The bases of the transistors 519 and 520 are transistors 515 and 5
16 is connected to each base, and each emitter has a resistor 5
It is connected to the power source 522 via 21. Note that the transistors 519 and 520 are the transistors 515 and 516, respectively.
Is equivalent to N parallel connections of
Reference numeral 21 is configured to have a resistance value of 1 / N of the resistance 517.

Next, the operation of the circuit shown in FIG. 7 will be described. The description overlapping with the contents described in the second embodiment will be omitted. The control voltage input Vcin causes the current flowing in the transistor 510 to be (I52 + ΔI).
[510]), and the current flowing in the transistor 511 becomes (I52−ΔI [510]), the potential difference ΔV [5 generated between the bases of the transistors 515 and 516.
15, 516] is represented by (Expression 32). ΔV [515, 516] = 2 · ΔI [510] · Ro5 (Equation 32) Here, Ro5 is the resistance value of the resistors 513 and 514.

Since N times the current flowing through the transistors 515 and 516 flows through the transistors 519 and 520, the control currents Ic and Icx are expressed by (Expression 33) and (Expression 34). Ic = 2 · N · I52 · L / (1 + L) (Equation 33) Icx = 2 · N · I52 / (1 + L) (Equation 34) where L is given by (Equation 35). L = exp (2 · ΔI [510] · Ro5 / VT) (Formula 35)

By the way, in the control current generating circuit shown in FIG. 8, M in (Equation 30) and (Equation 31) is expressed by (Equation 4), but the control voltage Vcd in (Equation 4) is (Equation 21) ) And (Equation 22), ΔI [310] is Δ
Considering that it corresponds to I [410] and Ro3 corresponds to Ro4, Vcd is 2 · ΔI [410] · Ro4, so M is also expressed as in (Expression 36). M = exp (2 · ΔI [410] · Ro4 / VT) (Formula 36)

Therefore, (Equation 35) is ΔI [510] R
If o5 is set to the same value as ΔI [410] · Ro4,
This is equivalent to (Expression 36) derived in the control current generation circuit shown in FIG. Also, in (Equation 33) and (Equation 34), if N · I52 is set to the same value as I43, (Equation 3)
0) and (equation 31) are equivalent to
The control current generation circuit shown in FIG. 7 and the control current generation circuit shown in FIG. 8 are functionally equivalent. However, the current of the differential pair that outputs the control current is not shown in FIG.
7 is obtained by switching the current, the noise generated is increased because the current switched by the preceding circuit is multiplied by N in FIG.

FIG. 9 is a diagram comparing the noise level output from the control current generation circuit shown in FIG. 7 (solid line) with the noise level output from the control current generation circuit shown in FIG. 8 (dotted line) at a frequency of 1 MHz. Is. As shown in FIG. 9, the noise level output from the control current generating circuit shown in FIG. 7 is higher than the noise level output from the control current generating circuit shown in FIG.

FIG. 10 shows the NF characteristic (solid line) of the variable gain circuit when the control current generating circuit shown in FIG. 7 is used, and FIG.
7 is a comparison of the NF characteristics (dotted line) of the variable gain circuit when the control current generating circuit shown in FIG. 7 is used, it can be seen that the NF characteristics are deteriorated by using the control current generating circuit shown in FIG. However, since the buffer 416 can be omitted from the control current generation circuit shown in FIG. 8, the consumption current of the circuit can be reduced by using the control current generation circuit shown in FIG.

Although each of the above-described embodiments relates to a control voltage generating circuit and method, a control current generating circuit and method, by configuring a portable terminal using the control voltage generating circuit described above, high performance can be achieved. The mobile terminal can be realized. In addition, if a base station connected to the mobile terminal is configured,
A high-performance base station can be realized. Furthermore, if a communication system including the base station is configured, a high performance communication system can be realized.

[0068]

As is apparent from the above description, according to the present invention, the band of noise added to the control voltage is limited,
It is possible not to affect the NF characteristic of the variable gain circuit in the band detuned from the output frequency.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a control voltage generating circuit according to a first embodiment of the present invention.

FIG. 2 is an output noise level characteristic diagram of the control voltage generating circuit according to the first embodiment of the present invention.

FIG. 3 is an NF characteristic diagram of the variable gain circuit when the control voltage generating circuit according to the first embodiment of the present invention is used.

FIG. 4 is a circuit diagram showing a control voltage generating circuit according to a second embodiment of the present invention.

FIG. 5 is an output noise level characteristic diagram of the control voltage generating circuit according to the second embodiment of the present invention.

FIG. 6 is an NF characteristic diagram of a variable gain circuit when the control voltage generating circuit according to the second embodiment of the present invention is used.

FIG. 7 is a circuit diagram showing a control current generating circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example in which the control voltage generating circuit according to the second embodiment of the present invention is applied as a control current generating circuit.

FIG. 9 is an output noise level characteristic diagram of the control current generating circuit according to the third embodiment of the present invention.

FIG. 10 is an NF characteristic diagram of the variable gain circuit when the control current generating circuit according to the third embodiment of the present invention is used.

FIG. 11 is a circuit diagram showing a conventional variable gain circuit (voltage control type).

FIG. 12 is a circuit diagram showing a conventional control voltage generation circuit.

FIG. 13 is an NF characteristic diagram of a variable gain circuit when a conventional control voltage generating circuit is used.

FIG. 14 is a circuit diagram showing a conventional variable gain circuit (current control type).

[Explanation of symbols]

81,82 2 output current mirror circuit 101 attenuator 102,302,402,502 reference voltage generator 103,104,108-111,303,304,3
06, 307, 310, 311, 403, 404, 40
6, 407, 410, 411, 418, 419, 50
3, 504, 506, 507, 510, 511, 51
5, 516, 519, 520, 601, 602, 606
~ 611, 615-618, 801, 802, 804,
805 transistors 105, 113, 114, 301, 308, 309, 3
13, 314, 401, 408, 409, 413, 41
4, 501, 508, 509, 513, 514, 51
7, 521, 603, 612, 619, 620, 80
3, 806, 807, 808 Resistors 106, 107, 112, 305, 312, 405, 4
12, 420, 505, 512, 604, 605, 61
3,614 Current source 115,315 Low-pass filter 116,316,416 Buffer 117,317,417,522,621,809 Power supply 415,518 Capacitor

Continued front page    F-term (reference) 5J066 AA01 AA12 AA58 AA59 CA41                       FA20 HA02 HA25 HA29 KA03                       KA05 KA09 KA11 KA23 KA42                       KA47 MA08 MA21 ND01 ND14                       ND22 ND23 ND25 PD02 SA13                       TA02                 5J091 AA01 AA12 AA58 AA59 CA41                       FA20 HA02 HA25 HA29 KA03                       KA05 KA09 KA11 KA23 KA42                       KA47 MA08 MA21 SA13 TA02                 5J092 AA01 AA12 AA58 AA59 CA41                       FA20 HA02 HA25 HA29 KA03                       KA05 KA09 KA11 KA23 KA42                       KA47 MA08 MA21 SA13 TA02                 5J100 AA15 BA06 BB01 BC02 CA23                       CA31 DA06 EA02 FA01 FA02                 5J500 AA01 AA12 AA58 AA59 AC41                       AF20 AH02 AH25 AH29 AK03                       AK05 AK09 AK11 AK23 AK42                       AK47 AM08 AM21 AS13 AT02                       DN01 DN14 DN22 DN23 DN25                       DP02

Claims (7)

[Claims] 1. A low-pass converter that converts a difference voltage between a voltage obtained by attenuating a control voltage applied from the outside by an attenuator and a reference voltage output from a reference voltage generator into a voltage proportional to a thermal voltage. A control voltage generation circuit configured to output through a filter. 2. A differential voltage between a control voltage applied from the outside and a reference voltage output from a reference voltage generator is converted into a current and then converted into a voltage proportional to a thermal voltage, and a low-pass filter is used. A control voltage generation circuit configured to output. 3. A control current generating circuit configured to output the output obtained by the control voltage generating circuit according to claim 1 or 2 in a current state. 4. A low-pass converter that converts a difference voltage between a voltage obtained by attenuating an externally applied control voltage by an attenuator and a reference voltage output from a reference voltage generator into a voltage proportional to a thermal voltage. A control voltage generating method configured to output through a filter. 5. A differential voltage between an externally applied control voltage and a reference voltage output from a reference voltage generator is converted into a current and then converted into a voltage proportional to a thermal voltage, and a low-pass filter is used. A control voltage generation method configured to output. 6. A control current generating method configured to output the output obtained by the control voltage generating circuit according to claim 4 or 5 in a current state. 7. A mobile terminal using the control voltage generation circuit or the control current generation circuit according to claim 1. Description: