JP2003197848A - Semiconductor package and package mount body - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package which is easily aligned on an assembly board and enables easy determination of allocation of outer connection pads and can be mounted with little failure and enables an efficient visual inspection after mounting. <P>SOLUTION: The semiconductor package comprises a tabular package base 2a, surface interconnection patterns 63a, 64a, 65a, and 66a disposed on a first principal surface of the package base 2a, a plurality of outer connection pads 31a and 36a disposed on a second principal surface of the package base 2a, a semiconductor chip 1 mounted on the surface interconnection pattern 65a, molding resin 5a formed on the first principal surface so as to seal the semiconductor chip 1, and a plurality of pad display patterns 51a and 56a disposed on the surface of the molding resin 5a so as to correspond to the outer connection pads 31a and 36a. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small amount and a wide variety of semiconductor packages, and more particularly to a semiconductor package having a high mountability on an assembly substrate.

[0002]

2. Description of the Related Art Conventionally, as a high frequency semiconductor package, leads (external connection pins) 83 as shown in FIG.
Ceramic or resin molded packages with 1-838 have been widely used. As described above, in the package using the leads 831 to 838 for external connection, it is difficult to secure high frequency characteristics in the leads 831 to 838, and it is becoming difficult to cope with high frequency applications.

Therefore, until now, mainly high-speed multi-pin LSIs have been used.
Ball grid array (BGA) and land grid array (LGA) that have been used as chip packages
There is a movement to use a surface mounting package having a structure in which an external connection electrode is formed on the back surface of the package as a high frequency package used in a small mobile device such as a mobile phone.

The BGA package uses solder balls as electrodes for external connection. The LGA package does not have the balls of the BGA package, and electrodes for external connection are formed as lands on the package substrate. In these packages, a mark called an index mark is usually provided at the position of the first pin on the surface of the package in order to show the directionality of the package. Since BGA packages and LGA packages used for LSI are mass-produced in a single standard, even if the external connection pads on the back surface of the package are not visible, the package outline and pin 1 position If the package type is known, the layout of the external connection pad can be uniquely determined.

High-frequency packages used in small portable devices such as mobile phones tend to be in small quantities and in a large variety of products, and their specifications vary, and model changes are frequently made. In particular, special specifications peculiar to high frequencies are often adopted in semiconductor packages for high frequencies such as millimeter wave band and submillimeter wave band.

[0006]

In such a small amount and a large variety of semiconductor packages, the arrangement of external connection pads (external connection pins) differs depending on the product. Therefore, even if an attempt is made to mount a small amount of various types of semiconductor packages having different pin arrangements for each product on the assembly board, the BG
In the case of A type and LGA type, the external connection pad cannot be seen from the surface of the package side. Therefore, BG
There has been a problem that it is extremely difficult to align the A / LGA type small-quantity, large-variety semiconductor packages on the assembly substrate.

In view of the above circumstances, the present invention provides a BGA / LG
It is an object of the present invention to provide a small amount and a wide variety of semiconductor packages that are easy to position on an assembly substrate even when they are A type.

Another object of the present invention is to easily allocate the external connection pads of a small number of various types of semiconductor packages, to suppress the occurrence of mounting mistakes during mounting, and also in the visual inspection after mounting. The purpose of the present invention is to provide a BGA / LGA type package assembly that can improve its efficiency.

[0009]

In order to achieve the above object, the first feature of the present invention is (a) a flat package substrate whose thickness is defined by the first and second main surfaces; ) First
(C) a plurality of external connection pads arranged on the second main surface; (d) a semiconductor chip mounted on the surface wiring pattern; (e) this semiconductor chip is sealed. A resin package formed on the first main surface; and (f) a semiconductor package having a plurality of pad display patterns arranged on the surface of the mold resin in correspondence with the arrangement positions of a plurality of external connection pads. The main point is. Here, the “first main surface” is one main surface (the surface having the largest area or the second largest surface) of the flat plate-shaped package substrate. The “second main surface” is a main surface facing the “first main surface” of the package substrate.
That is, one of the first and second main surfaces is the "surface",
The other defines two opposite faces that are in a relationship that can be interpreted as a "back face".

According to the first aspect of the present invention, BGA / L
Even in the case of a GA type semiconductor package, the position of the plurality of external connection pads arranged on the second main surface can be identified by the pad display pattern arranged on the surface of the mold resin, so that the alignment with the assembly substrate is possible. It will be easy. Further, since the allocation of the external connection pads can be easily determined, it is possible to suppress the occurrence of mounting mistakes during mounting.

In the first feature of the present invention, if the plurality of pad display patterns are made up of a combination of indicators for identifying the function of the external connection pad, the mounting process on the assembly substrate becomes easy. For example, the operator can recognize in advance in the mounting process whether the terminal is a high frequency input / output terminal or a DC terminal, so that the semiconductor package can be mounted so that the overall functions of the semiconductor package can be utilized.

A second feature of the present invention is (a) a flat package substrate whose thickness is defined by the first and second main surfaces;
(B) a surface wiring pattern and a plurality of external connection pads arranged on the second main surface; (c) a semiconductor chip mounted on the surface wiring pattern; (d) this semiconductor chip is sealed,
A molding resin selectively formed on the second main surface so as to expose the plurality of external connection pads; (e) arranged on the first main surface in correspondence with the arrangement positions of the plurality of external connection pads. The gist is that the semiconductor package includes a plurality of pad display patterns.

According to a second feature of the present invention, BGA / L
Even in the case of a GA type semiconductor package, the positions of the plurality of external connection pads arranged on the second main surface can be identified by the pad display pattern arranged on the first main surface. It will be easy. Also,
Since the allocation of the external connection pads can be easily determined, it is possible to suppress the occurrence of mounting errors during mounting.

In the second aspect of the present invention, if the plurality of pad display patterns are made up of a combination of marks for identifying the function of the external connection pads, the mounting process on the assembly substrate becomes easy. For example, the operator can recognize in advance in the mounting process whether the terminal is a high frequency input / output terminal or a DC terminal, so that the semiconductor package can be mounted so that the overall functions of the semiconductor package can be utilized.

A third feature of the present invention is (a) a flat package substrate whose thickness is defined by the first and second main surfaces;
(B) A surface wiring pattern arranged on the first main surface;
(C) A plurality of external connection pads arranged on the second main surface;
(D) A semiconductor chip mounted on the surface wiring pattern;
(E) Mold resin formed on the first main surface so as to seal this semiconductor chip; (F) On the surface of the mold resin, corresponding to the positions of the plurality of external connection pads,
A plurality of pad display patterns arranged; (g) a package mounting body including a plurality of external connection pads and an assembly substrate having a plurality of assembly substrate surface wirings that can be electrically connected to each other To do.

According to the third aspect of the present invention, in the assembly process of mounting the BGA / LGA type semiconductor package on the package mounting body, a plurality of external connections arranged on the back surface (second main surface) of the semiconductor package. Since the position of the pad can be identified by the pad display pattern arranged on the surface of the semiconductor package, that is, the surface of the mold resin, the alignment with the assembly substrate becomes easy. In addition, since it is possible to easily determine the allocation of the external connection pads of a small amount of various types of semiconductor packages, it is possible to minimize the occurrence of mounting errors during mounting, and also to improve the efficiency in visual inspection after mounting. It is possible to provide a package mounting body that can do.

In the third feature of the present invention, if the plurality of pad display patterns are made up of a combination of marks for identifying the function of the external connection pad, the mounting process on the assembly substrate can be facilitated. This is as described in the first feature. Further, it is preferable that the plurality of external connection pads and the plurality of assembly substrate surface wirings are connected to each other by ball-shaped electrodes because the height of the package mounting body can be easily adjusted.

A fourth feature of the present invention is (a) a flat package substrate whose thickness is defined by the first and second main surfaces;
(B) a surface wiring pattern and a plurality of external connection pads arranged on the second main surface; (c) a semiconductor chip mounted on the surface wiring pattern; (d) this semiconductor chip is sealed,
A molding resin selectively formed on the second main surface so as to expose the plurality of external connection pads; (e) arranged on the first main surface in correspondence with the arrangement positions of the plurality of external connection pads. A plurality of pad display patterns; (f) A package mounting body including a plurality of external connection pads and an assembly substrate having a plurality of assembly substrate surface wirings that can be electrically connected to each other.

According to the fourth aspect of the present invention, in the assembly process of the package mounting body, even in the case of a BGA / LGA type semiconductor package, a plurality of external connection pads arranged on the second main surface of the package substrate. The position of
Since the identification can be made by the pad display pattern arranged on the first main surface of the package substrate, the alignment with the assembly substrate becomes easy. Also, since it is possible to easily determine the layout of the external connection pads of a small number of types of semiconductor packages,
It is possible to provide a package mounting body capable of suppressing the occurrence of mounting mistakes during mounting and improving the efficiency thereof even in visual inspection after mounting.

In the fourth feature of the present invention, if the plurality of pad display patterns are made up of a combination of indicators for identifying the function of the external connection pads, the mounting process on the assembly substrate can be facilitated. This is as described in the second feature. Further, it is preferable that the plurality of external connection pads and the plurality of assembly substrate surface wirings are connected to each other by ball-shaped electrodes because the height of the package mounting body can be easily adjusted.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic,
It should be noted that the relationship between the thickness and the plane dimension, the thickness ratio of each layer, and the like are different from the actual ones. Therefore,
Specific thicknesses and dimensions should be determined in consideration of the following description. Also, it is needless to say that the drawings include portions having different dimensional relationships and ratios.

(First Embodiment) As shown in FIG. 1B, a plurality of external connection pads are provided on the back surface (second main surface) of a semiconductor package 201a according to the first embodiment of the present invention. 31a, 32a, 33a, ..., 40a are provided. On the other hand, as shown in FIG. 1A, the plurality of external connection pads 31 are formed on the surface (first main surface) of the mold resin 5a that constitutes the upper surface of the semiconductor package 201a.
a, 32a, 33a, ..., 40a, a plurality of external connection pads 31a, 32a, 33a,
..., a plurality of pad display patterns 51a, 52a, 53a, ..., 60a indicating the existence of 40a are provided. In FIG. 1A, the external connection pads 31a, 32a, 33a, ..., 40a on the back surface (second main surface) are indicated by broken lines. Further, in FIG. 1B, pad display patterns 51a, 52a, 53a, ... On the front surface (first main surface).
..., 60a are indicated by broken lines. External connection pad 31
a, 32a, 33a, ..., 40a and pad display patterns 51a, 52a, 53a ,.
It can be seen that the arrangement of is in a parallel projection relationship. Further, the index mark 50a used also in the conventional semiconductor package is also provided on the surface (first main surface) of the mold resin 5a.

FIG. 2 is a sectional view taken along the line AA of FIG. 1, and surface wiring patterns 63a, 64a, 65 arranged on the first main surface of the package substrate 2 appearing on this section.
a, 66a and external connection pads 31a, 36a arranged on the second main surface of the package substrate 2. The surface wiring pattern 63a and the external connection pad 31a are connected by a via plug 981, and the surface wiring pattern 66a and the external connection pad 36a are connected by a via plug 986. Although not shown, the other external connection pads 32a, 33a, ..., 40a are similarly connected to corresponding surface wirings on the first main surface by using via plugs.

The semiconductor chip 1a is fixed to the surface wiring pattern 65a with a conductive adhesive (Ag paste) 73a. A high-frequency amplifier circuit including two high-frequency transistors is integrated on the semiconductor chip 1a (see FIG. 8B). Furthermore, the first of the package substrate 2
The chip component 4a is made of a conductive adhesive 71a, 72 such as solder or Ag paste so as to extend over the surface wiring pattern 63a and the surface wiring pattern 64a arranged on the main surface.
It is fixed at a. Then, the bonding wire 41
a connects the semiconductor chip 1a and the surface wiring pattern 64a, and the bonding wire 42a connects the semiconductor chip 1a and the surface wiring pattern 66a. The semiconductor chip 1a and the chip component 4a are sealed (molded) with a molding resin 5. Since FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1, on the mold resin 5,
Pad display patterns 51a and 56a are shown. The pad display patterns 51a and 56a are the package substrate 2
It can be seen that they are arranged so as to be aligned with the positions of the external connection pads 31a and 36a on the second main surface.

In the first embodiment, the package substrate 2
For a, for example, a 600 μm thick glass cloth base material epoxy resin copper clad plate (FR-4) can be used. Epoxy resin can be used as the molding resin 5a, and the thickness thereof may be, for example, about 600 μm.

A plurality of external connection pads 31a, 32a, 33a, ... Formed on the lower surface of the semiconductor package 201a.
, 40a are formed on the back surface (second main surface) of the package substrate 2a, and the size thereof is 500 μm square, as can be seen from FIG. 1 (b) and FIG.
Also, the external connection pads 31a, 32a, 33a, ...
The pitch of the arrangement of 40a is 1 mm. A plurality of pad display patterns 51a on the upper surface of the semiconductor package 201a,
52a, 53a, ..., 60a are directly above the plurality of external connection pads 31a, 32a, 33a, .., 40a, and are circular with a diameter of 400 μm in the first embodiment. This is manufactured by applying white ink on the surface of the semiconductor package 201a.

Although omitted in FIGS. 1 and 2,
On the surface of the semiconductor package 201a, the product name and model of the semiconductor package 201a are displayed in white ink. Displaying the product name and model number is also performed on conventional packages.
A plurality of pad display patterns 51a, 52a, 53a, ...
.., 60a, so that a plurality of pad display patterns 51a, 52a, 53a ,.
No special additional steps are required to print on the surface of the semiconductor package 201a. The index mark 50a shown in FIG. 1 (a) may be formed by applying ink, and is manufactured by processing the surface of the mold resin 5a into a concave shape, as in the conventional package. Is also good.

3 and 4 are a plan view showing a state in which the semiconductor package 201a as described above is mounted on the assembly substrate 8 and a cross-sectional view along the AA direction. As shown in FIG. 3, a plurality of external connection pads 31a, 32a, 33a, ..., 40 on the lower surface of the semiconductor package 201a.
Although a cannot be viewed directly, a plurality of pad display patterns 51a, 52a, formed on the upper surface of the semiconductor package 201a,
53a, ..., 60a, the signal lines 91 and 96 on the assembly substrate 8 and the assembly substrate surface wiring 9
The alignment of the end portions of 2, 93, ..., 100 can be easily performed. Assembly board surface wiring 92, 9
, ..., 100 are connected to pins 102, 103, .., 110 penetrating the side walls of the assembly substrate 8, respectively. In the sectional view shown in FIG. 4, the external connection pads 31a and 36a are electrically connected to the signal lines 91 and 96 with a conductive adhesive such as solder.

The semiconductor package 201a according to the first embodiment shown in FIG. 4 has a plurality of external connection pads 3 having external connection electrodes provided on the lower surface of the semiconductor package 201a.
Since it is composed of only 1a, 32a, 33a, ..., 40a, it is an LGA type semiconductor package 201a.
However, as shown in FIG. 5, a plurality of external connection pads 3
1a, 32a, 33a, ..., 40a and signal line 91,
It is also possible to connect the surface wiring of the assembly substrate such as 96 to each other by ball-shaped electrodes 581 ,. With the configuration shown in FIG. 5, the height of the package mounting body can be easily adjusted.

Also in the BGA type package mounting body shown in FIG. 5, a plurality of external connection pads 31a, 32a, 33a, ... Arranged on the back surface (second main surface) of the semiconductor package 201a in the assembly process.・ 、 40
Since the position of a can be identified by the pad display patterns 51a, 52a, 53a, ..., 60a arranged on the surface of the semiconductor package 201a, that is, the surface of the mold resin 5a, the alignment with the assembly substrate 8 can be performed. It will be easy. Also, external connection pads 31a, 32a, 33a, ...
Since it is possible to easily determine the allocation, it is possible to suppress the occurrence of a mounting error at the time of mounting, and it is possible to improve the efficiency in a visual inspection after mounting.

Referring to FIGS. 6 and 7, the semiconductor package 201a according to the first embodiment shown in FIGS.
The manufacturing method of will be described.

[0032] (a) First, as a package substrate 2, a thickness of 600 .mu.m, 100 mm ^□ degree of copper on both sides (Cu)
Glass cloth-based epoxy resin copper-clad board with foil (FR-
4) is prepared. Then, as shown in FIG. 6A, the surface wiring pattern 63 is formed on the first main surface of the package substrate 2.
a, 64a, 65a, 66a; 63b, 64b, 65
b, 66b; 63c, 64c, 65c, 66c;
To form. Further, external connection pads 31a, 36a; 31b, 36b; 31 are formed on the second main surface of the package substrate 2.
c, 36c ;. Surface wiring pattern 63
a, 64a, 65a, 66a is a 10 mm ^□ extent in the region of the first main surface of the package substrate 2 is formed as a first package pattern. Surface wiring pattern 63b, 6
4b, 65b, 66b have similar 10 mm ^{squares at} positions adjacent to the first package pattern on the first main surface.
It is formed as a repeating pattern (second package pattern) arranged in a certain area. Surface wiring pattern 63
Similarly, c, 64c, 65c, 66c are formed as a repeating pattern (third package pattern) at a position adjacent to the second package pattern on the first main surface. On the other hand, the external connection pads 31a and 36a on the second main surface of the package substrate 2 are patterned using a double-sided mask aligning device so as to be positioned corresponding to the first package pattern on the first main surface. At this time, the double-sided mask aligning device uses the second package pattern on the first main surface,
External connection pads 31b and 36b and external connection pads 31c and 36c are provided at positions corresponding to the second package pattern.
Are formed respectively. In addition, drilling processing,
A via hole penetrating the package substrate 2 is formed.
After performing the desmear process in the via hole after the drilling process, plating is performed to form the surface wiring patterns 63a and 66a;
63b, 66b; 63c, 66c; ... and corresponding external connection pads 31a, 36a; 31b, 36b; 31
Via plugs (not shown) for connecting c, 36c, ... To each other are embedded in the via holes.

(B) Next, as shown in FIG. 6B, the surface wiring pattern 65 on the first main surface of the package substrate 2
The semiconductor chips 1a, 1b, 1c, ... Are fixed to the respective a, 65b, 65c, ... With a conductive adhesive (Ag paste) 73a. Furthermore, the surface wiring pattern 6
The chip component 4a is mounted with conductive adhesives 71a and 72a such as solder or Ag paste so as to extend over 3a and 64a. Further, the chip component 4b is attached to the conductive adhesives 71b, 72 so as to extend over the surface wiring patterns 63b and 64b.
At step b, the chip component 4c is mounted with the conductive adhesives 71c and 72c so as to extend over the surface wiring patterns 63c and 64c. The semiconductor chips 1a, 1b, 1c, ... Are surface wiring patterns 65a, 6 on the first main surface of the package substrate 2.
When fixed to each of 5b, 65c, ..., Bonding wires 41a, 42a; 41b, 42b; 41
Bonding is carried out using c, 42c ..., As shown in FIG. The bonding wire 41a connects the semiconductor chip 1a and the surface wiring pattern 64a,
The bonding wire 42a connects the semiconductor chip 1a and the surface wiring pattern 66a. Bonding wire 4
1b connects the semiconductor chip 1b to the surface wiring pattern 64b, and the bonding wire 42b serves as the semiconductor chip 1b.
And the surface wiring pattern 66b are connected. The bonding wire 41c is used for the semiconductor chip 1c and the surface wiring pattern 6
4c, and the bonding wire 42c connects the semiconductor chip 1c and the surface wiring pattern 66c.

(C) Next, as shown in FIG. 7D, an epoxy resin (molding resin) 5 having a constant thickness of 600 μm is formed on the entire surface of the package substrate 2 excluding the edge of the first main surface. So that the semiconductor chips 1a, 1b, 1c, ...
... and chip parts 4a, 4b, 4c, ... are molded.

(D) Thereafter, the pad display patterns 51a, 56a; 51b, 56b; 51 are formed on the mold resin 5.
c, 56c, ... Are printed by a method such as screen printing. External connection pads 31a, 36a; 31b, 36b; 31c, 36c on the second main surface of the package substrate 2;
Printing is performed with reference to the position of the end portion of the package substrate 2 so as to match the position of. Pad display pattern 51a,
Simultaneously with the printing of 56a; 51b, 56b; 51c, 56c; .., the scribe line (dicing line) may be printed.

(E) Finally, the pad display pattern 56a
, 51b, and between the pad display patterns 56b and 51c, ..., and the semiconductor packages 201a,
Separated into 201b, 201c, .... As described above, dicing may be performed along the scribe line formed by printing.

A semiconductor package 202a according to a modification of the first embodiment shown in FIG. 8A has a plurality of pad display patterns 45a, 52a, 43a, 44a, 55a ,.
46a, 57a, 48a, 49a, 60a are displayed as a plurality of external connection pads 31a, 32a, 33a, ...
The display (sign) is changed according to the role (function) of 40a. In FIG. 8A, description will be made assuming that the semiconductor chip mounted in the semiconductor package is a high-frequency amplifier circuit including two-stage high-frequency transistors Tr1 and Tr2 as shown in FIG. 8B.

In FIG. 8B, the RF input terminal 31
a coupling capacitor C between a and the RF output terminal 36a.
1, a first transistor Tr1, a coupling capacitor C4,
A high-frequency transmission line is formed by the path of the second transistor Tr2 and the coupling capacitor C7. Then, the RF signal is input from the RF input terminal 31a, transmitted through the high frequency transmission line, and output from the RF output terminal 36a. An open stub having an impedance Z _s for adjusting the impedance of the high frequency transmission line is provided between the coupling capacitor C1 and the RF input terminal 31a. First
The source of the transistor Tr1 is grounded, and the gate voltage Vg1 can be supplied to the gate from the DC bias terminal 82 via the bypass capacitor (decoupling capacitor) C2 for separating DC and high frequency and the impedance Z _g. Is configured. The drain of the first transistors Tr1, via a bypass capacitor C3 and the impedance Z _d for separating DC and RF, the drain voltage Vd1 is configured to be supplied from the DC bias terminal 33a. Similarly, the gate voltage Vg2 is supplied from the DC bias terminal 38a to the gate of the second transistor Tr2 via the bypass capacitor C5 and the impedance Z _g, and the drain of the second transistor Tr2 is connected to the bypass capacitor C6. and via an impedance Z _d, the drain voltage Vd2 is configured to be supplied from the DC bias terminal 34a. Second transistor Tr
The source of 2 is grounded. In this way, the high frequency signal input from the RF input terminal 31a is coupled to the coupling capacitor C1.
Is input to the first transistor Tr1 through and is amplified here. The amplified high frequency signal is a coupling capacitor C
4 is input to the second transistor Tr2, is amplified here, and is output to the outside from the RF output terminal 36a through the coupling capacitor C7. Also, in FIG. 8 (b), Z
₀ indicates an impedance component composed of wiring or the like.

In FIG. 8A, a display pattern 4 showing the input / output pads 31a and 36a for the high frequency (RF) signal.
A display pattern 48 showing the marks 5a and 46a in a "black triangle" and the pads 38a and 39a for gate terminals.
a, 49a are marked with "x", and drain terminals 33a, 3a
The display pattern 43a, 44a indicating 4a is marked with "+"
In addition, the signs of the display patterns 52a, 55a, 57a, 60a showing the ground terminals 32a, 35a, 37a, 40a are "black circles".

Pad display patterns 45a, 5 consisting of a combination of markers for identifying functions as shown in FIG. 8 (a).
2a, 43a, 44a, 55a, 46a, 57a, 48
By adopting a, 49a and 60a, the alignment with the assembly substrate 8 is facilitated and the plurality of external connection pads 31a, 32a of the semiconductor package 202a,
The assignment of 33a, ..., 40a can be easily understood.
As a result, it is possible to reduce the occurrence of mounting mistakes when mounting on the assembly substrate 8, and it is possible to improve the efficiency in visual inspection after mounting on the assembly substrate 8.

As shown in FIG. 9, a plurality of external connection pads 4 arranged in almost two rows are formed on the back surface (lower surface) of the semiconductor package 203 according to the modification of the first embodiment of the present invention.
11-416, 421-426, 431, 436, 44
1 to 446 and 451 to 456 are provided. on the other hand,
As shown in FIG. 9, the plurality of external connection pads 411 to 416, 421 to 426, 431, 43 are formed on the surface of the mold resin 5a forming the upper surface of the semiconductor package 203.
6, 441 to 446, 451 to 456, a plurality of external connection pads 411 to 416, 421 to
426, 431, 436, 441-446, 451-4
A plurality of pad display patterns 311 to 3 indicating the presence of 56
16, 321-326, 331, 336, 341-34
6,351-356 are provided. In FIG. 9, external connection pads 411-416, 421-426, 4 on the back surface
31, 436, 441 to 446, 451 to 456 are indicated by broken lines. External connection pads 411-416, 421
~ 426, 431, 436, 441-446, 451-
456 arrangement and pad display patterns 311 to 316,
321 to 326, 331, 336, 341 to 346, 3
It can be seen that the arrangements of 51 to 356 have a parallel projection relationship.

(Second Embodiment) As shown in FIG. 10B, the semiconductor package 204 according to the second embodiment of the present invention has a lower surface (second main surface) of the package substrate 3.
Has a plurality of ball-shaped electrodes 11, 12, 1 for external connection.
3, ..., 16, ..., 20 are provided. Then, as shown in FIG. 10A, a plurality of ball-shaped electrodes 11, 1 are formed on the upper surface (first main surface) of the package substrate 3.
2, 13, ..., 16, ..., 20, a plurality of ball-shaped electrodes 11, 12, 13 ,.
A plurality of pad display patterns 51, 52, 53, ..., 60 indicating the presence of 16 ,. An index mark 50, which is also used in the conventional semiconductor package, is also provided.

FIG. 11 is a cross-sectional view taken along the direction AA of FIG. 10, showing surface wirings 611, 612, 613, 614 arranged on the second main surface of the package substrate 3.
As shown in FIG. 11, ball-shaped electrodes 11, 12, 13,
The mold resin 6 is formed on the same surface as the lower surface (second main surface) of the package substrate 3 on which 20 is formed. Since it is a cross-sectional view along the direction AA of FIG. 10,
The external connection pad 60 is formed on the second main surface of the package substrate 3.
The cross section of 1,606 is exposed. The semiconductor chip 1 is attached to the surface wiring 612 by a conductive adhesive (Ag paste) 673.
It is fixed at. The semiconductor chip 1 shown in FIG.
A high frequency amplifier circuit including two high frequency transistors similar to that shown in FIG. 8B is integrated. Further, the chip component 4 is fixed with conductive adhesives 671 and 672 such as solder or Ag paste so as to straddle the surface wiring 613 and the surface wiring 614 arranged on the second main surface of the package substrate 3. The bonding wire 41 connects the semiconductor chip 1 and the surface wiring 613, and the bonding wire 42 connects the semiconductor chip 1 and the surface wiring 611. The semiconductor chip 1 and the chip component 4 are sealed (molded) with a mold resin 6. Figure 11
10 is a sectional view taken along the line AA of FIG. 10, the pad display pattern 5 is formed on the first main surface of the package substrate 3.
1, 56 are shown. Pad display patterns 51, 5
It can be seen that 6 is arranged so as to be aligned with the positions of the external connection pads 601 and 606 on the second main surface of the package substrate 3.

Although not shown in FIG. 10B, referring to FIG. 11, a plurality of external connection pads 601 and 6 are provided on the lower surface (second main surface) of the package substrate 3.
02, 603, ..., 606, .. are provided at positions behind the ball-shaped electrodes 11, 12, 13 ,. I can understand that. That is, FIG.
As shown in (a), a plurality of external connection pads 601, 602, 6 are provided on the upper surface (first main surface) of the package substrate 3.
03, ..., 606, ....., a plurality of external connection pads 601,602,603, ..
A plurality of pad display patterns 51, 52, 53, ..., 60 indicating the presence of 606 ,.

As the package substrate 3, an alumina ceramic substrate is used and its thickness is 250 μm.
Ball-shaped electrodes 11, 12, 13, ..., 20 have a diameter of 7
00 μm solder balls can be used. Index mark 50, plural pad display patterns 51, 52, 5
3, ..., 60 are the upper surface of the package substrate 3 (first
It was formed with a metal pattern on the main surface).

FIG. 12 is a plan view showing a state in which the semiconductor package 204 as described above is mounted on the assembly substrate 8, and FIG. 13 is a sectional view taken along the line AA of FIG. As shown in FIG. 12, on the first main surface of the assembly substrate 8, the signal lines 91, 96 and the assembly substrate surface wiring 9 are provided.
2, 93, ..., 100 are arranged. As shown in FIG. 13, a ground plate 90 is formed on the second main surface of the assembly substrate 8, and the signal line 9 on the first main surface is formed.
A microstrip line is formed between the microstrip lines 1 and 96. As shown in FIG. 12, the second part of the package substrate 3
A plurality of external connection pads 601, 602, 60 on the main surface
3, ..., 606, ... cannot be directly viewed from the first main surface side. However, a plurality of pad display patterns 51, 52, 53, ... Formed on the first main surface of the package substrate 3
.., 60 to see the signal line 9 on the assembly substrate 8.
1, 96, assembly substrate surface wiring 92, 93, ...
.., external connection pads 601, 60 to the end of 100
The positions of 2, 603, ..., 606 ,. In the cross-sectional view shown in FIG. 13, the external connection pads 601 and 606 are the ball-shaped electrodes 11 and 16 respectively.
Shows the state of being connected to the signal lines 91 and 96. Further, as shown in FIG. 13, the package height after mounting on the assembly substrate 8 can be suppressed low.

The semiconductor package according to the modification of the second embodiment shown in FIG. 14 has a plurality of pad display patterns 4.
5,52,753,754,55,46,57,75
8, 759 and 60 are displayed differently depending on the role of the plurality of external connection pads 31, 32, 33 ,. In FIG. 14 as well, the semiconductor chip mounted in the semiconductor package is the two-stage high frequency transistor Tr shown in FIG. 8B described in the first embodiment.
Description will be made assuming that the circuit is a high frequency amplifier circuit composed of 1 and Tr2. In FIG. 14, the display patterns 45 and 46 showing the input / output pads 31 and 36 of the high frequency (RF) signal are “black triangles”, and the pads 38 and 3 for the gate terminals.
The display patterns 758 and 759 indicating "9" are set to "G", and the display patterns 753 and 754 indicating the drain terminals 33 and 34 are set.
Is "D" and the display patterns 52, 55, 57, 60 showing the ground terminals 32, 35, 37, 40 are "black circles". Pad display pattern 4 as shown in FIG.
5,52,753,754,55,46,57,75
By adopting 8, 759 and 60, the signal lines 91 and 96 on the assembly substrate 8 and the assembly substrate surface wiring 9
2, 93, ..., 100 can be easily aligned with the ends, and a plurality of external connection pads 31, 32, 33 ,. Understandable As a result, it is possible to suppress the occurrence of mounting errors when mounting a small amount of a large variety of semiconductor packages on the assembly substrate 8, and to improve the efficiency of the visual inspection after mounting on the assembly substrate 8. it can.

(Other Embodiments) As described above, the present invention has been described by the first and second embodiments.
The discussion and drawings forming a part of this disclosure should not be understood as limiting the invention.

Particularly, in the first and second embodiments, the description has been given by taking the high frequency semiconductor package of the microwave band, the millimeter wave band, the submillimeter wave band, etc. as an example. It should be noted that the package mounting body using this is not limited. INDUSTRIAL APPLICABILITY The technical idea of the present invention can be applied to various types of small-quantity, high-mixture semiconductor packages in which external connection pads are laid out differently. For example, even in the case of an LSI package, the present invention will be effective at the stage of trial manufacture, pilot products, etc., where the layout specifications of the external connection pads have not yet been determined.

As described above, from the disclosure of the present invention, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the scope of claims appropriate from the above description.

[0051]

According to the present invention, even in the BGA / LGA type, it is possible to provide a small quantity and a large variety of semiconductor packages that can be easily aligned with the assembly substrate.

According to the present invention, it is possible to easily determine the allocation of the external connection pads of a small amount of various types of semiconductor packages, so that it is possible to suppress the occurrence of mounting mistakes during mounting and to perform visual inspection after mounting. Also in the case, it is possible to provide a package mounting body that can improve the efficiency.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor package according to the first embodiment of the present invention.

FIG. 3 is a plan view of a package mounting body according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a package mounting body according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a package mounting body according to a modification of the first exemplary embodiment of the present invention.

FIG. 6 is a process sectional view explaining the manufacturing process of the semiconductor package according to the first embodiment of the present invention (No. 1).

FIG. 7 is a process sectional view explaining the manufacturing process of the semiconductor package according to the first embodiment of the present invention (No. 2).

FIG. 8A is a plan view of a semiconductor package according to a modification of the first embodiment of the present invention, and FIG.
FIG. 9 is an equivalent circuit diagram of a semiconductor integrated circuit mounted on the semiconductor package of FIG.

FIG. 9 is a plan view of a semiconductor package according to another modification of the first embodiment of the present invention.

FIG. 10 is a plan view of a semiconductor package according to a modification of the second embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor package according to a second embodiment of the present invention.

FIG. 12 is a plan view of a package mounting body according to a second embodiment of the present invention.

FIG. 13 is a cross-sectional view of a package mounting body according to a second embodiment of the present invention.

FIG. 14 is a plan view of a package mounting body according to a modification of the second embodiment of the present invention.

FIG. 15 is a plan view of a conventional semiconductor package.

[Explanation of reference numerals] 1a, 1b, 1c Semiconductor chips 2, 2a, 3 Package substrates 4a, 4b, 4c Chip components 5a, 5, 6 Mold resin 8 Assembly substrates 11-20, 581, 586 Ball-shaped electrodes 31a-40a; 31b, 36b; 31c, 36c, 4
11-416, 421-426, 431, 436, 44
1-446, 451-456, 601, 606 External connection pads 41a, 42a; 41, 42; 41b, 42b; 41
c, 42c Bonding wires 43a to 46a, 48a, 49a, 51a to 60a, 5
1-60, 311-316, 321-326, 331
336, 341-346, 351-356, 753, 7
54, 758, 759 Pad display patterns 50, 50a Index marks 63a-66a, 63b-66b, 63c-66c, 6
11-614 surface wiring 71a, 72a, 73a, 671, 672, 673 conductive adhesive 90 ground plate 91, 96 signal line 92-100 assembly substrate surface wiring 102-110 pins 201a, 201b, 201c semiconductor package 981, 986 via plug

Claims (6)

[Claims] 1. A flat plate-shaped package substrate whose thickness is defined by the first and second main surfaces, a surface wiring pattern arranged on the first main surface, and a plurality of surface wiring patterns arranged on the second main surface. External connection pads, a semiconductor chip mounted on the surface wiring pattern, a mold resin formed on the first main surface so as to seal the semiconductor chip, and 2. A semiconductor package comprising a plurality of pad display patterns arranged corresponding to the arrangement positions of the external connection pads. 2. A flat package substrate having a thickness defined by first and second main surfaces, a surface wiring pattern and a plurality of external connection pads arranged on the second main surface, and the surface wiring pattern. A semiconductor chip mounted on the first main surface, a molding resin selectively formed on the second main surface so as to seal the semiconductor chip and expose the plurality of external connection pads. And a plurality of pad display patterns arranged corresponding to the arrangement positions of the plurality of external connection pads. 3. The semiconductor package according to claim 1, wherein the plurality of pad display patterns are made up of a combination of markers for identifying the function of the external connection pad. 4. A flat plate-shaped package substrate having a thickness defined by the first and second main surfaces, a surface wiring pattern arranged on the first main surface, and a plurality of surface wiring patterns arranged on the second main surface. External connection pads, a semiconductor chip mounted on the surface wiring pattern, a mold resin formed on the first main surface so as to seal the semiconductor chip, and A plurality of pad display patterns arranged corresponding to the arrangement positions of the external connection pads, and an assembly substrate having a plurality of assembly substrate surface wirings electrically connectable with the plurality of external connection pads, respectively. A package mounting body comprising: 5. A flat plate-shaped package substrate whose thickness is defined by the first and second main surfaces, a surface wiring pattern and a plurality of external connection pads arranged on the second main surface, and the surface wiring pattern. A semiconductor chip mounted on the first main surface, a molding resin selectively formed on the second main surface so as to seal the semiconductor chip and expose the plurality of external connection pads. A plurality of pad display patterns arranged corresponding to the arrangement positions of the plurality of external connection pads, and a plurality of assembly substrate surface wirings that can be electrically connected to the plurality of external connection pads on the surface. A package mounting body comprising an assembly substrate. 6. The package mounting body according to claim 4, wherein the plurality of external connection pads and the plurality of assembly substrate surface wirings are connected to each other by ball-shaped electrodes.