JP2003197634A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily obtain a body contact while reducing the magnitude of parasitic resistance on a source side and suppressing the change of a pinch-off point. <P>SOLUTION: A P<SP>-</SP>type impurity layer 7 for threshold value control is formed only near to the source side of the channel region while an N<SP>-</SP>impurity layer 6 is formed only on a drain side. Furthermore, the N<SP>-</SP>impurity layer 6 and an N<SP>+</SP>impurity layer 10 are formed so as to reach an insulating layer 1, and the P<SP>-</SP>type impurity layer 7 and N<SP>+</SP>impurity layer 8 are formed so as to be separated from the insulating layer 1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an SOI (Silicon O
It is suitable for application to a semiconductor device using an n Insulator) substrate.

[0002]

2. Description of the Related Art Some conventional MOS transistors use an SOI substrate in order to achieve high speed and low power consumption. FIG. 9 is a cross-sectional view showing the configuration of a MOS transistor formed on a conventional SOI substrate. In FIG. 9, a P ⁻ -type single crystal silicon layer 22 is formed on the insulating layer 21.
Are formed.

Here, in order to increase the speed and power consumption of the MOS transistor, the P ^-- type single crystal silicon layer 22 is thinned and set to a thickness of 100 nm, for example. Also, P ^- type on the single crystal silicon layer 22, a gate electrode 24 is formed via a gate insulating film 23, the sidewall 26 is formed in a side wall of the gate electrode 24, P ^- type single crystal silicon In the layer 22, P ⁻ -type impurities for controlling the threshold value are introduced into the entire channel region.

Here, the gate insulating film 23 can be formed of, for example, a silicon oxide film, and the gate electrode 24 can be formed of, for example, polycrystalline silicon. In addition, N ⁻ impurity layers 25a and 25b are formed on the P ⁻ type single crystal silicon layer 22 with the gate electrode 24 interposed therebetween, and a sidewall 26 is provided outside the N ⁻ impurity layers 25a and 25b. N ⁺ impurity layers 27a and 27b are formed so as to be sandwiched therebetween.

Here, the N ⁻ impurity layers 25a and 25b are L
The DD region can be formed, and the N ⁺ impurity layer 27a,
27b can respectively configure the source / drain of the MOS transistor. Here, N ⁻ impurity layer 2
5a, 25b and the depths of the N ⁺ impurity layers 27a, 27b are set to the insulating layer 2 in order to reduce the junction capacitance and increase the speed.
It is set to reach 1.

Further, the N ⁺ impurity layer 27a and the gate electrode 2
Titanium salicides 28a, 28b and 28c are formed on the 4 and N ⁺ impurity layers 27b to reduce parasitic resistance.

[0007]

However, in the MOS transistor of FIG. 9, in order to suppress the generation of hot carriers, N ⁻ impurity layers 25a and 25b are formed on both the source / drain, and a large parasitic on the source side. Resistance R
Is formed. Here, this parasitic resistance R is several KΩ / S
It has a size of about QUARE (sq) and the gate electrode 2
An RC delay circuit is formed in series with the capacitance of the gate insulating film 23 between the P ^- type single crystal silicon layer 4 and the P ⁻ -type single crystal silicon layer 22.

Therefore, in the conventional MOS transistor, there is a problem that the higher the speed of operation, the greater the influence of the parasitic resistance R, which is an obstacle to the high speed operation. Further, due to the voltage drop of the parasitic resistance R, the effective gate-source voltage Vgs also decreases. Therefore, the conventional M
In the OS transistor, the transconductance gm and the cutoff frequency fc (= gm /
There is a problem in that the amplification factor of the analog amplifier circuit deteriorates due to the decrease of 2π · Cgs).

In particular, this problem becomes more remarkable as the thickness of the P ^-- type single crystal silicon layer 22 is reduced in order to increase the speed and power consumption of the MOS transistor. When operating the MOS transistor in analog, M
Since the OS transistor is used in the saturation region, the pinch-off point PC is formed in the channel. Here, in the P ⁻ -type single crystal silicon layer 22, since P ⁻ -type impurities for controlling the threshold value are introduced into the entire channel region, the entire channel region has a high concentration, and the pinch-off point PC is near the drain. Occurs in.

Therefore, in the conventional MOS transistor, when the AC signal in the analog operation is output to the drain, the pinch-off point PC also changes with this AC signal, and the output signal leaks from the drain to the source. There is a problem that the amplification factor of the amplifier circuit decreases. Furthermore, in the MOS transistor using the SOI structure, in order to reduce the junction capacitance and increase the speed, the N ⁻ impurity layer 2 is used.
5a, 25b and N ⁺ impurity layers 27a, 27b are in contact with the insulating layer 21.

As a result, the body made of the P ^-- type single crystal silicon layer 22 is completely isolated, and due to the substrate floating effect,
Hot carriers (holes) generated at the drain end accumulate in the body, and the body potential fluctuates. For this reason, in the conventional MOS transistor using the SOI structure, there is a problem that the variation of the pinch-off point PC becomes more significant and analog operation in the SOI structure becomes difficult.

On the other hand, if the existing body contact technique is used to fix the potential of the body, there are problems that the structure of the MOS transistor is complicated and the chip size is increased. Therefore, a first object of the present invention is to provide a semiconductor device capable of reducing the magnitude of parasitic resistance on the source side while relaxing the electric field on the drain side, and a manufacturing method thereof.

A second object of the present invention is to provide a semiconductor device and a method of manufacturing the same capable of suppressing the fluctuation of the pinch-off point while enabling threshold control. A third object of the present invention is to provide a semiconductor device capable of easily realizing a body contact while reducing the junction capacitance on the drain side, and a manufacturing method thereof.

[0014]

In order to solve the above-mentioned problems, the semiconductor device according to claim 1 is characterized in that the LDD region is provided only on the drain side of the MOS transistor. This makes it possible to reduce the size of the parasitic resistance on the source side and reduce the effective gate-source voltage drop.

Therefore, it is possible to suppress a decrease in the transconductance of the MOS transistor, suppress a decrease in the cutoff frequency, and suppress a deterioration in the amplification factor of the analog amplifier circuit. According to a second aspect of the semiconductor device, the threshold controlling impurity is introduced only into the channel region near the source side of the MOS transistor.

As a result, the impurity concentration of the channel region near the drain side of the MOS transistor is lowered, and M
The pinch-off point formed in the channel region of the OS transistor can be kept away from the drain. Therefore, it is possible to suppress the fluctuation of the pinch-off point at the time of analog operation, suppress the leak of the output signal, and suppress the deterioration of the amplification factor of the analog amplifier circuit.

According to another aspect of the semiconductor device of the present invention, the source-side impurity layer of the MOS transistor formed on the SOI substrate is separated from the insulating layer of the SOI substrate, and the drain-side impurity layer is formed. Reach the insulating layer. Thereby, the MOS formed on the SOI substrate through the semiconductor layer under the source
The body contact of the transistor can be easily made, and the substrate floating effect can be reduced without complicating the structure.

Further, it is possible to reduce the junction capacitance by reducing the PN junction region on the drain side, and it is possible to achieve high speed and low power consumption of the MOS transistor. According to the semiconductor device of claim 4, a first conductive type semiconductor layer provided on the insulating layer, and a gate electrode formed on the first conductive type semiconductor layer via a gate insulating film, A sidewall formed on the sidewall of the gate electrode, an LDD region formed in the first conductive type semiconductor layer corresponding to the drain side sidewall, and a first conductive type semiconductor layer formed through the LDD region. It is characterized by comprising a formed second conductivity type drain layer and a second conductivity type source layer formed below the source side sidewall and formed in the first conductivity type semiconductor layer.

As a result, the LDD region can be provided only on the drain side, and the magnitude of the parasitic resistance on the source side can be reduced while relaxing the electric field on the drain side, so that an effective gate-source connection can be achieved. It is possible to reduce the voltage drop. Therefore, it is possible to suppress the decrease in the transconductance of the MOS transistor, suppress the decrease in the cutoff frequency, and suppress the deterioration in the amplification factor of the analog amplifier circuit.

According to another aspect of the semiconductor device of the present invention, the depth of the second conductivity type drain layer is set to reach the insulating layer, and the depth of the second conductivity type source layer is the depth. It is characterized in that it is set so as not to reach the insulating layer. As a result, the junction capacitance on the drain side can be reduced to speed up the MOS transistor and reduce the power consumption, and hot carriers generated at the drain end can be externalized via the semiconductor layer below the source. It becomes possible to escape, and it is possible to suppress the accumulation of hot carriers in the body and suppress the occurrence of kinks.

Further, by arranging the second-conductivity-type source layer to be separated from the insulating layer, it becomes possible to form the escape route for carriers accumulated in the body in the vertical direction only by adjusting the implantation energy of impurities. It is possible to realize body contact while suppressing an increase in chip size and the number of steps. According to a sixth aspect of the semiconductor device of the present invention, the semiconductor device further comprises a threshold controlling impurity layer formed only in the channel region near the source side.

As a result, it becomes possible to reduce the impurity concentration of the channel region near the drain side of the MOS transistor and to move the pinch-off point away from the drain while controlling the threshold value of the MOS transistor, thereby preventing the output signal from leaking. It is possible to suppress the deterioration of the amplification factor of the analog amplifier circuit. The semiconductor device according to claim 7, further comprising a first-conductivity-type high-concentration impurity layer formed outside the second-conductivity-type source layer and in contact with the first-conductivity-type semiconductor layer. And

Thus, the body contact can be easily made only by forming the first-conductivity-type high-concentration impurity layer outside the source layer, and the substrate floating effect can be reduced without complicating the structure. It becomes possible. Also,
According to the method of manufacturing a semiconductor device according to claim 8, a step of forming a first-conductivity-type low-concentration semiconductor layer on an insulating layer; and a step of forming a gate electrode on the first-conductivity-type semiconductor layer via a gate insulating film. Forming step, forming a first photoresist film on the source side so as to cover the gate electrode, and using the gate electrode and the first photoresist film as a mask, a second conductivity type low concentration impurity Forming a layer on the drain side of the gate electrode, removing the first photoresist film, and forming a second photoresist film on the drain side so as to cover the gate electrode; Forming a second conductivity type high concentration impurity layer separated from the insulating layer on the source side of the gate electrode by using the gate electrode and the second photoresist film as a mask; Forming a threshold adjustment first conductivity type impurity layer in the channel region near the source by obliquely implanting ions using the gate electrode and the second photoresist film as a mask; Removing the resist film, forming a sidewall on the side wall of the gate electrode, forming a third photoresist film on the source side so as to cover the gate electrode, the gate electrode, Using the sidewall and the third photoresist film as a mask,
Forming a second conductivity type high concentration impurity layer reaching the insulating layer on the drain side of the gate electrode; removing the third photoresist film; the gate electrode, the sidewall and the second Forming a fourth photoresist film on the conductivity type high concentration impurity layer;
Forming a first conductivity type high-concentration semi-impurity layer in contact with the first conductivity type low-concentration semiconductor layer using the photoresist film as a mask.

Thus, by repeatedly using the photolithography technique and the ion implantation technique, the LDD region can be provided only on the drain side, and the impurity layer on the drain side is brought into contact with the insulating layer of the SOI substrate. It becomes possible to separate the impurity layer on the source side from the insulating layer of the SOI substrate and further to introduce the threshold controlling impurity only into the channel region near the source side of the MOS transistor. For this reason, it is possible to suppress the fluctuation of the pinch-off point while reducing the magnitude of the parasitic resistance on the source side, and it is possible to easily realize the body contact, which is formed on the SOI substrate. M
It is possible to easily improve the characteristics of the OS transistor.

Further, it is possible to separate the second-conductivity-type high-concentration impurity layer from the insulating layer only by adjusting the implantation energy of the second-conductivity-type high-concentration impurity, so that the escape route of the carriers accumulated in the body can be lengthened. Since it can be formed in the same direction, the body contact can be easily realized while suppressing an increase in chip size and the number of steps.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below by taking a MOS transistor formed on an SOI substrate as an example.
FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. In Figure 1, on the insulating layer 1 is P ^-
A type single crystal silicon layer 2 is formed, and a field oxide film 3 for element isolation is formed on the P ^-- type single crystal silicon layer 2.

Here, the thickness of the P ^-- type single crystal silicon layer 2 can be set to 100 nm, for example. The SOI structure is SOS (Silicon O
n Saphire) substrate, a SIMOX substrate, a bonded substrate, or the like can be used. A gate electrode 5 is formed on the P ⁻ -type single crystal silicon layer 2 with a gate insulating film 4 interposed therebetween, and a sidewall 9 is formed on the side wall of the gate electrode 5.

Here, the gate insulating film 4 can be formed of, for example, a silicon oxide film, and the gate electrode 5 can be formed of, for example, polycrystalline silicon. The thickness of the gate insulating film 4 can be set to, for example, 7 nm, the gate length of the gate electrode 5 can be set to, for example, 0.35 μm, and the length of each sidewall 9 can be set to, for example, 0.15 μm. In addition, P ^-
In the type single crystal silicon layer 2, the N ⁻ impurity layer 6 is formed only on the drain side corresponding to the position of the sidewall 9, and the P ⁻ type impurity layer 7 for controlling the threshold value is formed in the channel region of the source. It is formed only near the side.

The length of the P ^-- type impurity layer 7 can be set to 0.1 μm, and the channel length can be set to 0.2 μm, for example. Here, the N ⁻ impurity layer 6 can form an LDD region, and by providing the LDD region only on the drain side, the electric field on the drain side can be relaxed and the generation of hot carriers can be suppressed. At the same time, it is possible to reduce the parasitic resistance on the source side.

Therefore, the effective voltage drop between the gate and the source can be reduced, the reduction of the mutual conductance of the MOS transistor can be suppressed, and the reduction of the cutoff frequency can be suppressed. It is possible to suppress deterioration of the amplification factor of the analog amplifier circuit. Further, by forming the P ⁻ -type impurity layer 7 for controlling the threshold value only near the source side of the channel region, the impurity concentration near the drain side of the channel region is lowered,
The position of the pinch-off point PC can be brought closer to the source side.

Therefore, it is possible to suppress the fluctuation of the pinch-off point PC during the analog operation, suppress the leak of the output signal, and suppress the deterioration of the amplification factor of the analog amplifier circuit. Also, P ^- -type source side of the single crystal silicon layer 2, N ⁺ impurity layer 8 extends to the end of the gate electrode 5 beyond the side walls 9 of the source side is formed, P ^- -type single On the drain side in the crystalline silicon layer 2,
N ⁺ impurity layer 1 through the sidewall 9 on the drain side
0 is formed.

Here, the N ⁺ impurity layer 8 can form the source of the MOS transistor, and the N ⁺ impurity layer 1
0 can form the drain of the MOS transistor. As a result, the impurity concentration below the source-side sidewall 9 can be increased, the source-side parasitic resistance can be reduced, and a decrease in mutual conductance can be suppressed.

Further, the N ⁻ impurity layer 6 and the N ⁺ impurity layer 1
The depth of 0 is set so as to reach the insulating layer 1, and P ⁻
The depths of the impurity layer 7 and the N ⁺ impurity layer 8 are set apart from the insulating layer 1. For example, the depth of the N ⁻ impurity layer 6 and the N ⁺ impurity layer 10 is set to 100 nm, and the depth of the P ⁻ impurity layer 7 and the N ⁺ impurity layer 8 is 50 nm.
can be set to nm.

As a result, carriers accumulated in the body can be discharged to the outside through the P ^-- type single crystal silicon layer 2 under the N ⁺ impurity layer 8 while suppressing an increase in drain junction capacitance. It is possible to reduce the floating effect on the substrate. Therefore, it is possible to realize the stabilization of the analog operation in the SOI structure while increasing the speed and power consumption of the MOS transistor. Further, by preventing the P ⁻ impurity layer 7 and the N ⁺ impurity layer 8 from coming into contact with the insulating layer 1, the escape route for carriers accumulated in the body is formed in the vertical direction only by adjusting the implantation energy of the impurities. This makes it possible to realize body contact while suppressing an increase in chip size and the number of steps.

A P ⁺ impurity layer 11 reaching the insulating layer 1 is formed outside the N ⁺ impurity layer 8. The titanium salicide 12 is formed on the P ⁺ impurity layer 11, the N ⁺ impurity layer 8, the gate electrode 5 and the N ⁺ impurity layer 10.
a, 12b, 12c are formed, titanium salicide 12
Aluminum contact layers 13a and 13b on a and 12c
Are formed respectively.

As a result, the P ⁺ impurity layer 11 and the N ⁺ impurity layer 8 are suppressed while suppressing the complexity of the structure of the MOS transistor.
Can be maintained at the same potential, and the lead wire for the body contact can be easily formed. 2 to 7 are cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment of the present invention. In FIG. 2, a single crystal silicon film is formed on the insulating layer 1 by an epitaxial growth method or the like. Then, by ion-implanting P-type impurities into the whole single crystal silicon film at a low concentration,
A P ^-- type single crystal silicon layer 2 is formed.

Here, the thickness of the P ^-- type single crystal silicon layer 2 can be set to 100 nm, for example. Further, as P-type impurities of the P ^-- type single crystal silicon layer 2,
For example, BF ²⁺ can be used. The ion implantation conditions are, for example, energy of 35 keV,
The dose amount can be set to 1E12. As the insulating layer 1, a sapphire substrate, a glass substrate, a buried oxide film, or the like can be used.

Next, the field oxide film 3 for element isolation is selectively formed by the LOCOS method or the like. Next, an oxide film is formed on the P ^-- type single crystal silicon layer 2 by thermal oxidation or the like, and a polycrystalline silicon film doped with an N type impurity is formed by plasma CVD or the like. And photolithography technology and RIE
By using the anisotropic etching technique such as, P ^-
The oxide film and the polycrystalline silicon film formed on the type single crystal silicon layer 2 are patterned to form the gate insulating film 4 and the gate electrode 5.

Here, the gate insulating film 4 has a thickness of, for example, 7 nm, and the gate electrode 5 has a thickness of, for example, 200 n.
m, the gate length of the gate electrode 5 is, for example, 0.35 μm
Can be set to. Next, by a photolithography technique, a photoresist film PR1 is formed so as to cover the gate electrode 5 and cover the source side.
Then, using the photoresist film PR1 and the gate electrode 5 as a mask, ion implantation IP1 is performed on the P ^-- type single crystal silicon layer 2 to form the N ^-- impurity layer 6 on the drain side of the gate electrode 5 in a self-aligned manner. To do.

The depth of the N ^- impurity layer 6 is equal to that of the insulating film 1.
It is preferable to set so as to reach. For example, phosphorus can be used as the N-type impurity used for the ion implantation IP1, and the energy of the ion implantation IP1 can be set to 35 keV and the dose amount can be set to 1E12. As a result, the N ⁻ impurity layer 6 can reach the insulating film 1 and the junction capacitance due to the N ⁻ impurity layer 6 can be reduced.

Next, as shown in FIG. 3, the photoresist film PR1 is removed and the photolithography technique is used to remove the photoresist film PR1.
A photoresist film PR2 is formed so as to cover the drain side and the region where the P ⁺ impurity layer 11 of FIG. 5 is formed so as to cover the gate electrode 5. Then, by ion-implanting IP2 into the P ^-- type single crystal silicon layer 2 from an oblique direction using the photoresist film PR2 and the gate electrode 5 as a mask, the P ^-- impurity layer 7 is formed only under the gate electrode 5 near the source side. To form.

For example, BF ²⁺ is used as the P-type impurity used in the ion implantation IP2, and the energy of the ion implantation IP2 is 40 keV and the dose is 1.6E1.
3. The tilt angle can be set to 30 degrees. As a result, for example, the P ⁻ impurity layer 7 can be formed so as to extend inward by 0.1 μm from the end of the gate electrode 5, the impurity concentration in the vicinity of the drain side of the channel can be suppressed low, and the drain of the channel can be reduced. It is possible to increase the resistance on the side.

Therefore, the depletion layer on the drain side can be widened, and the pinch-off point PC can be moved away from the drain. Therefore, it is difficult for voltage fluctuations to be transmitted to the pinch-off point PC, and the amplification factor of the analog circuit can be reduced. Can be suppressed. Furthermore, these photoresist film PR2 and the gate electrode 5 as a mask, P ^-
By performing ion implantation IP3 on the type single crystal silicon layer 2, the N ⁺ impurity layer 8 is formed on the source side of the gate electrode 5 in a self-aligned manner.

As a result, the end of the N ⁺ impurity layer 8 can be aligned with the end of the gate electrode 5, a high resistance layer is prevented from being formed between the source and the gate electrode 5, and the source side is prevented. The parasitic resistance can be reduced to about several tens Ω / SQUARE (sq). Therefore, while suppressing the RC delay due to the parasitic resistance on the source side, the effective gate-
It is also possible to suppress a decrease in the source-to-source voltage Vgs, suppress a decrease in the transconductance gm and the cutoff frequency fc of the MOS transistor, and realize a high-speed operation.

Here, the depth of the N ⁺ impurity layer 8 is set so as not to reach the insulating film 1, and for example, the depth is preferably about half the thickness of the P ^-- type single crystal silicon layer 2. For example, as N-type impurities used for ion implantation IP3, As
^{Using +} , as the conditions of the ion implantation IP3, for example, the energy can be set to 20 keV and the dose amount can be set to 2.0E15. As a result, the depth of the N ⁺ impurity layer 8 is equal to the thickness of the P ⁻ -type single crystal silicon layer 2 (for example, 100
nm) or less.

Then, by the subsequent heat treatment, the depth of the N ⁺ impurity layer 8 can be adjusted to about half the thickness of the P ^-- type single crystal silicon layer 2. Here, by separating the N ⁺ impurity layer 8 from the insulating film 1, the passage of the hole can be formed vertically in the lower portion of the N ⁺ impurity layer 8 only by adjusting the implantation energy of the impurity, and the drain end It is possible to let the hot carriers (holes) generated in step 2 escape to the outside.

Therefore, it is possible to prevent hot carriers generated at the drain end from accumulating in the body,
It is possible to suppress the potential fluctuation of the body and prevent the occurrence of kinks while suppressing an increase in the chip size and the number of manufacturing steps. Next, as shown in FIG. 4, the photoresist film PR2 is removed, and an oxide film is deposited on the entire surface by the CVD method or the like. The thickness of this oxide film is, for example,
It can be set to 250 nm.

Then, by dry etching back of this oxide film by RIE or the like, the gate electrode 5 is formed.
Side walls 9 are formed on the side walls of the. The length of each sidewall 9 can be set to 0.15 μm, for example. Next, by using the same mask as that used for patterning the photoresist film PR1 of FIG. 2, photolithography is performed to cover the source side so as to cover the gate electrode 5 and the photoresist film PR3. To form.

Then, these photoresist films PR
3, by using the gate electrode 5 and the sidewall 9 as a mask, ion implantation IP4 is performed on the P ⁻ -type single crystal silicon layer 2 to form the N ⁺ impurity layer 10 on the drain side of the sidewall 9 in a self-aligned manner. . Here, the depth of the N ⁺ impurity layer 10 is set so as to reach the insulating film 1. For example, As ⁺ is used as the N-type impurity used for the ion implantation IP1, and the conditions of the ion implantation IP1 are, for example, an energy of 40 keV and a dose of 2.0E1.
It can be set to 5.

As a result, the N ⁺ impurity layer 10 is formed into the insulating film 1.
And the drain junction capacitance of the N ⁺ impurity layer 10 can be reduced. Next, as shown in FIG.
The photoresist film PR3 is removed, and a photoresist film PR4 is formed by a photolithography technique so that the formation region of the P ⁺ impurity layer 11 is exposed and the other regions are covered. Then, this photoresist film PR
Ion implantation IP5 is performed on the P ⁻ -type single crystal silicon layer 2 using 4 as a mask to form the P ⁺ impurity layer 11 outside the N ⁺ impurity layer 8.

For example, BF ²⁺ may be used as the P-type impurity used for the ion implantation IP5, and the energy of the ion implantation IP5 may be set to 40 keV and the dose amount may be set to 2E15. As a result, the P ⁺ impurity layer 11 can be formed in the P ⁻ -type single crystal silicon layer 2, and the carriers accumulated in the body can be discharged to the outside through the P ⁺ impurity layer 11.

In the case of CMOS, P channel MOS
A source / drain forming pattern of a transistor, and N
A single mask may also serve as the pattern for forming the P ⁺ impurity layer 11 of the channel MOS transistor, whereby the number of steps can be reduced. Next, as shown in FIG. 6, the photoresist film PR4 is removed, and titanium is deposited on the entire surface by sputtering or the like. Then, by heat treatment to react titanium with silicon, titanium salicides 12a, 12b, 12c are formed on the P ⁺ impurity layer 11, the N ⁺ impurity layer 8, the gate electrode 5 and the N ⁺ impurity layer 10, respectively. Unreacted residual titanium is removed.

The thickness of titanium is, for example, 70 nm.
Can be set to. Also, titanium salicide 12
As the heat treatment for forming a, 12b, and 12c, for example, two-stage RTP (Rapid) at 650 ° C. and 900 ° C.
Thermal Processes) can be used. Here, titanium salicide 12a, 12b, 12
By forming c, it becomes possible to reduce the parasitic resistance of the P ⁺ impurity layer 11, the N ⁺ impurity layer 8, the gate electrode 5 and the N ⁺ impurity layer 10 without increasing the chip size, and at the same time, P ⁺ Impurity layer 11 and N ⁺ impurity layer 8
Can be electrically connected to each other to keep the P ⁺ impurity layer 11 and the N ⁺ impurity layer 8 at the same potential.

Next, as shown in FIG. 7, an interlayer insulating film is formed by the atmospheric pressure CVD method or the like. Note that, for example, a BPSG film is used as the interlayer insulating film, and the thickness of the interlayer insulating film can be set to 600 nm, for example. Then, by heat treatment, the interlayer insulating film is reflowed, and the profile of the impurities implanted in the P ^-- type single crystal silicon layer 2 is adjusted and activated. Where N ⁺
It is preferable to set the heat treatment conditions so that the depth of the impurity layer 8 is about half the thickness of the P ⁻ -type single crystal silicon layer 2.

For example, as the heat treatment performed here, 95
RTP at 0 ° C. for 1 minute can be used. Next, contact holes are formed in the interlayer insulating film, and aluminum contact layers 13a, 13 are formed on the titanium salicides 12a, 12c.
b is formed. FIG. 8 is a diagram showing operating characteristics of the semiconductor device according to the embodiment of the present invention in comparison with a conventional example. The horizontal axis of FIG. 8 is the drain voltage Vd of the MOS transistor, and the vertical axis is the drain current Id of the MOS transistor.
Indicates.

In FIG. 8, the conventional MOS transistor of FIG. 9 has a pinch-off point PC when used in the saturation region.
Occurs near the drain, and a channel modulation effect due to fluctuations in the pinch-off point PC occurs at point B, as shown in. Further, when the drain voltage Vd is increased, hot carriers are generated at the drain end, the hot carriers are accumulated in the body, and the potential of the body fluctuates, so that a kink due to the substrate floating effect occurs at point C.

On the other hand, in the MOS transistor of FIG. 1, the P ⁻ -type impurity layer 7 for threshold control is formed only near the source side of the channel region, and the channel region near the drain has a high resistance. The pinch-off point PC can be kept away from the drain. Therefore, it is possible to suppress the fluctuation of the pinch-off point PC during analog operation and reduce the channel modulation effect at the point B.

In the MOS transistor of FIG. 1, the source N ⁺ impurity layer 8 is formed so as to be separated from the insulating layer 1, and the P ⁻ type single crystal silicon layer 22 under the source N ⁺ impurity layer 8 is interposed, The carrier accumulated in the body can be discharged to the outside. Therefore, it is possible to reduce the substrate floating effect peculiar to the SOI structure and suppress the generation of kinks at the point C. As a result, Vd of the MOS transistor
The -Id characteristic can be improved from the characteristic to the characteristic.

Further, in the MOS transistor of FIG.
The LDD N ^- impurity layer 6 is formed only on the drain side,
The parasitic resistance on the source side can be reduced. Therefore, the effective reduction of the gate-source voltage Vgs can be suppressed, and the Vd-Id characteristic of the MOS transistor can be increased by A, and the characteristic can be improved from the characteristic. In this way, the N ⁻ impurity layer 6 for LDD is formed only on the drain side, and the P − for threshold control is formed.
^{The −} type impurity layer 7 is formed only near the source side of the channel region, and the N ⁺ impurity layer 10 for drain is formed as the insulating layer 1.
And the source N ⁺ impurity layer 8 is formed so as to be separated from the insulating layer 1.
Even when it is formed on the OI substrate, it is possible to speed up the MOS transistor and reduce the power consumption while suppressing the characteristic deterioration of the MOS transistor, and it is also possible to stably operate the MOS transistor.

In the above-described embodiment, the N-channel MOS transistor is described as an example, but it may be applied to a P-channel MOS transistor, or may be applied to CMOS, for example. Further, although the enhancement type MOS transistor is described as an example in the above-described embodiment, it may be applied to a depletion type MOS transistor. Furthermore, in the embodiment described above,
Regarding the method of forming the N ⁻ impurity layer 6 for LDD only on the drain side and the method of forming the P ⁻ type impurity layer 7 for threshold control only near the source side of the channel region, MO
Although the configuration in which the S transistor is formed on the SOI substrate has been described as an example, it may be applied to the configuration in which the MOS transistor is formed on the semiconductor substrate.

[0061]

As described above, according to the present invention,
By providing the LDD region only on the drain side, it is possible to reduce the magnitude of the parasitic resistance on the source side while relaxing the electric field on the drain side, and to suppress the reduction of the mutual conductance of the MOS transistor and to reduce the cutoff frequency. It is possible to suppress the deterioration of the analog amplifier circuit and the deterioration of the amplification factor of the analog amplifier circuit.

Further, only the impurity layer on the drain side is SOI
By contacting the insulating layer of the substrate, while reducing the junction capacitance on the drain side, through the semiconductor layer under the source,
The carriers accumulated in the body can be released to the outside, the floating effect of the substrate can be reduced, and the speed and power consumption of the MOS transistor can be increased. Further, by introducing the threshold control impurities only into the channel region near the source side of the MOS transistor, the pinch-off point formed in the channel region of the MOS transistor can be moved away from the drain, and the pinch-off during analog operation can be achieved. It is possible to suppress the fluctuation of the points and suppress the deterioration of the amplification factor of the analog amplifier circuit.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a diagram showing operating characteristics of a semiconductor device according to an embodiment of the present invention in comparison with a conventional example.

FIG. 9 is a cross-sectional view showing a structure of a MOS transistor formed on a conventional SOI substrate.

[Explanation of symbols]

1 insulating layer 2 P ^- type single crystal silicon layer 3 a field oxide film 4 gate insulating film 5 gate electrode 6 N ^- impurity layer 7 P ^- impurity layers 8, 10 N ⁺ impurity layer 9 sidewall 11 P ⁺ impurity layer 12a, 12b, 12c Titanium salicide 13a, 13b Aluminum contact layers IP1 to IP5 Ion implantation PR1 to PR4 Photoresist PC Pinch off point

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F110 AA01 AA08 AA09 AA15 BB04                       CC02 DD02 DD04 DD05 EE09                       EE32 EE45 FF02 FF23 GG02                       GG12 GG25 GG28 GG32 GG37                       GG42 GG52 HJ01 HJ06 HJ13                       HJ23 HK05 HK33 HK40 HL03                       HM12 HM15 NN04 NN22 NN35                       NN40 NN62 NN66 QQ11

Claims (8)

[Claims] 1. A semiconductor device in which an LDD region is provided only on the drain side of a MOS transistor. 2. A semiconductor device in which a threshold control impurity is introduced only into a channel region near the source side of a MOS transistor. 3. The impurity layer on the source side of the MOS transistor formed on the SOI substrate is separated from the insulating layer of the SOI substrate, and the impurity layer on the drain side reaches the insulating layer. Semiconductor device. 4. A first conductive type semiconductor layer provided on an insulating layer, a gate electrode formed on the first conductive type semiconductor layer via a gate insulating film, and formed on a sidewall of the gate electrode. Side wall, an LDD region formed in the first conductive type semiconductor layer corresponding to the drain side sidewall, and a second conductive type drain formed in the first conductive type semiconductor layer via the LDD region. A semiconductor device comprising: a layer; and a second-conductivity-type source layer that is formed on the first-conductivity-type semiconductor layer and extends below the source-side sidewall. 5. The depth of the second conductivity type drain layer is set so as to reach the insulating layer, and the depth of the second conductivity type source layer is set so as not to reach the insulating layer. The semiconductor device according to claim 4, wherein: 6. The semiconductor device according to claim 4, further comprising a threshold controlling impurity layer formed only in the channel region near the source side. 7. The method according to claim 4, further comprising a first-conductivity-type high-concentration impurity layer formed outside the second-conductivity-type source layer and contacting the first-conductivity-type semiconductor layer.
7. The semiconductor device according to claim 6. 8. A step of forming a first-conductivity-type low-concentration semiconductor layer on an insulating layer; a step of forming a gate electrode on the first-conductivity-type semiconductor layer via a gate insulating film; So that the first on the source side
Forming a photoresist film, forming a second conductivity type low concentration impurity layer on the drain side of the gate electrode using the gate electrode and the first photoresist film as a mask, and the first photoresist film And a step of forming a second photoresist film on the drain side so as to cover the gate electrode, and a step of separating the insulating layer with the gate electrode and the second photoresist film as a mask. A second conductivity type high-concentration impurity layer on the source side of the gate electrode, and ion implantation is performed obliquely using the gate electrode and the second photoresist film as a mask to form a channel near the source. A step of forming a first conductivity type impurity layer for adjusting a threshold value in the region, a step of removing the second photoresist film, Forming a side wall on the side wall of the gate electrode, and forming a third side wall on the source side so as to cover the gate electrode.
A step of forming a photoresist film, and using the gate electrode, the sidewall and the third photoresist film as a mask, forming a second conductivity type high concentration impurity layer reaching the insulating layer on the drain side of the gate electrode And a step of removing the third photoresist film, a step of forming a fourth photoresist film on the gate electrode, the sidewall, and the second-conductivity-type high-concentration impurity layer; And a step of forming a first-conductivity-type high-concentration semi-impurity layer that is in contact with the first-conductivity-type low-concentration semiconductor layer, using the resist film as a mask.