JP2003196803A - Distortion detecting circuit, distortion correcting circuit, bias adjusting circuit and signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce costs, size and power consumption, to improve performance stability, to conduct highly precise distortion detection and to conduct learning by random signals by employing a digital distortion detecting circuit. <P>SOLUTION: An interpolation process is conducted by an interpolating circuit 13 for digital reproduced data obtained by sampling the reproduced signals obtained through an MR head 2 by an ADC 16 to generate high magnification sampling reproduced data. Distortion detection is conducted by a distortion detecting circuit 14 for the high magnification sampling reproduced data. Based on the detected output by the circuit 14, a bias current of the head 2 is optimized by a bias current setting circuit 19 and a distortion correcting processing is conducted for the reproduced data by a distortion correcting circuit 12. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distortion detecting circuit, a distortion correcting circuit, a bias adjusting circuit and a signal processing circuit applied to a reproducing apparatus for reproducing magnetic recording data by an MR (Magneto-Resistive) head.

[0002]

2. Description of the Related Art Hard disk drive
In iver: HDD), an MR (Magneto-Resistive) head is used to reproduce magnetically recorded data. In the MR head, data reproduction is performed by utilizing the principle that the resistance value changes due to the change in magnetic flux. M
There is a current bias voltage sense method as a data reproducing method using the R head.
This is a method for reproducing recorded data by applying a current to the MR head, generating a voltage in the head, and detecting a change in the resistance value of the MR head according to the recorded data as a change in the head voltage. is there.

A high-sensitivity head called an MR head largely contributes to the increase in capacity of HDDs.

However, since the MR head has a non-linear input magnetic field-output voltage characteristic, the reproduction waveform is distorted as shown in FIG. 37 unless it is used at an appropriate operating point. It is the bias current that determines the operating point of the MR head.
The input / output characteristics can be regarded as a straight line if the operating point is near the center of the.

When the reproduced signal waveform is distorted, the error rate deteriorates. The reason is that when a partial response channel, which is a high recording density technology, is used, the reproduced waveform is as shown in FIG.
This is because the detection point distribution has three values such as +1, 0, -1, and if the waveform is distorted, the eye height has different waveforms on the plus side and the minus side. The partial response channel is the PR shown in FIG.
There are many other than Type 1.

In order to solve such a problem, the bias current is optimized and shipped in the manufacturing process of the device.

FIG. 39 is a block diagram showing a configuration example of the recording / reproducing circuit 200 of the HDD.

In the recording / reproducing circuit 200, the recording system 210 records the recording data on the hard disk 220 by supplying the recording data to the recording head 212 via the recording amplifier 211.

The reproducing system 230 is equipped with an MR head 231 for reproducing the data recorded on the hard disk 220, from the hard disk 220 to the MR head 2.
The reproduction RF signal obtained by 31 is amplified by the reproduction amplifier 232 and supplied to the equalization circuit 233. Regenerative amplifier 2
The reference numeral 33 has a function of applying a desired bias current to the MR head 231 and a voltage amplification function. The equalization circuit 233 determines the transfer function of the electromagnetic conversion channel to have a desired characteristic (PR1 or P1).
R4) etc.

From the output signal of the equalizing circuit 233 to the PLL
The detection timing is generated by the circuit 234, and the analog / digital converter (AD
C: analog-to-digital converter) 235 samples the detection point voltage of the output signal of the equalization circuit 233.

Then, the reproduction signal discrimination circuit 236 binarizes the reproduction RF signal sampled by the ADC 235 to obtain reproduction data equal to the recording data.

Here, as shown in FIGS. 40 (A) and 40 (B), in an apparatus such as an HDD in which the disk 311 and the MR head 312 do not slide, if they continue to be used at the operating point at the time of factory shipment. Can be expected.

On the other hand, there is a device such as a tape streamer in which a tape and a head slide. The tape streamer has a fixed head 3 as shown in FIGS. 41 (A) and (B).
21. A fixed head type for recording / reproducing data via a magnetic tape 322 by a rotary drum 33 provided with a magnetic head 331 as shown in FIGS. 42 (A) and 42 (B).
2 and a fixed drum 333 can be classified into a helical scan type that records / reproduces data via a magnetic tape 335 wound around a rotary drum device 334.

The MR head used in the helical scan type tape streamer has a size of 0.1 m in width and 1 mm in length.
Extremely small. Since such an MR head slides on the magnetic tape, it gradually wears. In the initial state, the MR head 4 having the size Wo as shown in FIG.
When 01 is worn by sliding contact with the magnetic tape 402, the cross-sectional area of the MR head 401 becomes small as shown in FIG. Then, the input magnetic field-reproduction output voltage characteristic changes, and the bias current density increases in inverse proportion to the MR element cross-sectional area. As a result, as shown in FIG. 44, as if the bias current is excessive. The operating point shifts. Therefore, the waveform of the reproduction signal obtained from the MR head 401 via the reproduction amplifier 403 is distorted.

As described above, the MR head has the following problems: 1) Optimization of bias current 2) Distortion of reproduced waveform, which is good in sensitivity but difficult to use.

These are not only tape streamers,
HDDs are also a problem, and various measures are being taken.

For example, in Japanese Patent Laid-Open No. 5-159209, a bias setting circuit that receives an asymmetric signal such as the output of an MR head and the output of the bias setting circuit are processed to nonlinearly correct the asymmetric signal into a symmetric signal. A correction circuit, a data discriminator that discriminates data from the output of the non-linear correction circuit, and a circuit that feeds back a signal to the bias setting circuit via a feedback circuit including a zero-value error calculator and a low-pass filter are provided. A signal processing device is disclosed.

In this signal processing device, assuming that the detection point voltage at which 0 is detected is V0, V0> 0 asymmetrical, upper collapsed waveform V0 = 0 no asymmetry, upper / lower symmetrical V0 <0 asymmetrical, lower collapsed waveform Distortion is detected based on the principle. The detection result is used to determine whether or not the voltage is 0V.

In the technique disclosed in Japanese Patent Laid-Open No. 5-159209, since the detection output is fed back, there is a problem that it does not operate unless correct detection is performed.

Japanese Patent Laid-Open No. 7-202575 discloses a circuit for shaping a waveform so that the positive and negative amplitudes of an AC analog signal having different positive and negative amplitudes are the same with respect to a reference 0 level. Positive and negative maximum amplitude value detecting means for detecting the positive and negative maximum amplitude values with respect to the 0 level of
Based on the detected value of the positive and negative maximum amplitude value detecting means, a correction amount calculating means for calculating a correction amount for making the amplitude of the analog signal equal to the reference level, and an analog signal according to the correction amount calculated by the correction amount calculating means There is disclosed an analog signal waveform shaping circuit including an amplitude correction means for correcting the amplitude of the.

Further, in Japanese Unexamined Patent Publication No. 7-210807, a signal separating means 1 for separating an analog signal into positive and negative signals with respect to a reference level and an amplitude comparing means for comparing the magnitude of the amplitude of the separated positive and negative signals. A signal correcting means capable of independently amplifying and correcting the amplitudes of the separated positive and negative signals, a signal combining means 4 for combining the corrected positive and negative signals, and a smoothed signal after rectifying the combined analog signal. Of the positive and negative signals to be corrected in the signal correction means from the output of the DC level and the amplitude comparison means. An analog signal waveform shaping circuit including a signal correction value calculation means for calculating a correction value is disclosed.

In the analog signal waveform shaping circuits disclosed in JP-A-7-202575 and JP-A-7-210807, the non-target of the MR head output waveform is controlled by means having a nonlinear input / output response characteristic. to correct. The non-linear means separates the positive part and the negative part of the waveform with a rectifier, amplifies gains independent of positive and negative, and adds them again to obtain an output corrected for non-linearity. That is, it is a non-linear means having a 0V polygonal line characteristic. The distortion detecting means detects the imbalance between the positive peak and the negative peak of the waveform. Make students learn by learning patterns. However, the above-mentioned Japanese Patent Laid-Open No. 7-20257.
In the techniques disclosed in Japanese Patent Laid-Open No. 5 and Japanese Patent Laid-Open No. 7-210807, even if the distorted waveform is rectified, the positive portion and the negative portion cannot be separated with high accuracy. Further, since the learning is performed so that the positive peak and the negative peak of the waveform are equal to each other, the learning can be performed only with the learning pattern of the fixed frequency.

Japanese Unexamined Patent Publication No. 6-44510 discloses a technique relating to adaptive digital linearization of a magnetoresistive head output. In the technique disclosed in Japanese Patent Laid-Open No. 6-44510, a non-symmetrical MR head output waveform is corrected by means having a nonlinear input / output response characteristic. The non-linear means is a memory lookup table, and the lookup table is generated by applying an external magnetic field H to the MR head at the factory.
This is performed by storing the reproduction voltage e characteristic with respect to H in a non-volatile memory. Since the optimum non-linearity is stored at the time of factory shipment, no distortion detecting means is provided. But,
The technique disclosed in Japanese Patent Laid-Open No. 6-44510 cannot deal with a change in the characteristics of the MR head after factory shipment.

Japanese Patent Laid-Open No. 9-69203 discloses a magnetoresistive head that detects a fluctuating magnetic field and generates an analog signal output, which is complementary to the nonlinearity of the resistivity / external magnetic field characteristics of the magnetoresistive head. A magnetic recording / reproducing apparatus is disclosed in which a non-linear amplification section having a non-linear amplification characteristic is provided and the non-linear amplification characteristic of the non-linear amplification section is used to compensate for the non-linearity of the output of the magnetoresistive head. This JP-A-9
In the technology disclosed in Japanese Patent No. 69203, a non-symmetrical MR head output waveform is corrected by means having a nonlinear input / output response characteristic. The non-linear means utilizes the non-linearity of the transistor. The non-linear characteristics are fixed. There is no automatic adjustment (learning) function for the nonlinear amplification unit. Japanese Unexamined Patent Publication No. 10-55504 discloses envelope detection for detecting a positive envelope connecting a positive peak and a negative envelope connecting a negative peak with respect to a reproduction signal obtained from a sense current of an MR head. Section, an asymmetry detection section that detects asymmetry between the positive envelope and the negative envelope detected by the envelope detection section, and the asymmetry detected by this asymmetry detection section falls within a certain range. Disclosed is a reproduction signal waveform control device including a sense current control unit for controlling the sense current of the MR head and a switching circuit for outputting the reproduction signal to either the PRML signal processing unit or the envelope detection unit. Has been done.

In the technique disclosed in Japanese Patent Application Laid-Open No. 10-55504, the sense current of the MR head is optimized and the asymmetry of the output waveform of the MR head is made zero. The distortion detecting means detects the imbalance between the positive envelope and the negative envelope of the waveform. Even if the distorted waveform is rectified, the positive part and the negative part cannot be separated with high accuracy.

In Japanese Patent Laid-Open No. 10-134307, M
The reproduction signal from the MR head is subjected to peak discrimination and amplitude discrimination in order to optimize the sense current flowing through the MR head so that the positive and negative amplitude asymmetry with respect to the reference zero level of the reproduction analog signal of the R head has the same amplitude. The recording signal reproducing section, the waveform asymmetry detecting section for detecting the asymmetry of the positive and negative amplitudes of the waveform and producing the gate signal for controlling the sense current, and the sense current controlling section for setting the sense current value are used to reproduce the MR head. A magnetic disk device is disclosed in which the read margin at the time of data discrimination can be increased and the reliability can be improved by correcting the positive / negative amplitude asymmetry of the signal.

In the technique disclosed in Japanese Patent Laid-Open No. 10-134307, the sense current of the MR head is optimized to
Make the output waveform asymmetry of the head zero. The distortion detecting means detects the difference in pulse width of the reproduction signal. Only the learning pattern of a single frequency signal can be used for learning.

Japanese Unexamined Patent Publication No. 10-320723 discloses that M
A technique is disclosed in which the influence of vertical asymmetry in the R head is suppressed, and it is possible to always slice at a constant slice level in response to changes in the pattern of the reproduced waveform.

In the technique disclosed in Japanese Unexamined Patent Publication No. 10-320723, a learning pattern is created by a learning pattern creating section and written on a recording medium, and an adjustment pattern is reproduced by an MR head. The reproduced adjustment pattern is an AGC circuit, L
The correction voltage detection unit input via the PF, the equalizer, and the coupling capacitor detects and holds the amplitude and the waveform center value of the adjustment pattern from the reproduced waveform, and determines the difference between the positive and negative peak value and the waveform center value. Create a correction voltage. During the actual reproduction of the data, the peak and negative peak values of the reproduced waveform are detected by the peak voltage detector, and the slice level setting unit sets the slice level from the correction voltage and the peak voltage of the reproduced waveform. The level slice section outputs a slice gate signal according to the slice level. However, it can be learned only by a single frequency learning pattern.

In each case, as shown in FIG. 45, the distortion detection circuit 24
The distortion is detected by 2 and fed back to the bias current setting circuit 243, or the distortion correction circuit 241 aims to eliminate distortion.

The problems of the prior art relating to the distortion correction of the MR head are summarized as follows.

L) There is an example of using the detection result, but it is desirable not to use the detection result.

2) It is necessary to be able to detect asymmetry with high accuracy even with a severely distorted waveform, but there are some cases where this is not possible in principle.

3) The user should be able to adjust automatically while using the device.

4) It is desirable to be able to learn with random data, but there are cases where learning is possible only with a specific learning pattern. With such a device, it becomes necessary to suspend the work of the user for learning.

5) In many cases, it is realized by an analog circuit, but there is room for digital circuits other than the bias current setting circuit.

However, most of the MR head distortion correction circuits of the prior art are analog circuits.

[0038]

By the way, when the signal processing in the reproducing apparatus for reproducing the magnetic recording data by the MR head is digitized, the following problems occur.

Although the following description will be made by taking a helical scan type tape streamer as an example, the same applies to an HDD and a linear recording type tape streamer.

The block diagram of FIG. 46 shows an example of the essential structure of a reproducing system in which a bias current automatic adjusting function and a distortion automatic correcting function are added to a helical scan type tape streamer by a conventional technique.

In the reproduction system 500 of the helical scan type tape streamer, the magnetic tape 501 to the MR head 50 are used.
The reproduction RF signal obtained by 2 is amplified by the reproduction amplifier 503, and the equalization circuit 50 is passed through the rotary transformer 504.
5 is supplied. Here, for example, DDS (Digital Data)
Storage) A tape streamer compliant with the 4 standard has partial response class 1 (P
Since R1) is adopted, the transfer characteristic of the equalizing circuit 505 is adjusted so that the transfer characteristic from the recording amplifier of the recording system to the output of the equalizing circuit 505 of the reproducing system is as close as possible to the PR1 transfer characteristic. . Then, the output signal of the equalization circuit 505 is sent to the distortion detection circuit 50 via the distortion correction circuit 506.
7 and the PLL circuit 508 and an analog-to-digital converter (ADC).
509.

The distortion detection circuit 507 is the equalization circuit 50.
Distortion is detected for the output signal of No. 5. Then, based on the detection output signal of the distortion detection circuit 507, the distortion correction circuit 506 performs distortion correction, and the bias current setting circuit 510 also causes the MR head 502.
The bias current is set.

That is, the distortion detection output signal of the distortion detection circuit 507 is supplied to the distortion correction circuit 506 and the bias current setting circuit 510.

The distortion correction circuit 506 is based on the distortion detection output signal of the distortion detection circuit 507 and the equalization circuit 50.
The distortion of the output signal of No. 5 is corrected to eliminate distortion.

The bias current setting circuit 510 also includes a V / F conversion circuit 511 for converting the distortion detection output signal of the distortion detection circuit 507 into a frequency signal, and the V / F conversion circuit 511 and the rotary transformer 512. F / V conversion circuit 5 for converting the supplied frequency signal into a voltage signal
13 and supplies the voltage signal signal obtained by the F / V conversion circuit 513 to the reproduction amplifier 503 as a bias current setting signal, whereby the MR head 502.
Set the bias current of.

Then, the output signal of the equalization circuit 505, which has been distortion-free by the distortion correction circuit 506, is used as the PLL.
The channel clock is extracted by the circuit 508, and the detection point voltage of the output signal of the distortion correction circuit 506 is sampled by the ADC 509 driven by this channel clock.

The sampling data obtained by the ADC 509 is reproduced signal discriminating circuit 5 such as a Viterbi decoder.
It is converted to a binary signal by 30.

As described above, in the helical scan type tape streamer, since the rotary transformer is used for the signal transmission of the rotary drum, in order to adjust the bias current which is a direct current, the V / F conversion circuit 511 → the rotary transformer 512.
The path must be through the −F / V conversion circuit 513 → regeneration amplifier 503. This is a part different from the reproduction system for HDD.

The means for supplying electric power to the circuit on the drum is not shown in FIG. 46 because it is not the subject of discussion.
A method of transmitting AC power by a rotary transformer dedicated to power transmission or DC transmission with a brush has been put into practical use.

Next, FIG. 47 shows a modification of FIG. 46 in which the distortion correction circuit 521 and the distortion detection circuit 522 are digitized and provided in the subsequent stage of the ADC 509.

The bias current setting circuit 510 is composed of a pure analog circuit, and is provided from the distortion detection circuit 522 to a digital-to-analog converter (DAC).
ter) 515 to supply a distortion detection output signal.

In the configuration shown in FIG. 47, the distortion correction circuit 52
Since 1 is in the subsequent stage of the PLL circuit 508, the PLL input signal is distorted, so that the PLL circuit 508 may malfunction. Then, the distortion correction circuit 521 in the subsequent stage of the PLL circuit 508 cannot detect distortion unless the PLL circuit 508 operates normally. That is, too severe distortion cannot be detected.

Further, FIG. 48 shows a structural example in which the drawbacks of the structure shown in FIG. 47 are improved.

In the configuration example shown in FIG. 48, by disposing the digitized PLL circuit 528 after the distortion correction circuit 521 and the distortion detection circuit 522, there is no need to worry about malfunction of the PLL.

However, in order to detect distortion, it is difficult to realize the configuration shown in FIG. 48 because the reproduced waveform must be captured with analog resolution.

Here, FIG. 49 (A) shows a distortion-free PR1 channel output eye pattern, and FIG. 49 (B).
Shows the PR1 channel output eye pattern with distortion in which the positive region of the waveform is crushed. FIG. 50 shows the original waveform of the eye pattern shown in FIG. 49 (B).

In the conventional analog distortion detection circuit 507,
A waveform as shown in FIG. 50 is input, and (1) the positive and negative amplitudes of analog waveforms are compared.

(2) The positive and negative widths of analog waveforms are compared. The distortion was detected by either of the above.

On the other hand, the data input to the digital distortion detection circuit 522 of FIG. 48 is data obtained by asynchronously sampling the waveform as shown in FIG. 51 at a certain cycle.
For example, FIG. 51 shows data sampled at 1.6 times the channel clock frequency. Black dots are sampling voltages. However, in the sparse sampling as shown in FIG. 51, since (1) asynchronous sampling is performed, an accurate peak voltage cannot be captured.

(2) Since the sampling is sparse, an accurate width cannot be captured. However, the digital distortion detection circuit 522 that receives low-magnification asynchronous oversampled data as an input cannot exhibit satisfactory performance.

It suffices to input the high-magnification oversampled data as shown in FIG. 52 to the digital distortion detection circuit 522, but it is difficult to obtain a high-speed ADC having a high frequency of several to several tens of times the channel clock frequency.

Therefore, conventionally, the distortion detection circuit could not be configured by a digital circuit.

Therefore, in view of the conventional situation as described above, an object of the present invention is to employ a digitized distortion detection circuit,
Low cost, downsizing, low power consumption, improved performance stability, high distortion detection accuracy, and learning by random signal, distortion detection circuit, distortion correction circuit, bias adjustment circuit, and signal processing circuit To provide.

[0064]

To detect digital distortion, high-magnification sampling of several times to several tens times the channel clock frequency is required. However, it is very difficult to obtain such a high-distance ADC. In the present invention, it is easy to obtain A
The low-magnification sampled data at DC is digitally interpolated to obtain high-magnification sampling data as shown in FIG.

That is, the distortion detection circuit according to the present invention is
An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by an MR (Magneto-Resistive) head, and a high-magnification sampling reproduction by interpolating the reproduction data digitized by the analog / digital conversion means. It is characterized by comprising an interpolating means for generating data, and a distortion detecting means for detecting distortion by arithmetic processing on the high-magnification sampling reproduction data generated by the interpolating means.

Further, the distortion correction circuit according to the present invention is
(Magneto-Resistive) An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by a head, and a non-linear characteristic variable for performing non-linear processing on the reproduction data digitized by the analog / digital conversion means. Non-linear processing means, interpolation means for performing interpolation processing on the reproduction data subjected to the non-linear processing by the non-linear processing means to generate high-magnification sampling reproduction data, and calculation for the high-magnification sampling reproduction data generated by the interpolation means. Distortion detecting means for detecting distortion by processing, and control means for variably controlling the non-linear characteristic of the non-linear processing means according to the distortion detection output by the distortion detecting means are provided, and the reproduction is automatically corrected for distortion from the non-linear processing means. It is characterized by outputting data.

The bias adjusting circuit according to the present invention is
A bias current supply means capable of variably setting a current value for supplying a bias current supplied to an MR (Magneto-Resistive) head; and an analog / digital conversion means for sampling and digitizing a reproduction signal obtained by the MR head. Interpolation means for interpolating reproduction data digitized by the analog / digital conversion means to generate high-magnification sampling reproduction data, and distortion for high-magnification sampling reproduction data generated by the interpolation means by arithmetic processing And a control means for variably controlling the current value of the bias current supplied to the MR head by the bias current supply means in accordance with the distortion detection output by the distortion detection means. Automatically adjust bias current to minimize signal distortion Characterize that.

Further, the signal processing circuit according to the present invention is
(Magneto-Resistive) An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by a head, and a non-linear characteristic variable for performing non-linear processing on the reproduction data digitized by the analog / digital conversion means. Non-linear processing means, interpolation means for performing interpolation processing on the reproduction data subjected to the non-linear processing by the non-linear processing means to generate high-magnification sampling reproduction data, and calculation for the high-magnification sampling reproduction data generated by the interpolation means. Distortion detecting means for detecting distortion by processing, control means for variably controlling the non-linear characteristic of the non-linear processing means according to the distortion detection output by the distortion detecting means, and reproduction data subjected to non-linear processing by the non-linear processing means Is supplied to the digital phase-locked loop (PLL). ), The detection point voltage is extracted from the reproduction data whose distortion is automatically corrected by the non-linear processing means by the digital / PLL circuit.

Further, the signal processing circuit according to the present invention is M
An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by an R (Magneto-Resistive) head, and a variable non-linear characteristic for performing non-linear processing on reproduction data digitized by the analog / digital conversion means. The non-linear processing means, the interpolation means for performing the interpolation processing on the reproduction data subjected to the non-linear processing by the non-linear processing means to generate the high-magnification sampling reproduction data, and the high-magnification sampling reproduction data generated by the interpolation means. Distortion detecting means for detecting distortion by arithmetic processing, non-linear characteristic control means for variably controlling non-linear characteristics of the non-linear processing means in accordance with the distortion detection output by the distortion detecting means, and bias current to be supplied to the MR head are supplied. Bias current supply means capable of variably setting current value, and the bias described above. Characterized in that it comprises a bias current control means for variably controlled in accordance with the current value of the bias current supplied to the MR head in the distortion detection output of said distortion detecting means by the flow supply means.

[0070]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a reproducing system 100 of a tape streamer to which the present invention is applied.

The reproducing system 100 of this tape streamer is
Reproduction RF obtained by the reproduction head 2 from the magnetic tape 1.
An equalizing circuit 5 in which a signal is amplified by a regenerative amplifier 3 and supplied through a rotary transformer 4, and an analog / digital converter (ADC: Waveform equalized by the equalizing circuit 5 is supplied to a regenerated RF signal). An analog-to-digital converter) 6 is provided.

Here, for example, DDS (Digital Data Sto
rage) 4 standard compliant tape streamer with partial response class 1 (PR) as channel transfer characteristics.
Since 1) is adopted, the transfer characteristic of the equalizing circuit 5 is adjusted so that the transfer characteristic from the recording amplifier of the recording system to the output of the equalizing circuit 5 of the reproducing system becomes as close as possible to the PR1 transfer characteristic. . Then, the ADC 6 outputs the reproduction RF data waveform-equalized by the equalization circuit 5 to the fixed frequency oscillator 7
1-sample 8-bit reproduction RF by sampling with ADC clock given by
Generate data.

Also, the reproducing system 10 of this tape streamer
0 is a distortion correction circuit 12 to which reproduced RF data obtained by digitizing the reproduced RF signal by the ADC 6 is supplied.
And the reproduction R whose distortion is corrected by this distortion correction circuit 12.
Interpolation circuit 13 to which F data is supplied, and this interpolation circuit 13
The automatic distortion correction circuit 8 including the distortion detection circuit 14 to which the interpolated output data is supplied.

The interpolation circuit 13 performs interpolation processing on the reproduction RF data to generate high-magnification sampling reproduction RF data as interpolation output data. Further, the distortion detection circuit 14 detects the distortion of the high-magnification sampling reproduction data generated by the interpolation circuit 13 by a calculation process. Then, the distortion correction circuit 12 performs distortion correction on the reproduction RF data based on the distortion detection output of the distortion detection circuit 14.

That is, in the automatic distortion correction circuit 8 provided in the reproduction system 100 of this tape streamer, the distortion correction circuit 12 makes the reproduced RF data non-distorted based on the distortion detection output of the distortion detection circuit 14. Try.

Also, the reproducing system 10 of this tape streamer
0 is the interpolation circuit 13, the distortion detection circuit 14, and the distortion detection output obtained by the distortion detection circuit 14 is a digital-to-analog converter (DAC).
r) A bias current automatic adjustment circuit 9 including a bias current setting circuit 19 supplied via 15 is provided.

The bias current setting circuit 19 converts the distortion detection output signal, which is analogized and supplied from the distortion detection circuit 14 through the DAC 15, into a frequency signal, and the V / F conversion circuit 16. It is composed of an F / V conversion circuit 18 for converting a frequency signal supplied from the conversion circuit 16 via the rotary transformer 17 into a voltage signal, and the voltage signal obtained by the F / V conversion circuit 18 is used as a bias current setting signal for a regenerative amplifier. The bias current of the MR head 2 is set by supplying the bias current to the MR head 3.

That is, in the bias current automatic adjusting circuit 9 provided in the tape streamer reproducing system 100,
The bias current setting circuit 19 optimizes the current value of the bias current flowing through the MR head 2 based on the distortion detection output of the distortion detection circuit 14. Furthermore, the tape streamer reproducing system 100 is configured to perform the automatic distortion correction. The reproduced RF data that has been rendered undistorted by the circuit 8 is supplied to P
An LL circuit 10 and a reproduction signal discriminating circuit 11 such as a Viterbi decoder driven by a channel clock extracted by the PLL circuit 10 are provided, and the reproduction RF data which has been distorted by the automatic distortion correction circuit 8 is the reproduction signal. The discrimination circuit 11 converts it into a binary signal.

Here, as the interpolation circuit 13, for example, as shown in FIG. 2, a 4 × interpolation circuit 20A and a 4 × linear interpolation circuit using four 16-tap transversal filters LPF0, LPF1, LPF2, LPF3 are used. A 16-fold interpolation circuit configured by combining 20B is used.

The interpolation algorithm is a technique used in audio sampling rate converters.

FIG. 3 shows a configuration example of the quadruple interpolation circuit. The interpolation circuit 20 includes a zero insertion circuit 21 and a low pass filter.
(LPF) 22 and a multiplication circuit 23. This interpolation circuit 2
At 0, the zero insertion circuit 21 causes the input signal sequence x (n)
A four-fold interpolation signal sequence y (m) in which three zeros are inserted is obtained.

For example, an input signal sequence x (n) x (n) = {...,-1,0,1,1, ... On the other hand, as shown by ● in FIG. 4B, a quadruple-interpolation signal sequence y (m) in which three zeros are inserted, that is, y (m) = {...,-1,0 , 0,0,0,1,0,0,0,1,0,0,0, ...} is obtained.

The LPF 22 in the next stage smoothes the 4-fold interpolation signal sequence y (m) obtained by the zero insertion circuit 21.

Then, in the multiplication circuit 23 at the final stage, 3
Since two zeros are inserted and smoothed, the amplitude of the LPF output sequence becomes 1/4 of the original, so this is multiplied by 4 and the input signal sequence x ( An output signal sequence z (m) having the same amplitude as n) is obtained.

In the interpolating circuit 20 having such a configuration, 40 z (m) of 0 ≦ m ≦ 39 for 10 x (n) of 0 ≦ n ≦ 9 are obtained by the above calculation.

To interpolate R times by the interpolation circuit 20, the zero insertion circuit 21 inserts R-1 zeros.

Next, with reference to FIG. 5, a specific example of the interpolation circuit 20 for performing quadruple interpolation will be described.

The interpolation circuit 20 shown in FIG. 5 has a frequency of 150 MHz obtained by dividing the original oscillation signal of 600 MHz oscillated by the fixed frequency oscillator 7 into quarters by the quarter divider.
An 8-bit sample data of 1 sample obtained by digitizing the reproduced RF signal by the ADC 6 which operates by the ADC clock of 3 is supplied as the input signal series x (n).

This three-zero insertion circuit 21 is the same as the above-mentioned 600.
A 2-bit binary counter 211 for counting the original oscillation signal of MHz, a 4-input 1-output data selector 212 controlled by the 2-bit count output of the 2-bit binary counter 211, and an 8-bit data selector 212 An 8-bit latch circuit 213 which latches the output with the 600 MHz original oscillation signal and supplies it to the LPF 22 at the next stage.
Consists of.

A transversal filter is used for the LPF 22. A 2-bit shift circuit is used as the multiplication circuit 23.

In the three-zero insertion circuit 21, the data selector 212 is supplied with the input signal sequence x (n) at the selector input 0, and the selector inputs 1, 2,
3 is given zero, and the selector inputs 0, 1, 2, and 3 are switched in order at the 600 MHz clock, so that as shown in FIG. 6, the data sequence y (m ) Is output.

Next, the interpolation algorithm executed by the interpolation circuit 20 will be described.

The following equation is used to obtain X (w) by Fourier transforming 10 input signal sequences x (n).

[0095]

[Equation 1]

In the interpolating circuit 20 which performs quadruple interpolation, each x (n)
Since three zeros are inserted into, the quadruple interpolation signal sequence y (m) is expressed by the following equation.

[0097]

[Equation 2]

The four-fold interpolation signal sequence y (m) is Fourier transformed by the following equation.

[0099]

[Equation 3]

The internal term of Σ is a non-zero value x (n) only when m = 4n.
Therefore, if y (m) is replaced by x (n) and m is replaced by 4n, 0 ≦ n ≦ 9, the following formula can be obtained.

[0101]

[Equation 4]

Further, it can be rearranged and transformed into the following equation.

[0103]

[Equation 5]

The right side is equal to X (w), and X (w) is as shown in FIG.
As shown in FIG. 7A, since it has a periodic waveform with a period of 10, Y (w) is a frequency spectrum in which X (w) is repeated four times, as shown in FIG. 7B. Of these,
Since the shaded spectrum is an image component obtained by zero interpolation, as shown in FIG. 7C, only the left and right spectrums are left in the LPF that sharply attenuates at ¼ of the Nyquist frequency, and the spectrum shown in FIG. As shown in, the spectrum LPF (w) interpolated by 4 is obtained. Then, as shown in (E) of FIG.
Since it becomes 4, it is multiplied by 4 to obtain Z (w).

The digital transversal filter used in the LPF 32 can use the impulse response obtained by inverse Fourier transforming the desired transfer characteristic as the tap coefficient.

FIG. 8 shows an example of transfer characteristics required for the x4 interpolation filter.

In the transfer characteristic shown in FIG. 8, a point of gain = 0.5 is provided at the boundary between the pass band and the attenuation band so that the zero lobe of the side lobes of the impulse response is swiftly considered. This is because the number of taps should be as short as possible.

FIG. 9 shows a result obtained by truncating the impulse response obtained by the inverse Fourier transform at 64 points.
An LPF can be realized by using this response as a tap coefficient of a 64-tap transversal filter.

Here, as shown in the timing chart of FIG. 6, the data rate of the input signal sequence x (n) is 1
The data rate of the output signal sequence z (m) is 50 MHz and 60
It is 0 MHz. In this way, the data rate becomes R times when the R times interpolation is performed. Although a 150 MHz operating circuit can be easily designed, 600 MHz is difficult.

Therefore, in order to keep the clock frequency at 150 MHz, four 16-tap transversal filters in which every four taps are thinned are used to output the 4-fold interpolation data in parallel. In this way, the same result can be obtained.

That is, FIG. 10A shows 600 MH.
It is the figure which observed the time of LPF which operates by z. x
Since a data series in which three zeros are interpolated is input to (n), three out of four shift registers should be zero. In that case, as shown in FIG. 10B, the product-sum circuit in which zero is input is unnecessary. further,
A correct output can be obtained even in the circuit of FIG. 10C in which the clock frequency is lowered to 150 MHz, the shift register outputting zero is deleted, and x (n) which does not interpolate zero is input.

With the configuration shown in FIG. 10C, the number of taps of the transversal filter is reduced to 4
It is possible to reduce the number of taps by reducing the number of taps to 1/4 by thinning out every other period and keeping the clock frequency at 150 MHz.

In FIG. 10, the coefficients k0, k4, k8, k12 ...
・ I should have left the sum-of-products circuit. But besides this,
Depending on which tap is non-zero, the time of the interpolation output signal is m, and 1) as shown in FIG. 10, when m = 4n, the coefficients k0, k4, k
Pattern in which the product-sum circuit of 8, k12 ... Is non-zero 2) As shown in FIG.
Pattern in which the product-sum circuit of 5, k9, k13, ... Is non-zero 3) As shown in FIG. 12, when m = 4n-2, the coefficients k2, k
The pattern in which the product-sum circuit of 6, k10, k14 ... Is non-zero 4) As shown in FIG. 13, when k = 4n-3, the coefficients k3, k
There are four patterns in which the product-sum circuit of 7, k11, k15, ... Is non-zero.

The 64-tap transversal filter shown in FIG. 10A is expressed by the following product-sum formula.

[0115]

[Equation 6]

1) When m = 4n, y (m-4b) = x (nb), b is an integer, otherwise y = 0.

[0117]

[Equation 7]

The right term is equalization in which x (n) is input to the 16-tap transversal filter shown in FIGS. 10B and 10C in which tap coefficients are thinned out every fourth interval starting from k 0. . 2) When m = 4n + 1, y (m-1-4b) = x (nb), otherwise y = 0.

[0119]

[Equation 8]

The right term is equalization in which x (n) is input to the 16-tap transversal filter shown in (B) and (C) of FIG. 11 in which tap coefficients are thinned out every fourth interval starting from k1. . 3) When m = 4n + 2, y (m-2-4b) = x (nb), otherwise y = 0.

[0121]

[Equation 9]

The right term is equalization of inputting x (n) into the 16-tap transversal filter shown in FIGS. 12 (B) and 12 (C), in which tap coefficients are thinned out every fourth interval starting from k2. . 4) When m = 4n + 3, y (m-3-4b) = x (nb), otherwise y = 0.

[0123]

[Equation 10]

In the right term, the tap coefficient is 4 starting from k3.
This is equivalent to inputting x (n) into the 16-tap transversal filter shown in (B) and (C) of FIG.

Therefore, the transversal filter originally having 64 taps is modified, as shown in FIG. 14, 1) starting from k0, 16 tap transversal filter (LPF0) thinned out every 4 taps, and starting from 4) starting from k1. 16-tap transversal filter (LPF1) thinned out every tap 3) 16-tap transversal filter thinned every 4 taps starting from k2 (LPF2) 4) 16-tap transversal filter thinning every 4 taps starting from k3 (LPF3) 4) 16-tap transversal filters (LPF0, LPF1, LPF2, LPF3) defined in), are driven by the 150MHz clock before interpolation, and x (n) is input, 4 clocks are paralleled in 1 clock. Quadruple interpolation to obtain double interpolation data It may be road 20A.

In the quadruple interpolation circuit 20A, the LPF0 outputs the m = 4n-th interpolation data series lpf (4n),
LP of m = 4n + 1th interpolation data sequence lpf (4n + 1)
Output from F1 and m = 4n + second interpolation data series l
pf (4n + 2) is output from LPF2, and m = 4n + 3rd interpolation data series lpf (4n + 3) is output from LPF3.

The example of the interpolating LPF described above is the quadruple interpolation, but it can be generally expressed as follows.

[0128]

[Table 1]

[0129]

[Table 2]

Since the PR1 channel transfer characteristic becomes zero at 1/2 of the channel frequency, it can be considered that the channel output power is distributed almost all below the Nyquist frequency. Therefore, the reproduction system 100 of the tape streamer shown in FIG.
If the ADC sampling frequency is higher than the channel clock, sampling without aliasing can be performed.

Therefore, in the following description, channel frequency = 100 MHz and ADC sampling frequency = 150 MHz. AD about 1.5 times the channel frequency
With the C clock, the load on the circuit associated with the speedup is small.

High-magnification interpolation is desirable for highly accurate distortion detection. This is because the high-magnification interpolation data series includes sampling data near the detection point.

However, when the above-mentioned interpolation method is expanded to perform interpolation of 8 times or 16 times, the number of taps of the transversal filter increases, which is a problem. The LPF for 4-fold interpolation needs to have a characteristic of sharply attenuating at 1/4 of the Nyquist frequency, and therefore a 64-tap transversal filter is used. However, the LPF for 16-fold interpolation needs to have a characteristic of steeply attenuating at 1/16 of the Nyquist frequency. Such an LPF has poor zero convergence of the side lobes of the impulse response and has a tap number larger than 64 taps. Will be required.

The impulse response of the LPF cut off at 1/4 of the Nyquist frequency is calculated in FIG. 15, and the impulse response of the LPF cut off at 1/16 of the Nyquist frequency is calculated up to a length of 200 points in FIG. As illustrated by the result of the above, the latter has poor side lobe convergence.

Therefore, it is advantageous to implement high-magnification interpolation while preventing an increase in circuit scale by performing low-magnification interpolation using a transversal filter and performing linear interpolation in the subsequent stage. An example of interpolation by the linear interpolation circuit is shown in FIG.

Generally, the following equation is used to obtain Q sample data lin (i) by linearly interpolating between two points a and b.

[0137]

[Equation 11]

When 4 parallel inputs of z (4n), z (4n + 1), z (4n + 2), and z (4n + 3) are performed, they are each linearly interpolated 4 times to 1
To obtain 6 sample data lin (i), do as follows.

Lin (16n) = z (4n-1) + {z (4n) -z (4n-1)} / 4 lin (16n + 1) = z (4n-1) + {z (4n)- z (4n-1)} ÷ 4 × 2 lin (16n + 2) = z (4n-1) + {z (4n) −z (4n-1)} ÷ 4 × 3 lin (16n + 3) = z (4n) lin (16n + 4) = z (4n) + {z (4n + 1) −z (4n)} ÷ 4 lin (16n + 5) = z (4n) + {z (4n + 1) − z (4n)} / 4 × 2 lin (16n + 6) = z (4n) + {z (4n + 1) −z (4n)} / 4 × 3 lin (16n + 7) = z (4n + 1) ) lin (16n + 8) = z (4n + 1) + {z (4n + 2) −z (4n + 1)} ÷ 4 lin (16n + 9) = z (4n + 1) + {z (4n +2) −z (4n + 1)} ÷ 4 × 2 lin (16n + 10) = z (4n + 1) + {z (4n + 2) −z (4n + 1)} ÷ 4 × 3 lin ( 16n + 11) = z (4n + 2) lin (16n + 12) = z (4n + 2) + {z (4n + 3) −z (4n + 2)} / 4 lin (16n + 13) = z (4n + 2) + {z (4n + 3) −z (4n + 2)} ÷ 4 × 2 lin (16n + 14) = z (4n + 2) + {z (4n + 3) −z (4n +2)} ÷ 4 × 3 lin (16n + 15) = z (4n + 3) Here, the multiplication circuit and the division circuit used in the linear interpolation are realized by the shift circuit. Therefore, x2 can be realized by a 1-bit left shift circuit, x4 can be realized by a 2-bit left shift circuit, ÷ 2 can be realized by a 1-bit right shift circuit, and ÷ 4 can be realized by a 2-bit right shift circuit.

The quadruple interpolation circuit 20A using a transversal filter as the interpolation circuit 20 and the quadruple interpolation circuit using linear interpolation have been described above.

The four 16-tap transversal filters LPF0, LPF1, LPF shown in FIG. 14 described above.
By combining the 4 × interpolation circuit 20A and the 4 × linear interpolation circuit 20B using the LPF 3, the 16 × interpolation circuit 13 shown in FIG. 2 can be realized.

Here, an example of the interpolated waveform obtained by calculation will be illustrated below.

PR over-sampled 1.5 times
FIG. 18 shows an example of 1-channel output, FIG. 19 shows an example of a waveform obtained by 16 times interpolation of the PR1-channel output, and FIG. 20 shows the eye pattern thereof. As shown in the eye pattern of FIG. 20, it can be seen that there is a detection point for every 24.

ADC sampling frequency is 150 MHz
Then, the 16-fold interpolation signal corresponds to a 2400 MHz sample signal, and it is extremely difficult to obtain such a high frequency ADC. Moreover, the power consumption also increases almost in proportion to the clock frequency.

Next, the distortion detecting circuit 14 for detecting the distortion of the high-magnification sampling reproduction data generated by the interpolation circuit 13 by the arithmetic processing will be described.

Distortion detection circuit 14 including the interpolation circuit 13
FIG. 21 shows a block configuration of the above. Also, the distortion detection circuit 1
An example of the operation waveform of No. 4 is shown in (A) and (B) of FIG. The distortion detection circuit 14 includes a high-pass filter (HPF) 421 to which the 16 × 8-bit high-magnification sampling reproduction data generated by the 16-fold interpolation circuit 13 is input, and the HPF 4
21. Zero-cross comparator 42 to which high-magnification sampling reproduction high-frequency data from which DC component is removed is input
2 and a low pass filter (LPF) 423 to which the output of the zero cross comparator 422 is supplied.

Here, for example, when the high-magnification sampling reproduction data of the upper collapsed waveform shown in FIG. 52 is input to the HPF 421, the high-magnification sampling reproduction high-frequency data in which the DC component is removed by the HPF 421 is shown in FIG. It becomes like A). The characteristic of the signal waveform shown in FIG. 22A is that the waveform is shifted upward as a whole as compared with the input signal waveform shown in FIG. This is because the area of the lower half is larger than that of the upper half due to the upper crush strain.

The zero-cross comparator 422 is formed by arranging 16 level comparators for comparing an 8-bit input and a 1-bit 0 input, respectively.
Whether the output of 1 is positive or negative is determined, and + 1 / −1 is output as shown in FIG. Here, the output of the zero-cross comparator 422 is the average dut if there is no distortion.
The y ratio = 50%, but if there is distortion, the average duty ratio ≠ 50%.

Whether the distortion is upper crushed or lower crushed can be determined based on whether the output duty ratio of the zero-cross comparator 422 is over 50% or less. The LPF 423 smoothes the output of the zero cross comparator 422. And LPF42
The distortion of the input waveform can be detected by monitoring the F output of No. 3 with the following algorithm.

In the example shown in FIGS. 22A and 22B, the output of the zero-cross comparator 422 has a duty ratio> 50.
%, The output of the LPF 423 is positive, and it is detected that there is upper crush distortion.

LPF output> 0≡duty ratio> 50% ≡upset distortion LPF output = 0≡duty ratio = 50% ≡no distortion LPF output <0≡duty ratio <50% ≡down collapse distortion For example, since it is a full digital circuit, it is possible to reduce cost, reduce size, reduce power consumption, and improve performance stability. Further, since the oversampled data by interpolation is input, the ADC 6 may be of a low speed type, and may not be a learning pattern, and learning by a random signal is possible.

It should be noted that the HPF 421 provided in the subsequent stage of the 16 × interpolation circuit 13 may be replaced with an HPF 421A in the preceding stage of the 16 × interpolation circuit 13 as shown in FIG.

The above-mentioned algorithm uses the dut of the recording signal.
It goes without saying that it is assumed that y is 50% on average. Generally 8/10 for magnetic recording / reproducing devices
Average du due to modulation code such as conversion or 16/20 conversion
There is no problem because the ty is set to 50%.

FIG. 24 shows another form of the distortion detection circuit 14. Further, FIG. 25 shows an operation waveform example of the distortion detection circuit 14.
(A) and (B).

In the distortion detection circuit 14 shown in FIG. 24, the 16 × 8-bit high-magnification sampling reproduction data generated by the 16-fold interpolation circuit 13 is directly input and via the first low-pass filter (LPF1) 425. A level comparator 426 is provided, and the output of this level comparator is the second
A low-pass filter (LPF2) 427 for output as a distortion detection output signal.

In the distortion detection circuit 14, the first LPF 425 outputs D from the 16 × 8-bit high-magnification sampling reproduction data generated by the 16-times interpolation circuit 13.
The C component is extracted. For example, the high-magnification sampling reproduction data of the upper collapsed waveform shown in FIG. 52 is converted into the first LPF 425.
When it is input to, the output of the first LPF 425 is as shown in FIG. Since the upper part of the waveform is crushed, the average voltage is a negative value, so the output of the first LPF 425 is a negative value. Level comparator 426
Compares the input and output of the first LPF 425,
+ 1 / -l is output as shown in FIG. Here, the output of the level comparator 426 has an average duty ratio = 50% if there is no distortion, but if there is distortion, the average duty ratio ≠ 50%. The output duty ratio of the comparator 426 is 5 depending on whether the distortion is upper or lower distortion.
It can be determined whether it is more than 0% or less. The second LPF 427 smoothes the output of the comparator 426. Second LPF
Since the relationship between the output of 427 and the distortion is the same as that described above,
The description is omitted.

The first LPF 425 provided in the subsequent stage of the 16 × interpolation circuit 13 is replaced by A as shown in FIG.
The output of DC6 may be supplied to the comparator 426 via the first LPF 425A.

Next, the configurations of the x16 parallel input type HPF and LPF which use the output of the 16 × interpolation circuit 13 as an input signal will be described.

FIG. 27 shows a data input type I for each clock.
The structure of IR type LPF430 is shown. The IIR LPF 430 of the data input type for each clock 1 has a first coefficient circuit 431 for multiplying the input data by a coefficient (K) and an adder 432 to which the output of the first coefficient circuit 431 is supplied.
And a latch circuit 433 for latching the output of the adder 432 for each clock, and a second coefficient circuit 434 for multiplying the output of the latch circuit 433 by a coefficient (1-K). The output of the second coefficient circuit is added to the output by the adder, and the added output is added to the latch circuit 433.
The LPF output is made via.

In the IIR type LPF 430 of the data input type for every clock, the response speed of the LPF becomes slower when the coefficient K is made smaller and becomes faster when the coefficient K is made larger.

The present invention requires a special LPF into which 16 parallel data are input every clock. An example of the structure is shown in FIG.

The IIR LPF 440 of 16 parallel data input type for every clock shown in FIG. 28 comprises an average value calculation circuit 441 and an IIR LPF 430.

The IIR type LPF 430 is set to 1 every 1 clock.
Since only data can be calculated, the average of all 16 input data is calculated by the average value calculation circuit 441 in the preceding stage, and I
Input to IR type LPF 430. With this configuration, only one output is output for 16 inputs. That is, the LPF used in the present invention is an LPF of a type having a very slow response speed for extracting the DC component of the waveform, and one data output per clock is sufficient to know the DC component.

Next, FIG. 29 shows the configuration of an IIR type HPF 450 of one data input type per clock.

The IIR type HPF 450 of the data input type every clock 1 has an IIR type LPF 430 and a subtractor 451.
Composed of. IIR type LPF430 from input data
The DC component is extracted by the
By subtracting 51 from the input data, the HPF output from which the DC component is removed can be obtained.

As shown in FIG. 30, the 16-per-clock / parallel-data input type HPF 460 used in the present invention is an IIR-type LPF 430 of the 16-per-clock data input type.
And an individual subtraction circuit 46 for obtaining HPF output 0 to HPF output 15 for each of data 0 to data 15.
1A to 461P.

Next, correction of distortion will be described.

In the distortion correction, as shown in FIG. 31, in principle, in the case of the upper collapsed waveform, the inclination of the input / output characteristic with respect to the positive portion of the waveform may be increased to correct the upper collapse. In the case of the under-crushed waveform, the opposite is true, as shown in FIG. That is, it suffices to design a distortion correction circuit 12 that incorporates some non-linear circuit 12B as shown in FIG. 32 and can obtain arbitrary non-linearity according to the characteristic control input voltage as shown in FIG.

Next, the automatic distortion correction circuit 8 corresponding to FIG.
A specific configuration example of the above will be described with reference to FIG.

In the automatic distortion correction circuit 8, the distortion detection circuit 14 generates a positive voltage for an upper collapsed waveform and a negative voltage for a lower collapsed waveform, as described with reference to FIG.

The distortion correction circuit 12 includes a nonlinearity updating section 12
A and a non-linear circuit 12B.

The non-linearity updating section 12A includes the distortion detecting circuit 1
Based on the output of 4, when D _{n + 1} = D _n + ΔD distortion detection circuit output> 0 (upper collapsed waveform case) D _{n + 1} = D _n distortion detection circuit output = 0 (no distortion case) D _{n + 1} = D _n −D The distortion correction amount is updated as in the case _{where the} distortion detection circuit output is less than 0 (the case of the under-crushed waveform), and the distortion correction amount D
_{n + 1 = D n + ΔD} , D n, the _D n _-ΔD selected by the selector switch 463 is adapted to output through the latch circuit 464.

Here, D _n is the n-th distortion correction amount. If the distortion correction amount D _n is 1>, it increases the ADC data (role to correct upper crushing), and if 1 <, it attenuates the ADC data (role to correct lower crushing). ΔD is a unit update amount for sequentially updating the distortion correction amount D _n , and in the specific example shown in FIG. 34, ΔD =
It is 0.01. The distortion correction amount D _{n + 1} is ± ΔD
Are updated by the update circuits 261 and 262 for giving the distortion correction amounts D _{n + 1} = D _n + ΔD, D _n , D _n −ΔD according to the detection output of the distortion detection circuit 14.
It is selected by 63 and output via the latch circuit 264.

The non-linear circuit 12B uses the distortion correction amount D _{n + 1.}
And ADC data are multiplied by a multiplication circuit 266.
A selector switch 268 for selecting the multiplication result when the output of the zero-cross comparator 267 = 1 is provided in order to act D _n only on the positive part of the ADC data.

The frequency of updating the distortion correction amount D _n may be once per one rotation of the drum, or may be 1000 channel clocks or the like if a higher speed response is desired.

In this way, the distortion correction amount D _n gradually changes in the direction in which the distortion is corrected. Distortion correction amount D _n
When the distortion correction circuit 14 reaches the optimum point for distortion correction, the distortion detection circuit 14 has an output of 0, so that the distortion correction amount D _n remains unchanged.

Since the distortion of the MR head 2 can be changed by the bias current, the distortion can be minimized by controlling the bias current by using the distortion detecting circuit 14 described above.

Next, a specific configuration example of the bias current automatic adjustment circuit 9 corresponding to FIG. 1 will be described with reference to FIG.

The bias current automatic adjusting circuit 9 is provided with the bias current updating section 9 to which the output of the distortion detecting circuit 14 is supplied.
Equipped with 0. The bias current updating unit 90 updates the bias current based on the output of the distortion detection circuit 14 as follows.

B _{n + 1} = B _n + ΔB When distortion detection circuit output> 0 (upper collapsed waveform case) B _{n + 1} = B _n distortion detection circuit output = 0 (no distortion case) B _{n + 1} = B _n −ΔB When Distortion Detection Circuit Output <0 (Case of Lower Crushed Waveform) Here, B _n is the nth bias current setting value.

If the distortion detection circuit output> 0, increase the bias current (direction to correct the upper crush) Distortion detection circuit output <0
Then, it works to attenuate the bias current (in the direction to correct the bottom crush). ΔB is a unit update amount for sequentially updating B _n , and in the specific example shown in FIG. 35, ΔB = 1. If the bit width of the input data to the DAC 15 is 8 bits, the bias current can be varied with a resolution of 1/256 if ΔB = 1. Bias current set value B _{n + 1} is ± ΔB
Bias current set value B _{n + 1} = B _n + ΔB, B _n , B _n −ΔB.
Is selected by the selector switch 93 according to the detection output of the distortion detection circuit 14 and is output via the latch circuit 94.

The bias current set value B _n is converted into a voltage by the DAC 15 and supplied to the bias current setting section 19.

The bias current setting section 19 once converts the output voltage of the DAC 15 into V / F by the V / F conversion circuit 16, passes it through the rotary transformer 17 with AC, and converts it into F / V by the F / V conversion circuit 17. To obtain the bias current setting signal. The reproduction amplifier 3 gives a bias current according to the bias current setting signal to the MR head 2.

The update frequency of the bias current setting value B _n may be normally once per one rotation of the drum, or may be 1000 channel clocks or the like if a higher speed response is desired.

In this way, the bias current setting value B _n gradually changes in the direction in which the distortion is corrected. At the time when the bias current setting value B _n reaches the optimum bias,
Since the output of the distortion detection circuit 14 becomes 0, the bias current setting value B _n remains unchanged.

Here, in the case where the distortion automatic correction circuit 8 and the bias current automatic adjustment circuit 9 coexist as shown in FIG. 1, it is possible that the feedback loop malfunctions when both operate simultaneously. This is because it is confused whether the change in distortion is the result of the bias current adjustment or the result of the correction by the nonlinear circuit 12B. Therefore, it is necessary to operate either one exclusively.

In order to reduce the strain to zero, it is preferable to reduce the strain by adjusting the bias current because it is close to the source flow.
After optimizing the bias current, it is preferable to correct the residual distortion with the non-linear circuit 12B.

Therefore, the distortion elimination sequence is shown in FIG.
It is best to optimize the bias current first, and then continue the non-linear correction as shown in FIG.

That is, a system controller (not shown)
First, when the distortion elimination sequence is started,
Distortion correction is stopped in step S1 of
Amount D _nProhibit update of D_n= 0.

In the next step S2, the bias current automatic adjustment is started and the bias current set value B _n can be updated.

In the next step S3, the completion of automatic bias current adjustment is awaited.

In the next step S4, the optimum bias current value determined by the bias current automatic adjustment is held,
The update of the bias current set value B _n is prohibited.

Then, in the next step S5, automatic distortion correction is started, and the distortion correction amount D _n can be updated.

[0194]

As described above, according to the present invention, the distortion detection circuit, the distortion correction circuit, the bias adjustment circuit, and the signal processing circuit can be configured by a full digital circuit, which can reduce the cost, downsize, and reduce the cost. It is possible to provide a distortion detection circuit, a distortion correction circuit, a bias adjustment circuit, and a signal processing circuit, which can reduce power consumption, improve performance stability, and have high distortion detection accuracy and which can perform learning by a random signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a reproduction system of a tape streamer conforming to the DDS4 standard to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a 16 × interpolation circuit configured by combining a 4 × interpolation circuit and a 4 × linear interpolation circuit used as an interpolation circuit in the reproduction system of the tape streamer.

FIG. 3 is a block diagram showing a configuration example of a quadruple interpolation circuit.

FIG. 4 is a diagram schematically showing an operation of quadruple interpolation.

FIG. 5 is a block diagram showing a specific example of a quadruple interpolation circuit.

FIG. 6 is a time chart showing the operation of a three-zero insertion circuit that constitutes the four-fold interpolation circuit.

FIG. 7 is a diagram showing various frequency spectra in a process of quadruple interpolation processing by the quadruple interpolation circuit.

FIG. 8 is a diagram showing an example of transfer characteristics required for a × 4 interpolation filter.

FIG. 9 is a diagram showing a result of truncating an impulse response obtained by inverse Fourier transform at 64 points.

FIG. 10: Time m with LPF operating at 600 MHz
, The coefficients k1, k4, k8, k1 at m = 4n
It is a figure which shows the state where the product-sum circuit of 2 ... becomes nonzero.

FIG. 11: Time m with LPF operating at 600 MHz
When m is observed, the coefficients k1, k5, k are satisfied at m = 4n-1.
It is a figure which shows the state in which the product-sum circuit of 9, k13 ... becomes nonzero.

FIG. 12: Time m with LPF operating at 600 MHz
When m is observed, the coefficients k2, k6, k1 are satisfied at m = 4n-2.
It is a figure which shows the state where the sum-of-products circuit of 0, k14 ... becomes nonzero.

FIG. 13: Time m with LPF operating at 600 MHz
When m is observed, the coefficients k3, k7, k1 at m = 4n-3
It is a figure which shows the state where the product-sum circuit of 1, k15 ... becomes nonzero.

FIG. 14 is a diagram showing a configuration of an interpolation circuit configured to obtain 4-fold interpolation data in parallel in one clock.

FIG. 15 is a diagram showing an impulse response of an LPF that cuts off at ¼ of the Nyquist frequency.

FIG. 16 is a diagram showing an impulse response of an LPF that cuts off at 1/16 of the Nyquist frequency.

FIG. 17 is a diagram schematically showing a method of realizing a linear interpolation circuit.

FIG. 18: PR1 oversampled by 1.5 times
It is a figure which shows a channel output example.

FIG. 19 is a diagram showing a waveform example in which the PR1 channel output is interpolated 16 times.

FIG. 20 is a diagram showing an eye pattern of a waveform example in which the PR1 channel output is interpolated 16 times.

FIG. 21 is a block diagram showing a configuration example of a distortion detection circuit in the reproduction system of the tape streamer.

FIG. 22 is a diagram showing an example of operation waveforms of the distortion detection circuit.

FIG. 23 is a block diagram showing a modified example of the distortion detection circuit.

FIG. 24 is a block diagram showing another configuration example of the distortion detection circuit in the reproduction system of the tape streamer.

FIG. 25 is a diagram showing an example of operation waveforms of the distortion detection circuit.

FIG. 26 is a block diagram showing a modified example of the distortion detection circuit.

FIG. 27 is a data input type IIR LPF for each clock.
3 is a block diagram showing the configuration of FIG.

FIG. 28: II for every clock 16 parallel data input type
It is a block diagram which shows the structure of R type LPF.

FIG. 29 is an IIR-type HPF that is a data input type for each clock.
3 is a block diagram showing the configuration of FIG.

FIG. 30: II of every clock 16 parallel data input type
It is a block diagram which shows the structure of R type HPF.

FIG. 31 is a waveform diagram for explaining the principle of distortion correction in the reproduction system of the tape streamer.

FIG. 32 is a block diagram showing a principle configuration of a distortion correction circuit in the reproduction system of the tape streamer.

FIG. 33 is a characteristic diagram showing non-linearity of a non-linear circuit included in the distortion correction circuit.

FIG. 34 is a block diagram showing a specific configuration example of a distortion automatic correction circuit in the reproduction system of the tape streamer.

FIG. 35 is a block diagram showing a specific configuration example of a bias current automatic adjustment circuit in the reproduction system of the tape streamer.

FIG. 36 is a flowchart showing a distortion elimination sequence in the reproduction system of the tape streamer.

FIG. 37 is a diagram showing the relationship between the operating point of the MR head and the distortion of the reproduced waveform.

FIG. 38 is a diagram showing PR1 transfer characteristics.

FIG. 39 is a block diagram showing a configuration example of a recording / reproducing circuit of the HDD.

FIG. 40 is a diagram schematically showing the configuration of an HDD.

FIG. 41 is a diagram schematically showing a configuration of a fixed head type recording / reproducing system.

FIG. 42 is a diagram schematically showing the configuration of a recording / reproducing system of a helical scan type.

FIG. 43 is a diagram for explaining characteristic changes due to wear of the MR head.

FIG. 44 is a diagram showing reproduction characteristics of a worn MR head.

FIG. 45 is a diagram for explaining a conventional measure for dealing with a characteristic change due to wear of an MR head.

FIG. 46 is a block diagram showing a configuration example of a main part of a reproducing system in the case where a bias current automatic adjustment function and a distortion automatic correction function are added to a helical scan type tape streamer by a conventional technique.

FIG. 47 is a block diagram showing a modified example of FIG. 46.

48 is a block diagram showing a configuration example in which the drawbacks of the configuration shown in FIG. 47 are improved.

FIG. 49 is a diagram showing a PR1 channel output eye pattern. is doing.

FIG. 50 is a diagram showing an original waveform of the eye pattern.

FIG. 51 is a diagram showing data that is asynchronously sampled.

FIG. 52 is a diagram showing high-magnification oversampled data.

[Explanation of symbols]

1 magnetic tape, 2 reproducing head, 3 reproducing amplifier, 4
Rotary transformer, 5 equalization circuit, 6 ADC, 7
Fixed frequency oscillator, 8 automatic distortion correction circuit, 9 bias current automatic adjustment circuit, 10 PLL circuit, 11 reproduced signal discrimination circuit, 12 distortion correction circuit, 13 interpolation circuit, 14
Distortion detection circuit, 15 DAC, 16V / F conversion circuit,
17 rotary transformer, 18 F / V conversion circuit 1,
19 bias current setting circuit, 100 tape streamer playback system

Claims (9)

[Claims] 1. An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by an MR (Magneto-Resistive) head, and an interpolation process for the reproduction data digitized by the analog / digital conversion means. A distortion detection circuit comprising an interpolation means for generating high-magnification sampling reproduction data and a distortion detection means for detecting distortion of the high-magnification sampling reproduction data generated by the interpolation means by arithmetic processing. 2. The distortion detecting means includes a high-pass filter for removing a DC component of the reproduction data or the high-magnification sampling reproduction data, and a comparator for determining whether the high-magnification sampling reproduction data from which the DC component is removed is positive or negative. The distortion detection circuit according to claim 1, wherein the distortion is detected based on a duty ratio of the output of the comparator. 3. The distortion detecting means comprises a low-pass pass filter for extracting an average value of the reproduction data or the high-magnification sampling reproduction data, and a comparator for comparing the output of the low-pass pass filter with the high-magnification sampling reproduction data. And the output du of the comparator
The distortion detection circuit according to claim 1, wherein distortion is detected by a ty ratio. 4. An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by an MR (Magneto-Resistive) head, and a non-linear process for the reproduction data digitized by the analog / digital conversion means. Non-linear processing means with variable non-linear characteristics, interpolation means for performing interpolation processing on the reproduction data subjected to the non-linear processing by the non-linear processing means to generate high-magnification sampling reproduction data, and high-frequency data generated by the interpolation means. The non-linear processing means is provided with a distortion detecting means for detecting a distortion of the magnification sampling reproduction data by arithmetic processing, and a control means for variably controlling the non-linear characteristic of the non-linear processing means in accordance with the distortion detection output by the distortion detecting means. Distortion correction circuit characterized by outputting playback data with automatic distortion correction . 5. A bias current supply means capable of variably setting a current value for supplying a bias current flowing to an MR (Magneto-Resistive) head, and an analog circuit for sampling and digitizing a reproduction signal obtained by the MR head. Digital conversion means, interpolation means for performing interpolation processing on the reproduction data digitized by the analog / digital conversion means to generate high-magnification sampling reproduction data, and calculation for high-magnification sampling reproduction data generated by the interpolation means The MR comprises: distortion detecting means for detecting distortion by processing; and control means for variably controlling the current value of the bias current flowing through the MR head by the bias current supplying means according to the distortion detection output by the distortion detecting means. A bias voltage is applied to minimize the distortion of the reproduced signal obtained by the head. Bias adjustment circuit, characterized in that automatically adjusted. 6. An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by an MR (Magneto-Resistive) head, and non-linear processing for the reproduction data digitized by the analog / digital conversion means. Non-linear processing means with variable non-linear characteristics, interpolation means for performing interpolation processing on the reproduction data subjected to the non-linear processing by the non-linear processing means to generate high-magnification sampling reproduction data, and high-frequency data generated by the interpolation means. Distortion detection means for detecting distortion of the magnification sampling reproduction data by calculation processing, control means for variably controlling the non-linear characteristic of the non-linear processing means according to the distortion detection output by the distortion detection means, and non-linear processing by the non-linear processing means. Digital phase-locked to which reproduced data that has been applied is supplied -Loop (P
A signal processing circuit comprising an LL (Phase Locked Loop) circuit, wherein a detection point voltage is extracted from the reproduction data whose distortion is automatically corrected by the nonlinear processing means by the digital / PLL circuit. 7. An analog / digital conversion means for sampling and digitizing a reproduction signal obtained by an MR (Magneto-Resistive) head, and non-linear processing for the reproduction data digitized by the analog / digital conversion means. Non-linear processing means with variable non-linear characteristics, interpolation means for performing interpolation processing on the reproduction data subjected to the non-linear processing by the non-linear processing means to generate high-magnification sampling reproduction data, and high-frequency data generated by the interpolation means. Distortion detecting means for detecting distortion in the magnification sampling reproduction data by arithmetic processing, non-linear characteristic control means for variably controlling the non-linear characteristic of the non-linear processing means in accordance with the distortion detection output by the distortion detecting means, and flowing to the MR head. Bias current supplier with variable setting of bias current supply When the signal processing circuit and a bias current control means for variably controlled in accordance with the current value of the bias current supplied to the MR head by the bias current supply means to the distortion detection output of said distortion detecting means. 8. A bias current automatic optimization mode for optimizing a current value of a bias current flowing through the MR head by the bias current control means, and a distortion of reproduced data output from the non-linear processing means by the non-linear characteristic control means. 8. The signal processing circuit according to claim 7, further comprising control means for exclusively operating a distortion automatic correction mode for automatically correcting by the above. 9. The control means first performs a control of optimizing a bias current in a bias current automatic optimization mode, fixing the bias current after the optimization, and then setting a distortion automatic correction mode. The signal processing circuit according to claim 8.