JP2003195833A - Method and circuit for driving liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and circuit for driving a liquid crystal display device which can realize no display without varying the level of a driving voltage nor increasing the number of levels of the driving voltage even when there is no common value between driving voltage values for driving row electrodes and driving voltage values for driving column electrodes. <P>SOLUTION: In a no-display period, a row driver applies V<SB>2</SB>as a non-select voltage used in a normal display period to all row electrodes. A column driver, on the other hand, applies an ON driving voltage and an OFF driving voltage (V<SB>1</SB>, V<SB>3</SB>) used in the normal display period to the column electrodes alternately at fixed intervals. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving circuit capable of realizing display-off without increasing the circuit scale of the driving circuit in a simple matrix liquid crystal display device having a plurality of row electrodes and a plurality of column electrodes. .

[0002]

2. Description of the Related Art As a driving method of a simple matrix liquid crystal display device having a plurality of row electrodes and a plurality of column electrodes, there is a line-sequential driving method for selecting one row electrode at a time. In the line-sequential drive method, the APT (Alto
Pleshko Technique) and IAPT (Improved APT) that changes the reference level of voltage at a constant cycle. In addition, as a driving method of a simple matrix liquid crystal display device,
There is a driving method called a multi-line simultaneous selection driving method (multi-line addressing method: MLA method) for simultaneously selecting a plurality of row electrodes.

Liquid crystal display devices are widely used as display devices for man-machine interfaces. For example, it is widely used in PDAs (Personal Digital Assistants), mobile phones, etc. by taking advantage of its lightweight and thin characteristics. In such an application, the voltage applied to the liquid crystal element is 0 V with the power supply circuit in the operating state for a transition period when switching to a display state with a different duty, protection immediately before turning off the power supply, and saving power consumption. Therefore, it is required to set a non-display period in which the entire screen is hidden.

For example, consider a case where a full screen display is performed at 1/160 duty and the display is switched to a partial screen display at 1/64 duty. When switching from full screen display to partial screen display, the drive voltage value must be changed. However, the power supply circuit that generates the drive voltage cannot immediately switch the output voltage value even if it receives a command to switch the drive voltage value and starts the switching process. That is, the output voltage value of the power supply circuit gradually changes. As a result, immediately after switching from full screen display to partial screen display, partial screen display is performed with a drive voltage suitable for full screen display, and thereafter the drive voltage gradually changes to a value suitable for partial screen display. Then, immediately after the display is switched, the effective voltage applied to the liquid crystal element suddenly rises, the display becomes white once, and then the display gradually returns to an appropriate brightness. Similarly, when switching from partial screen display to full screen display, immediately after switching the display, full screen display is performed with a drive voltage suitable for partial screen display, and then the drive voltage gradually changes to full screen display. Change to a suitable value. As a result, immediately after the display is switched, the effective voltage applied to the liquid crystal element sharply decreases, the display temporarily darkens, and then the display gradually returns to an appropriate brightness.

Therefore, when the display is switched, the user feels uncomfortable with the display. To avoid such problems, when switching from full-screen display to partial-screen display and when switching from partial-screen display to full-screen display, turn off the display while keeping the power supply circuit operating. Insert a display period. In the non-display period, the voltage of the same value is applied to the row electrode and the column electrode to set the potential difference to 0V. That is, the voltage applied to the liquid crystal element is set to 0V. Then, when the non-display period starts, the power supply circuit is instructed to set the output voltage value to the voltage value after display switching, and after the output voltage value of the power supply circuit stabilizes at the value after switching, End the display period and start partial screen display or full screen display after screen switching.

By providing a non-display period when switching the display, it is possible to prevent the viewer from seeing an abnormal display in which the display temporarily becomes white or dark.

[0007]

However, as shown in the voltage application sequence diagram of FIG. 13, IAPT is used as a driving method.
When using, the potential difference between the row electrode and the column electrode can be easily set to 0V. However, when the APT or the MLA method in which the number of simultaneously selected lines is odd is used, it is not easy to set the potential difference between the row electrode and the column electrode to 0V. As shown in FIG. 13, in the IAPT, in the normal display period (display period in which display is performed based on display data), the drive voltage value for driving the row electrode and the drive voltage value for driving the column electrode are Common values (V ₀ and V ₅ )
There is.

Therefore, in the non-display period, the potential difference between the row electrode and the column electrode can be set to 0 V only by applying the drive voltage having a common value (for example, V ₀ ) to the row electrode and the column electrode. In FIG. 13, (COM) indicates a drive voltage for driving the row electrodes, (SEG) indicates a drive voltage for driving the column electrodes, and (SEG, COM) indicates a column electrode and a row electrode. The drive voltage that can be applied to both is shown. Also, the thick solid line shows the drive voltage applied to the column electrodes, and the broken line shows the drive voltage applied to the row electrodes.

However, when the APT is used as the driving method, there is no common value between the driving voltage value for driving the row electrodes and the driving voltage value for driving the column electrodes in the normal display period. Therefore, the drive circuit must be changed so that a drive voltage having a value that is not required in the normal display period can be applied to the row electrodes or the column electrodes in the non-display period. For example, as shown in the voltage application sequence diagram of the APT of FIG. 14, the drive circuit is configured so that V ₁ used only for driving the column electrodes in the normal display period can be applied to the row electrodes as well, and a common circuit is used. A driving voltage having a value can be applied to the row electrode and the column electrode.

When the APT is used as the driving method, the driving voltages applied to the row electrodes are V ₀ , V ₂ and V ₄ and the voltages applied to the column electrodes are V _{1 in} the normal display period. And V ₃ . However, in order to make the driving voltage value for driving the row electrode and the driving voltage value for driving the column electrode the same during the non-display period, the voltage V ₁ can be applied to the row electrode as shown in FIG. The drive circuit must be configured so that

In the conventional example shown in FIG. 14, V ₁ is also applied to the row electrodes.
The drive circuit is configured such that V ₁ can be applied, and V ₁ is applied to the row electrode and the column electrode in the non-display period, but the drive circuit is configured such that V ₂ can also be applied to the column electrode. In the non-display period, V ₂ may be applied to the row electrode and the column electrode.

Further, even when the MLA method in which the number of simultaneously selected lines is odd is used, the drive voltage value for driving the row electrodes and the column electrodes for driving the row electrodes in the normal display period are used as in the case of using the APT. There is no common value with the driving voltage value to drive. Therefore, even when the MLA method in which the number of simultaneously selected lines is an odd number is used, the drive circuit is changed so that the drive voltage having a value not required in the normal display period can be applied to the row electrodes in the non-display period. Must.

The V that is normally used to drive the column electrodes
_{Since 1} is the ground potential, in the non-display period,
By forcibly setting V ₂ used for driving the row electrodes to the ground potential, a drive voltage having a common value can be applied to the row electrodes and the column electrodes. That is, in the non-display period,
The V ₁ is applied to the column electrodes while applying V ₂ to all the row electrodes, and is forced to ground potential V _2.

However, when V ₂ is forcibly set to the ground potential, when the non-display period ends,
It is necessary to return the V ₂ to the original level. Then, when the level is returned to the original level, the power supply becomes unstable and the voltage waveform becomes unstable, so that a flickering display appears. Further, in order to prevent the display from being performed in such an unstable period, the drive circuit may be configured to restart the normal display period after V ₂ is stabilized at the original level. However, in such a configuration, since a relatively large DC voltage is continuously applied to the liquid crystal element, there is a problem that the liquid crystal element is deteriorated. Further, the output of V ₁ of the power supply circuit and V
_If there is an offset between the output of _{2 and} the output of _2, a DC voltage is applied to the liquid crystal element during the non-display period, which also deteriorates the liquid crystal element.

When the drive circuit is constructed so that the drive voltage, which is originally used only for driving the row electrodes or the column electrodes, can be applied to both the row electrodes and the column electrodes, the row electrodes are driven. The number of drive voltage levels or the number of drive voltage levels for driving the column electrodes increases. Then, in the row driver for driving the row electrodes or the column driver for driving the column electrodes, the scale of the switch for selecting one driving voltage from a plurality of driving voltages becomes large. As a result, the circuit scale of the drive circuit becomes large, and the cost of the drive circuit increases.

Therefore, according to the present invention, even if there is no common value between the drive voltage value for driving the row electrode and the drive voltage value for driving the column electrode, the level of the drive voltage can be changed or the drive voltage can be changed. It is an object of the present invention to provide a driving method and a driving circuit of a liquid crystal display device capable of realizing non-display without increasing the number of levels.

[0017]

A first aspect of the present invention is provided with a plurality of row electrodes and a plurality of column electrodes, a liquid crystal layer is arranged between the row electrodes and the column electrodes, and selection is made to apply to the row electrodes. Voltage and a non-selection voltage are provided, a plurality of display drive voltages to be applied to the column electrodes are provided, a selection voltage is applied to a selected row during the display period, a non-selection voltage is applied to a non-selected row, and display data is In the method of driving a liquid crystal display device, in which a drive voltage is selected based on the above and applied to the column electrodes, a non-display period during which display is not substantially performed is provided other than the display period, and two drive voltages are selected from the drive voltages. , The potential relationship between the non-selection voltage and the positive side non-display drive voltage and the negative side non-display drive voltage, which is used as the positive side non-display drive voltage and the negative side non-display drive voltage applied to the column electrode during the non-display period, Non-selection voltage is positive side non-display drive voltage and negative side non-display drive Set so that it is located near the intermediate voltage with the voltage, and that there is no other drive voltage between the positive side non-display drive voltage and the negative side non-display drive voltage. Then, the non-selection voltage is applied to all the row electrodes, and the positive side non-display driving voltage and the negative side non-display driving voltage are alternately applied to all the column electrodes to perform AC driving of the liquid crystal layer. A driving method is provided.

Aspect 2 is that in Aspect 1, the polarity inversion cycle of the display drive voltage applied to the column electrode during the display period is T ₁ , and the non-display period applied during the non-display period is applied to the column electrode. When the polarity inversion cycle of the drive voltage is T ₂ , T ₂ ≧ T
A driving method characterized by being ₁ . Since the display cannot be seen in the non-display period, the polarity inversion cycle may be lengthened, and the power consumption can be reduced by lengthening the polarity inversion cycle.

Aspect 3 provides the driving method according to Aspect 1, wherein the polarity inversion period of the non-display drive voltage applied to the column electrodes is two frame periods during the non-display period.

Aspect 4 provides a driving method according to any one of Aspects 1 to 3, wherein an odd number of row electrodes are simultaneously selected during the display period.

In the fifth aspect, the difference between the non-selection voltage and the intermediate voltage between the positive non-display driving voltage and the negative non-display driving voltage is 50 mV.
There is provided a driving method characterized by being within the range.

Aspect 6 provides a driving method characterized in that the driving voltage is two.

In a seventh aspect, a plurality of row electrodes and a plurality of column electrodes are provided, a liquid crystal layer is arranged between the row electrodes and the column electrodes, and a selection applied to the row electrodes by the liquid crystal drive voltage generating section. Voltage and a non-selection voltage are generated, a plurality of display drive voltages applied to the column electrodes are generated, and during the display period, the row electrode drive section applies the selection voltage to the selected row and unselects the non-selected row. In the drive circuit of the liquid crystal display device in which the voltage is applied and the drive voltage selected from the plurality of drive voltages based on the display data is applied to the column electrode by the column electrode drive unit, substantially except during the display period. A non-display period is provided in which no display is performed, two drive voltages are selected from a plurality of drive voltages, and used as the positive non-display drive voltage and the negative non-display drive voltage applied to the column electrodes during the non-display period. Selected and unselected Voltage and the positive side non-display drive voltage and negative side non-display drive voltage are set so that the non-selection voltage is located near the intermediate voltage between the positive side non-display drive voltage and the negative side non-display drive voltage. The driving voltage is set so that no other driving voltage exists between the positive non-display driving voltage and the negative non-display driving voltage, and the non-selection voltage is applied to all the row electrodes during the non-display period. Further, the positive side non-display driving voltage and the negative side non-display driving voltage are alternately applied to all the column electrodes to perform AC driving of the liquid crystal layer, and a control unit for activating the operation in the non-display period is further provided. A drive circuit characterized by the above is provided.

Aspect 8 is the same as Aspect 7, but during the display period,
There is provided a driving circuit characterized in that an odd number of row electrodes are simultaneously selected by a row electrode driving unit.

[0025]

(First Embodiment) FIG. 1 is a block diagram showing a drive circuit according to a first embodiment of the present invention together with a liquid crystal panel 1. In the configuration shown in FIG. 1, the liquid crystal panel 1 is provided with STN liquid crystal between a plurality of row electrodes and a plurality of column electrodes. Then, the row electrode is driven by the row driver 2 at the APT. Also, the column electrodes
The column driver 3 applies a voltage according to the display data.

The MPU interface section 41 is a circuit for distributing commands and data from the MPU outside the drive circuit. The command decoder 42 is a circuit that decodes a command received from the MPU via the MPU interface unit 41 and outputs the decoding result to the timing generation circuit 43. The timing generation circuit 43 is a circuit that generates a signal indicating a driving timing and setting signals such as a driving voltage ratio and a contrast voltage value. Oscillator circuit 4
Reference numeral 4 is a circuit that generates a clock signal that defines the driving timing and supplies the clock signal to the timing generation circuit 43 and other circuits.

The display data RAM 45 is a storage circuit for temporarily storing the display data received from the MPU via the MPU interface section 41. The address control circuit 46 is a circuit that manages a write address and a read address of the display data RAM 45.

The power supply circuit 5 is a circuit for generating liquid crystal driving voltages (driving voltages) at a plurality of voltage levels and supplying them to the row driver 2 and the column driver 3.

The timing generation circuit 43 includes a row driver 2
Also, the column driver 3 is instructed to at least an FLM (first line marker) indicating the start of one frame, an LP (latch pulse) indicating switching of a driving row (selected row), and an alternating current when performing alternating current driving. It outputs M (output inversion signal) and / DOFF (display off signal) which is a non-display instruction signal. Further, it outputs FLM or LP to the address control circuit 46. The row driver 2 is F
When LM is input, the drive row is switched according to LP that is subsequently input. When LP is input, the column driver 3 takes in the display data from the display data memory RAM 45 and applies a voltage according to the received display data to the column electrode.

The row driver 2 as the row electrode drive section
Then, the non-selection voltage is applied to all the row electrodes, and the column driver 3 serving as the column electrode driving unit is closest to the non-selection voltage and has the same absolute voltage value with respect to the non-selection voltage. In the configuration shown in FIG. 1, the timing generation circuit 43 implements the control unit that alternately applies the two types of drive voltages on the side to the column electrodes to set the non-display period.

FIG. 2 is a block diagram showing an example of a power supply circuit 5 as a liquid crystal drive voltage generating section. In the power supply circuit 5 shown in FIG. 2, a step-up DC-DC converter 51
Generates a voltage _{V out} and _{V 4i n} boosts the power supply voltage _{V dd} as an operating voltage from the outside. further,
The power supply circuit 5 controls the voltage V ₄ by the resistors 401 to 404.
Voltages V _{0 to} V ₄ are generated from _in and the ground potential GND and are supplied to the row driver 2 and the column driver 3. Power supply circuit 5
In, the driving capability of the voltage V _{0 to} V ₄ outputs is increased by the operational amplifiers 301 to 304 connected to the voltage follower.

As shown in the explanatory diagram for explaining the driving voltage in FIG. 3, V ₄ is used as a selection voltage (a driving voltage output by the row driver 2 at the time of selection) at the time of positive polarity driving of AC driving. V ₃ is used as an ON drive voltage during negative drive (a drive voltage output by the column driver 3 during ON display) and an OFF drive voltage during positive drive (a drive voltage output by the column driver 3 during OFF display). . V ₂ is used as a non-selection voltage (a drive voltage output by the row driver 2 when it is not selected). V ₁ is used as an ON drive voltage during positive polarity driving and an OFF drive voltage during negative polarity driving. Then, V ₀ is used as a selection voltage during negative polarity driving.
In the present embodiment, the time when the above M is at the low level is the time of positive polarity driving.

Next, the operation relating to the setting of the non-display period of the drive circuit of the present embodiment will be described with reference to the timing chart of FIG. 4 and the flowchart showing the operation of the drive circuit of FIG. Here, an example is given in which the normal display period in which the full screen display is performed shifts to the normal display period in which the partial screen display is performed. In the present embodiment, the full screen display is a display when driven at a predetermined duty ratio (for example, 1/160 duty), and the partial screen display is a duty ratio (duty ratio smaller than the duty ratio at the time of full screen display). For example, 1 /
This is a display when driven at 64 duty.

In FIG. 4, (a) shows an example of the output timing of the command output from the MPU. (B) shows / DOFF output from the timing generation circuit 43.
(C) shows the drive voltage applied to the liquid crystal element. (C)
The voltage level for full screen display shown in is the level of the drive voltage applied to the liquid crystal element during full screen display, and the voltage level for partial screen display is the level of the drive voltage applied to the liquid crystal element during partial screen display. is there. (D) shows an example of a drive voltage waveform applied to the column electrodes. (E) shows an example of a drive voltage waveform applied to the row electrodes. (F) shows the display state of the liquid crystal panel 1. In (f), full-screen display and partial-screen display are states in which a selection voltage (driving voltage applied to the selected row electrode) is applied to the row electrodes line-sequentially. The period in the state is the display period (normal display period). Further, the non-display is a state in which the display is erased, and the period in the non-display state is the non-display period.

As shown in FIG. 4A, when a command indicating display off is output from the MPU outside the drive circuit to the drive circuit (step S1), the MPU interface unit 41 in the drive circuit causes the command to be output. Is input, and the input command is delivered to the command decoder 42. When the command decoder 42 analyzes the command and recognizes that the command is a command indicating display off, the timing generation circuit 43 outputs / DOFF.
Instruct to occur. Timing generation circuit 43
/ D to the row driver 2 and the column driver 3 according to the instruction.
OFF is output (step S2). Specifically, the level of the / DOFF signal line reaching the row driver 2 and the column driver 3 is set to the low level.

As shown in FIG. 4E, the row driver 2
Receives / DOFF, it applies V ₂ to all row electrodes. Further, as shown in FIG. 4D, the column driver 3
Receives / DOFF, all column electrodes have V ₁ and V ₃
And are alternately applied in a constant cycle (step S3). The application duration of V _{1 and} the application duration of V ₃ are equal.

FIG. 6 is a block diagram showing a configuration example of a drive voltage switching portion in the column driver 3. In the configuration shown in FIG. 6, the column driver 3 has a counter 31 that counts clock signals. The counter 31 becomes a countable state when / DOFF is input, and when the count value becomes a value corresponding to the application duration time of V ₁ or V ₃ , the counter value is initialized and the switching unit 32 is set. On the other hand, V ₁ and V ₃
A signal indicating switching between and is given. The switching unit 32 is / DOF
While F is being output, V ₁ and V ₃ are switched according to the instruction of the counter 31. Also, while the / DOFF signal is not output, V ₁ and V
Switch to ₃ .

As shown in FIG. 4A, the MPU
Outputs a command indicating display off and then outputs a command indicating switching to partial screen display (step S4). In the drive circuit, the MPU interface unit 41 inputs a command and delivers the input command to the command decoder 42. When the command decoder 42 analyzes the command and recognizes that the command is a command indicating switching to partial screen display, the level of the driving voltages V _{0 to} V _{4 to be} output is changed from the normal display voltage level to the partial display voltage level. The power supply circuit 5 is instructed to switch to the screen display voltage level (step S5).

A signal line for transmitting a serial signal and a clock signal is provided from the timing generation circuit 43 to the power supply circuit 5. Further, the power supply circuit 5 generates a power supply V _out of the voltage follower-connected operational amplifiers 301 to 304 that generates drive voltages V _{0 to} V _4, and a liquid crystal voltage generation circuit with an electronic volume that generates V _4in. Built-in. DC-DC converter 51
Generates V _4in having a value corresponding to the data indicated by the serial signal from the timing generation circuit 43. When switching to the partial screen display, the timing generation circuit 43 synchronizes with the clock signal and outputs the data indicating the value of the electronic volume (the value corresponding to V ₄ in) corresponding to the partial screen display by the power supply circuit 5 by the serial signal. Transfer to. Further, the timing generation circuit 43 includes an address control circuit 46.
Also, the duty and the frame frequency corresponding to the partial screen display are notified to the row driver 2 (step S
5).

After outputting the command indicating display off, the MPU outputs a command indicating cancellation of display off after several 100 ms (step S7). Normally, in 200 to 300 ms, the output voltage of the power supply circuit 5 stabilizes at the voltage level for partial screen display (step S6).
Therefore, the MPU outputs a command indicating display off and then outputs a command indicating cancellation of display off 200 to 300 ms later.

In the drive circuit, the MPU interface section 41 inputs a command and delivers the input command to the command decoder 42. Command decoder 42
When analyzing the command and recognizing that the command is a command indicating the release of the display off, it instructs the timing generation circuit 43 to release / DOFF. The timing generation circuit 43 cancels the output of / DOFF to the row driver 2 and the column driver 3 according to the instruction (step S8). Specifically, row driver 2
To the column driver 3 and the level of the signal line of / DOFF is set to a high level.

In response to the release of / DOFF, the row driver 2 returns to the state of the normal display period in which the selection voltage is line-sequentially applied to the row electrodes. Since the row driver 2 has already been notified of the duty and frame frequency according to the partial screen display, the row driver 2 can immediately drive the row electrode with the duty and frame frequency according to the partial screen display (step S9). The duty and frame frequency have already been notified to the address control circuit 46. Therefore, the address control circuit 46
Can immediately output the display data from the display data RAM 45 to the column driver 3 with the duty and the frame frequency according to the partial screen display.

In the present embodiment, in the non-display period, the line
The driver 2 is a non-selective power used during the normal display period.
V which is pressure_TwoIs applied to all row electrodes. Also the column drive
Ivar 3 is an on-drive voltage used in the normal display period.
Voltage and OFF drive voltage are applied to the column electrodes alternately at a constant cycle.
It Therefore, V used only for driving the column electrodes ₁
Can be configured to apply to the row electrode,
V used to drive the row electrodes_TwoForcibly ground the
There is no need to rank.

FIG. 7 is a voltage application sequence diagram showing the drive voltage to the liquid crystal element in the non-display period. In the non-display period, the absolute value of the potential difference between the two types of drive voltages V ₁ and V ₃ applied to the column electrodes alternately at a constant cycle with respect to V ₂ applied to the row electrodes is equal. In other _{words, |} V 3 -V _{2
| =} | V 2 -V ₁ | is. That is, the ON drive voltage and the OFF drive voltage are the drive voltages closest to the non-selection voltage, the voltage absolute values of the non-selection voltage are equal, and the positive and negative sides of the non-selection voltage.

In the present embodiment, even if there is no common value between the driving voltage value for driving the row electrode and the driving voltage value for driving the column electrode, the level of the driving voltage can be changed or the number of levels can be changed. Non-display can be realized without increasing. As a result, in the column driver 3, one of the plurality of drive voltages is
The size of the switching unit 32 that selects one of the drive voltages does not increase, and the power supply becomes unstable and the voltage waveform does not become unstable by changing the value of V ₂ .

In the non-display period, a drive voltage corresponding to full-on display or full-off display is applied to the column electrodes, but no selection voltage is applied to the row electrodes. Therefore, for example, only an effective voltage (about 1/2) that is sufficiently lower than the effective voltage at the time of normal full-off display is applied to the liquid crystal element. Therefore, the display is invisible to the viewer. Further, since the voltage applied to the column electrodes is inverted in polarity at regular intervals, no direct current component is applied to the liquid crystal element.

The polarity inversion period (T ₂ ) in the non-display period is preferably relatively long from the viewpoint of reducing power consumption. In the normal display period, the polarity inversion period (denoted as T ₁ ) is several to several 1 from the viewpoint of reducing crosstalk and flicker.
The display is invisible during the non-display period, while the period for selecting the row electrode of the 0th row is set, so the polarity inversion cycle may be lengthened. That is, T ₂ ≧ T ₁ may be satisfied. For example, in the non-display period, the polarity inversion cycle of the non-display drive voltage applied to the column electrode may be two frame periods. In other words, the application duration of the ON drive voltage and the application duration of the OFF drive voltage to be applied to the column electrodes are respectively until the application of the voltage once to all the row electrodes during the normal display period. It may be equal to one frame period which is a period.

FIG. 8 is an explanatory diagram showing the potential relationship between the non-selection voltage and the positive side non-display drive voltage and the negative side non-display drive voltage. (A) shows the potential relationship in the present embodiment, and (B) shows the potential relationship by the IAPT method (see FIG. 13) as a comparative example. As described above, in the present embodiment, two drive voltages (V ₁ and V _{3 in the} present embodiment) are selected from the display drive voltages and are applied to the column electrodes during the non-display period. The side non-display drive voltage (V ₃ in this embodiment) and the negative non-display drive voltage (V _{3 in} this embodiment) are used as a non-selection voltage (V _{2 in} this embodiment) and a positive side non-display voltage. The potential relationship between the display drive voltage and the negative side non-display drive voltage is set so that the non-selection voltage is located near the intermediate voltage between the positive side non-display drive voltage and the negative side non-display drive voltage, and A driving method for setting such that no other driving voltage exists between the side non-display driving voltage and the negative side non-display driving voltage is realized. Further, during the non-display period, the non-selection voltage is applied to all the row electrodes, and the positive side non-display drive voltage and the negative side non-display drive voltage are alternately applied to all the column electrodes to drive the AC of the liquid crystal layer. Has been done. It is preferable that the intermediate voltage between the positive side non-display drive voltage and the negative side non-display drive voltage matches the non-selection voltage, but if they do not match, the positive side non-display drive voltage and the negative side non-display voltage. The difference between the intermediate voltage of the display driving voltage and the non-selection voltage is preferably within 50 mV.

(Comparative Example) FIG. 9 shows a column driver in the case where the drive circuit is configured so that V ₂ used only for driving the row electrode in the normal display period can be applied to the column electrode in the non-display period. 3 is a block diagram showing a drive voltage switching part in FIG. Originally, for display, the column driver may use V ₁ and V ₃ as driving voltages. Therefore,
A switch for selecting one input from two inputs may be provided. However, if V ₂ can be applied to the column electrode as well, it is necessary to provide the switching unit 33 of the column driver with a switch for selecting one input from three inputs.

Comparing the switching unit 32 of the present embodiment shown in FIG. 6 with the switching unit 33 as a comparative example shown in FIG. 9, the switching unit 32 has a smaller switch scale. Since the switching unit 32 or the switching unit 33 is provided corresponding to all the column electrodes, the scale of the drive circuit becomes very large when configured as shown in FIG.

(Second Embodiment) FIG. 10 is a block diagram showing a drive circuit according to a second embodiment of the present invention together with a liquid crystal panel 1. The drive circuit shown in FIG. 10 is different from the drive circuit of the first embodiment shown in FIG. 1 in timing generation circuit 43.
The orthogonal function generating circuit 6 is added between the row driver 2 and the row driver 2, and the ML is provided between the display data RAM 45 and the column driver 3.
This is a configuration in which the A arithmetic circuit 7 is provided. The drive circuit shown in FIG. 10 drives a liquid crystal element by the MLA method. ML
Method A is a method of collectively selecting and driving a plurality of row electrodes.

The voltage pulse voltage group (selection pulse group) applied to each row electrode simultaneously selected can be expressed by a matrix of L rows and K columns. Hereinafter, this matrix is referred to as a selection matrix (A). L is the number of simultaneously selected lines. The selection pulse group is represented as a vector group orthogonal to each other. Therefore, the matrix including those vectors as elements is an orthogonal matrix.

Each row in the orthogonal matrix corresponds to each row electrode of the liquid crystal display device. For example, the element in the first row of the selection matrix (A) is applied to the first line in the selection line. That is, the selection pulse is applied to the first row electrode in the order of the elements in the first column and the elements in the second column.

FIG. 11 is an explanatory diagram showing an example of a 4 × 4 orthogonal matrix that can be used as the selection matrix (A) when the number of simultaneously selected lines is 3. When the number of simultaneously selected lines is 3, for example, a 3 × 4 column portion of a 4 × 4 orthogonal matrix is used as the selection matrix (A). Figure 11
In the orthogonal matrix shown in, “1” is a positive selection pulse,
"-1" means a negative selection pulse. The voltage to be applied to the column electrode is displayed data (for example, on-display “−
1 ", off display" 1 ". ) And the row selection pattern corresponding thereto are bit-wise multiplied and the results are summed. Therefore, the types of voltage to be applied to the column electrodes are "-3", "-1",
There are four types, "1" and "3". As described above, in the MLA method, the level number (type) of the drive voltage applied to the column electrodes
Becomes the number of simultaneously selected lines + 1.

In the normal display period, the orthogonal function generating circuit 6 holds the orthogonal matrix, and according to the instruction signal from the timing control circuit 43 output for each selection period.
The elements of the orthogonal matrix are applied to the row driver 2 and the MLA arithmetic circuit 7
Output to. The MLA arithmetic circuit 7 has a display data RAM 4
A column voltage pattern applied to the column electrode is generated by performing a product-sum operation of the display data output from 5 and the elements of the orthogonal matrix output from the orthogonal function generating circuit 6. Then, the column voltage pattern is output to the column driver 3. Column driver 3
Applies a drive voltage according to the column voltage pattern to the column electrodes.

In the MLA method, in order to reduce the number of drive voltage levels, there is a method in which some of the lines that are simultaneously selected are virtual lines that are not actually displayed. FIG. 12 is an explanatory diagram showing the MLA method in the case where a Hadamard matrix with 4 rows and 4 columns is used and the 4th row is a virtual row. In FIG. 12, (a)
Shows an example of a selection matrix and display data, and (b) shows an example of an image display pattern and a drive voltage pattern. Column electrode i,
12 shows the display data displayed with the row electrodes L = 1, L = 2, L = 3 in FIG.
As shown in (a), the column display pattern is as shown in FIG.
It is represented by a vector (d) as shown in (b).

The drive voltage pattern to be sequentially applied to the column electrodes i, j corresponds to the product of the column display pattern and the corresponding row selection pattern bit by bit and the sum of the results. Therefore, the voltage pattern to be sequentially applied to the column electrodes i and j is like a vector (v) shown in FIG. 12B, which has two kinds of values of “−2” and “2” as elements. . That is, when the number of simultaneously selected lines is 3 and one virtual row is provided, the number of drive voltage levels applied to the column electrodes can be reduced to 2.

Therefore, the APT of the first embodiment shown in FIG.
The driving voltage can be set in the same manner as in the above case. That is, V ₂ is a non-selection voltage, and V corresponding to “−2”
₁ and V ₃ corresponding to “2” can be the ON drive voltage or the OFF drive voltage. Even in such a driving method, the effective voltage applied to the liquid crystal element when turned on and the effective voltage applied to the liquid crystal element when turned off are constant.

Therefore, when the liquid crystal panel 1 is driven using the MLA method in which the number of simultaneously selected lines is 3 and one virtual row is provided, as in the case of the first embodiment, in the non-display period, It is effective that the row driver 2 applies the non-selection voltage to all the row electrodes, and the column driver 3 alternately applies the ON drive voltage and the OFF drive voltage to the column electrodes at a constant cycle.
That is, the number of simultaneous selections is 3, and one virtual row to which the driving voltage is not applied is set, and a predetermined voltage based on the elements of the orthogonal matrix is applied to the selected three row electrodes during the selection period. Even when the driving method of applying the voltage is used, the column driver 3 can realize the non-display period by alternately applying the on-driving voltage and the off-driving voltage to the column electrode in a constant cycle.

As in the case of the first embodiment, when the MPU outputs a command indicating display off to the drive circuit, the timing generation circuit 43 shown in FIG. 10 causes the command decoder 42 to which the command indicating display off is input. Row driver 2 and column driver 3 in response to instructions from
And / DOFF is output. Also, the command decoder 4
2 recognizes that the command input from the MPU is a command indicating switching to partial screen display,
The power supply circuit 5 is instructed to switch the output drive voltages V _{0 to} V ₄ from the normal display voltage level to the partial screen display voltage level. Note that the number of simultaneously selected lines is 3 here. Therefore, as in the case of the first embodiment, V ₀ , V ₂ and V ₄ are supplied from the power supply circuit 5 to the row driver 2 and V ₁ and V ₃ are supplied to the column driver 3.

When the row driver 2 receives / DOFF,
Non-selection voltage V for all row electrodes _TwoIs applied. Well
In addition, the column driver 3 receives all the columns when / DOFF is received.
V, which is an ON drive voltage and an OFF drive voltage, is applied to the electrodes.₁，
V_ThreeAre alternately applied in a constant cycle. The ON drive voltage
The application duration of OFF drive voltage and the application duration of OFF drive voltage are equal.
Yes.

Also in this embodiment, the level of the drive voltage is changed even if there is no common value in the drive voltage value for driving the row electrode and the drive voltage value for driving the column electrode. The non-display can be realized without increasing the number of drive voltage levels. As a result, in the column driver 3, the scale of the switching unit that selects one drive voltage from a plurality of drive voltages does not become large, and the power supply becomes unstable or the voltage waveform becomes unstable by changing the drive voltage value. It does not become unstable.

When the number of simultaneous selections is odd and a virtual row is not provided, there are a plurality of driving voltage values applied to the column electrodes that are larger and smaller than the non-selection voltage value. Further, among the drive voltage values applied to the column electrodes, there is no drive voltage value that matches the selection voltage and the non-selection voltage applied to the row electrodes. In this case, in the non-selection period, the column driver 3 is arranged so that the column driver 3 is closest to the non-selection voltage, has the same absolute voltage value with respect to the non-selection voltage, and alternately drives positive and negative drive voltages with respect to the non-selection voltage. Can be applied to. For example, when the number of simultaneously selected lines is 3 and no virtual row is provided, the selection voltage is V ₀ , V ₆ and the non-selection voltage is V ₃ , and the driving voltage applied to the row electrode is V ₁ , V _2, but _V is 4, _{V 5,} the non-selection period, the column driver 3, may be applied alternately and _{V 2} and _{V 4} with respect to the column electrodes. Here, V ₀ <V ₁ <V ₂ <V ₃
<V ₄ <V ₅ <V ₆ and | V ₄ −V ₃ | = | V ₃ −
V ₂ |.

[0064]

As described above, according to the driving method and the driving circuit of the present invention, the potential relationship between the non-selection voltage and the positive side non-display driving voltage and the negative side non-display driving voltage is not selected in the non-display period. The voltage is set near the intermediate voltage between the positive non-display driving voltage and the negative non-display driving voltage, and another voltage is set between the positive non-display driving voltage and the negative non-display driving voltage. The drive voltage is set so that no non-selection voltage is applied to all the row electrodes during the non-display period, and the positive side non-display drive voltage and the negative side non-display drive voltage are applied alternately to all the column electrodes. Since the liquid crystal layer is AC driven, the level of the drive voltage can be changed even if there is no common value between the drive voltage value for driving the row electrode and the drive voltage value for driving the column electrode. Hiding can be realized without increasing the number of levels.

[Brief description of drawings]

FIG. 1 is a block diagram of a drive circuit according to a first embodiment.

FIG. 2 is a block diagram showing an example of a power supply circuit.

FIG. 3 is an explanatory diagram for explaining a driving voltage.

FIG. 4 is a timing diagram illustrating a driving method.

FIG. 5 is a flowchart showing the operation of the drive circuit.

FIG. 6 is a block diagram showing a configuration example of a drive voltage switching portion of a column driver.

FIG. 7 is a voltage application sequence diagram according to the first embodiment.

FIG. 8 is an explanatory diagram showing a potential relationship between a non-selection voltage and a positive side non-display driving voltage and a negative side non-display driving voltage.

FIG. 9 is a block diagram showing a configuration example of a drive voltage switching portion of a column driver of a comparative example.

FIG. 10 is a block diagram of a drive circuit according to a second embodiment.

FIG. 11 is an explanatory diagram showing an example of a 3 × 4 column of a 4 × 4 orthogonal matrix.

FIG. 12 is an explanatory diagram showing an MLA method in the case where a Hadamard matrix with 4 rows and 4 columns is used and a 4th line is a virtual row.

FIG. 13 is a voltage application sequence diagram showing a conventional example.

FIG. 14 is a voltage application sequence diagram showing a conventional example.

[Explanation of symbols]

1 LCD panel 2-line driver 3-row driver 5 power supply circuit 6 Orthogonal function generator 7 MLA arithmetic circuit 41 MPU interface section 42 Command Decoder 43 Timing generation circuit 44 oscillator circuit 45 Display data RAM 46 Address control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623D (72) Inventor Tomohiro Takano 1150 Hazawa-machi, Kanagawa-ku, Yokohama-shi, Kanagawa Asahi Glass Co., Ltd. (72) Inventor Masashi Issei 1150, Hazawa-machi, Kanagawa-ku, Yokohama, Kanagawa F-Term (Reference) in Asahi Glass Co., Ltd. BC11 BF24 BF43 FA45 GA02 5C080 AA10 BB05 DD26 DD30 EE32 FF12 JJ02 JJ04 JJ07

Claims (8)

[Claims] 1. A column electrode comprising a plurality of row electrodes and a plurality of column electrodes, a liquid crystal layer being arranged between the row electrodes and the column electrodes, and providing a selection voltage and a non-selection voltage applied to the row electrodes. A plurality of drive voltages for display to be applied to are provided, a select voltage is applied to a selected row and a non-select voltage is applied to a non-selected row during the display period, and the drive voltage is selected based on the display data and the column is selected. In a method of driving a liquid crystal display device applied to electrodes, a non-display period during which a display is not substantially provided is provided in addition to the display period, two drive voltages are selected from the drive voltages, and a column electrode is applied during the non-display period. Used as positive side non-display drive voltage and negative side non-display drive voltage to be applied, the potential relationship between non-selection voltage, positive side non-display drive voltage and negative side non-display drive voltage Near the intermediate voltage between the voltage and the non-display drive voltage on the negative side. Set so that there is no other drive voltage between the positive side non-display drive voltage and the negative side non-display drive voltage, and set all non-selection voltage during the non-display period. Driving method for a liquid crystal display device, characterized in that a positive side non-display driving voltage and a negative side non-display driving voltage are alternately applied to all the column electrodes and AC driving of the liquid crystal layer is performed. . 2. A polarity inversion cycle of a display drive voltage applied to a column electrode during a display period is T _1, and during a non-display period,
The driving method for a liquid crystal display device according to claim ₁ , wherein T ₂ ≧ T ₁ where T ₂ is a polarity inversion period of the non-display driving voltage applied to the column electrodes. 3. The method for driving a liquid crystal display device according to claim 1, wherein the polarity inversion cycle of the non-display drive voltage applied to the column electrodes is two frame periods during the non-display period. 4. The method of driving a liquid crystal display device according to claim 1, 2 or 3, wherein an odd number of row electrodes are simultaneously selected during a display period. 5. The liquid crystal display device according to claim 1, wherein the difference between the non-selection voltage and the intermediate voltage between the positive side non-display driving voltage and the negative side non-display driving voltage is within 50 mV. Driving method. 6. The driving voltage is two,
6. The method for driving the liquid crystal display device according to 3, 4, or 5. 7. A plurality of row electrodes and a plurality of column electrodes are provided, a liquid crystal layer is disposed between the row electrodes and the column electrodes, and a selection voltage applied to the row electrodes by a liquid crystal drive voltage generator. A non-selection voltage and a plurality of display drive voltages applied to the column electrodes are generated.The row electrode drive section applies the selection voltage to the selected row and the non-selection voltage to the non-selected row during the display period. Is applied, and a drive voltage selected from the drive voltages based on the display data is applied to the column electrodes by the column electrode drive section, in a drive circuit of a liquid crystal display device, substantially during a period other than the display period. A non-display period in which no display is performed is provided, and two drive voltages are selected from the drive voltages, which are used as a positive side non-display drive voltage and a negative side non-display drive voltage applied to the column electrodes during the non-display period. , Unselected voltage The potential relationship between the positive side non-display drive voltage and the negative side non-display drive voltage is set so that the non-selection voltage is located near the intermediate voltage between the positive side non-display drive voltage and the negative side non-display drive voltage. And, it is set so that no other drive voltage exists between the positive side non-display drive voltage and the negative side non-display drive voltage, and the non-selection voltage is applied to all the row electrodes during the non-display period. In addition, the positive side non-display driving voltage and the negative side non-display driving voltage are alternately applied to all the column electrodes to perform AC driving of the liquid crystal layer, and a control unit for activating the operation in the non-display period is further provided. A drive circuit of a liquid crystal display device characterized by the above. 8. A drive circuit for a liquid crystal display device according to claim 7, wherein an odd number of row electrodes are simultaneously selected by the row electrode drive section during the display period.