JP2003189608A - Switching power supply unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching power supply unit having a current doubler synchronous rectifying circuit, capable of attaining a simple structure, less power loss, and high efficiency. <P>SOLUTION: A pair of sub windings 16 are provided on a transformer 12, one end of the sub windings 16 is connected with a gate of an FET for synchronous rectification on one side of the current doubler synchronous rectifying circuit 14, and the other end of the sub windings 16 is connected with a gate of the FET for synchronous rectification on the other side. A diode D<SB>1</SB>is connected between the gate of FET for synchronous rectification on one side and a source thereof, and a diode D<SB>2</SB>is connected between the gate of the FET for synchronous rectification on the other side and a source thereof. In the respective diodes D<SB>1</SB>, D<SB>2</SB>, the anodes thereof are connected to the sources of the FET for synchronous rectification, and the cathodes thereof are connected to the gates of the FET for synchronous rectification. As a result, during the whole period when the current is flowing through the FET for synchronous rectification, the FET can be turned on. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device that converts a DC voltage into a desired voltage and supplies the voltage to electronic equipment.

[0002]

2. Description of the Related Art Conventionally, there has been a switching power supply device having a current doubler synchronous rectification circuit using a MOS-FET as a synchronous rectification element as shown in FIGS. 13 (a) and 13 (b). The switching power supply device shown in FIG. 13 (a) is one in which the push-pull circuit 2 is provided on the primary side of the transformer 1, and the switching power supply device shown in FIG. 13 (b) is a half bridge on the primary side of the transformer 1. The circuit 3 is provided. A current doubler synchronous rectification circuit 4 is provided on the secondary side of the transformer 1 to perform synchronous rectification by the operation shown in FIG. This current doubler synchronous rectification circuit 4 has two components, as shown in FIG.
The drains of the MOS-FETs Q1 and Q2, which are synchronous rectifiers whose sources are connected to each other, are connected to the next side.
Coils L1 and L2 are placed between the drains of ETQ1 and Q2.
An output capacitor Co is connected in parallel between the coils L1 and L2 and the sources of the FETs Q1 and Q2.

This current doubler synchronous rectifier circuit 4 has no center tap in the transformer, the transformer has a simple structure, and the current propagating through the transformer is ½ compared to the full-wave rectifier circuit. It has the advantage that the ripple current is canceled.

The operation of the conventional current doubler synchronous rectification circuit 4 will be described with reference to FIG. Here in FIG.
(A) is the output voltage VT of the secondary side of the transformer 1, (b)
Is the gate-source voltage VGS (Q1) of the FET Q1,
(C) is the gate-source voltage VGS (Q
2) and (d) are current I (L1) of the coil L1, I (e) is current I (L2) of the coil L2, (f) is drain current I (Q1) of the FET Q1, and (g) is drain current of the FET Q2. I (Q2).

In the operation of the current doubler synchronous rectification circuit 4, a positive voltage is output to the terminal with a dot on the secondary side of the transformer 1 in the period A of FIG. 14, and this voltage causes the input capacitance Ciss of the FET Q2 to The gate is charged to a positive potential, and the FET Q2 turns on. Also,
Since the gate of the input capacitance Ciss of the FET Q1 is charged to a negative potential, it remains in the off state. Then, the current output from the terminal with the dot on the secondary side of the transformer 1 is the transformer 1, the coil L1, and the capacitor C.
o, FET Q2, transformer 1 flow. At this time, the current output from the coil L2 flows through the path of the coil L2, the capacitor Co, the FET Q2, and the coil L2. Therefore, during this period, the coil L1 stores energy and the coil L2 emits energy.

Next, in the period B, no voltage is output to the secondary side of the transformer 1, and the FE charged in the period A is discharged.
The input capacitance Ciss of TQ2 is discharged and the FET Q2 is turned off. The input capacitance Ciss of the FET Q1 is
Since the gate was charged to a negative potential,
This is also discharged, but the FET Q1 remains off. Then, since no current is output from the transformer 1, the coil L
Both 1 and L2 are in a state of releasing energy.
At this time, the current output from the coil L1 is
1, the capacitor Co, the FET Q1, the coil L1, and the current output from the coil L2 flows through the coil L2,
It flows through the path of the capacitor Co, the FET Q2, and the coil L2. Further, since the FETs Q1 and Q2 are in the off state,
The current passes through the parasitic diode Dq of the FETs Q1 and Q2 as shown in FIG.

When a positive voltage is output to the dotless terminal on the secondary side of the transformer 1 in the period C, FE
The input capacitance Ciss of TQ1 is charged to a potential at which the gate becomes positive, and the FET Q1 turns on. In addition, FETQ2
Since the input capacitance Ciss is charged to a potential at which the gate becomes negative, the FET Q2 remains in the off state. The current output from the non-dotted terminal on the secondary side of the transformer 1 flows through the transformer 1, the coil L2, the capacitor Co, the FET Q1, and the transformer 1. At this time, the current output from the coil L1 flows through the path of the coil L1, the capacitor Co, the FET Q1, and the coil L1. Therefore, during this period, the coil L2 stores energy and the coil L1 emits energy.

In the period D, as in the period B, no voltage is output to the secondary side of the transformer 1, and the input capacitance Ciss of the FET Q1 charged in the period C is discharged.
The FET Q1 turns off. Also, the input capacitance Ci of the FET Q2
Since ss was charged to a potential whose gate becomes negative in the period C, it is also discharged, but the FET Q2 remains off. Since no current is output from the transformer 1, the coils L1 and L2 are both in a state of releasing energy. At this time, the current output from the coil L1 flows through the path of the coil L1, the capacitor Co, the FET Q1, and the coil L1, and the current output from the coil L2 is
Coil L2, capacitor Co, FETQ2, coil L2
Flow through the route. Further, since the FETs Q1 and Q2 are in the off state, the current passes through the parasitic diode Dq of the FETs Q1 and Q2.

[0009]

In the case of the above conventional technique, there are periods B and D in which the FETs Q1 and Q2 are turned off in the period in which the current passes through the synchronous rectification FETs Q1 and Q2. During this period B and D, as shown in FIG.
Since a current flows through the parasitic diode Dq of TQ1 and Q2, there is a problem that the loss due to the forward voltage of the parasitic diode Dq occurs and the loss due to the FETs Q1 and Q2 increases.

The present invention has been made in view of the above prior art, and an object of the present invention is to provide a highly efficient switching power supply device having a current doubler synchronous rectification circuit and having a simple structure and less power loss. .

[0011]

According to the present invention, there is provided a push-pull circuit, a half-bridge circuit, or a drive circuit for generating a voltage similar to that when driven by these circuits on the secondary side of the transformer. In preparation for this, a current doubler synchronous rectifier circuit is provided on the secondary side of the transformer, and the synchronous rectifier element of this current doubler synchronous rectifier circuit is a MOS-F.
A switching power supply device configured by ET and other elements having a similar function to perform synchronous rectification, in which one set of sub-windings is provided in the transformer, and one end of the sub-winding and one synchronous rectification element The gate of the other sub-winding and the gate of the other synchronous rectifier, the diode between the gate and the source of one synchronous rectifier, and the gate and the source of the other synchronous rectifier. Also connect a diode. The anode of each diode is connected to the source of each synchronous rectifying element, and the cathode is connected to the gate of each synchronous rectifying element. With such a circuit, it becomes possible to turn on the synchronous rectification FET during the entire period of time when the current flows through the synchronous rectification FET.
It prevents the current from flowing through the parasitic diode of T and increasing the loss.

Further, according to the present invention, a voltage limiting circuit is provided between the terminal of the sub winding of the transformer and the gate of the synchronous rectification FET. The voltage limiting circuit is a power supply circuit that outputs a voltage equal to or lower than the breakdown voltage of the gate. With this circuit, the synchronous rectification FET can be turned on and the input voltage range of the switching power supply device can be widened during the entire period in which the current flows through the synchronous rectification FET.

In the voltage limiting circuit, a transistor is provided between the terminal of the sub winding and the gate of the synchronous rectifying element, the emitter of the transistor is connected to the gate of the synchronous rectifying element, and the collector is the sub winding. And a reference voltage generator connected to the base of the transistor. A diode is connected between the emitter and collector of the transistor, and the diode has the emitter connected to the anode and the collector connected to the cathode.

In the voltage limiting circuit, the MOS-F is provided between the terminal of the sub winding and the gate of the synchronous rectifying element.
ET may be provided, the source of the MOS-FET is connected to the gate of the synchronous rectification element, the drain is connected to the terminal of the sub-winding, and the reference voltage generator is connected to the gate of the MOS-FET.

Further, according to the present invention, a discharge circuit is provided together with the voltage limiting circuit. This discharge circuit is used for the synchronous rectification F even when the input capacitance values of the two synchronous rectification FETs of the current doubler synchronous rectification circuit become unbalanced.
It is possible to surely turn off the ET during the period when it is desired to be turned off, and it is possible to turn on the synchronous rectification FET during the entire period in which the current flows through the synchronous rectification FET.

Further, according to the present invention, two sets of sub windings are provided in the transformer, one end of one sub winding is connected to the gate of one synchronous rectifying element through a capacitor, and one sub winding of the one sub winding is connected. Connect the other end and the source of the synchronous rectification element,
The other end of the one sub-winding is connected to one end of the other sub-winding, and the other end of the other sub-winding is connected to the gate of the other synchronous rectification element via another capacitor, One end of the other sub-winding is connected to the source of the other synchronous rectifier, a diode is connected between the gate and the source of the one synchronous rectifier, and the gate and the source of the other synchronous rectifier are connected. Is a switching power supply device in which the anode is connected to the source of the synchronous rectifying element and the cathode is connected to the gate of the synchronous rectifying element.

Further, a voltage limiting circuit for outputting a voltage equal to or lower than the breakdown voltage of the gate may be provided between the capacitor and the gate of the synchronous rectifying element.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a switching power supply device according to a first embodiment of the present invention.
In the switching power supply device 10, a current doubler synchronous rectification circuit 14 is provided on the secondary side of the transformer 12. As shown in FIG. 1, in the current doubler synchronous rectification circuit 14, the drains of the MOS-FETs Q1 and Q2, which are synchronous rectification elements whose sources are connected to each other, are connected to the secondary side of the transformer 12, and the drains of the FETs Q1 and Q2 are connected. Coils L1 and L2 are connected between the drains, and an output capacitor Co is connected in parallel between the sources of the coils L1 and L2 and the FETs Q1 and Q2.

Further, the transformer 12 is provided with a set of sub-windings 16, and one end of the sub-windings 16 is connected to the gate of one of the synchronous rectification elements, the MOS-FET Q1, and the other sub-windings 16 are connected. MOS-F, which is a synchronous rectification element on the other end
The gate of ETQ2 is connected. One FET Q1
A diode D1 is connected between the gate and source of
The diode D is also between the gate and source of the other FET Q2.
2 is connected. The anodes of the diodes D1 and D2 are connected to the sources of the FETs Q1 and Q2, and the cathodes of the diodes D1 and D2 are connected to the gates of the FETs Q1 and Q2.

Next, the operation of the current doubler synchronous rectification circuit 14 of this embodiment will be described with reference to FIG. 2A is an output voltage VT on the secondary side of the transformer 12, FIG. 2B is an output voltage Vsub of the sub winding 16, and FIG.
(C) is the gate-source voltage VGS (Q
1) and (d) are the gate-source voltage VG of the FET Q2.
S (Q2), (e) is the current I (L1) of the coil L1,
(F) is the current I (L2) of the coil L2, (g) is the FET
The drain current I (Q1) and (h) of Q1 are the drain current I (Q2) of the FET Q2.

In the operation of the current doubler synchronous rectification circuit 14, a positive voltage is output to the terminal with a dot on the secondary side of the transformer 12 in the period A of FIG. A positive voltage is output from the dot terminal. The voltage of the sub winding 16 charges the input capacitance Ciss of the FET Q2,
The input capacitance Ciss of 1 is discharged.

The current flowing out from the sub winding 16 of the transformer 12 is supplied to the sub winding 16 of the transformer 12 and the FET when the input capacitance Ciss of the FET Q1 is discharged.
It flows from the gate of Q2 to the source, the source of FET Q1 to the gate, and the sub winding 16 of the transformer 12. Then, when the FET Q1 is discharged and becomes equal to or lower than the forward voltage of the diode D1, the sub winding 16 of the transformer 12 and the FET Q2
Flows from the gate to the source, from the anode of the diode D1 to the cathode of the sub winding 16 of the transformer 12.
As a result, the FET Q2 is turned on and the FET Q1 is turned off. At this time, the current output from the secondary side of the transformer 12 flows through the path of the transformer 12, the coil L1, the capacitor Co, the FET Q2, and the transformer 12. At this time, the current flowing through the coil L2 is in the path of the coil L2, the capacitor Co, the FET Q2, and the coil L2. Therefore, during this period, the coil L1 stores energy and the coil L2 emits energy.

Next, in the period B, 2 of the transformer 12 is used.
No voltage is output to the secondary side, and no voltage is output from the sub winding 16. FET Q2 charged in period A
The electric charge stored in the input capacitance Ciss of
Input capacitance Ciss of the FET Q1 via the sub winding 16 of
Move to. In this current doubler synchronous rectification circuit 14, since FETs Q1 and Q2 use FETs of the same type, the input capacitance Ciss of the FET Q1 and the input capacitance Ciss of the FET Q2 are equal, and the input capacitance Ciss of the FET Q2 is equal.
Half of the transition to the FET Q1. Here, since the electric charge stored in the capacitor is the product of the capacitance of the capacitor and the voltage, the input capacitance Cis of the FET Q2 in this period B is
The voltage b due to the electric charge of s becomes half of the voltage a charged in the period A. The voltage a is equal to the voltage generated in the sub winding 16 minus the forward voltage of the diode D1. Further, the voltage of the FET Q1 becomes equal to the voltage of the FET Q2.

By the above operation, the input capacitances Ciss of the FETs Q1 and Q2 are both charged,
The FETs Q1 and Q2 are turned on. Since no current is output from the secondary side of the transformer 12, the coil L
Both 1 and L2 are in a state of releasing energy.
At this time, the current output from the coil L1 is
1, the capacitor Co, the FET Q1, the coil L1, and the current output from the coil L2 flows through the coil L2,
It flows through the path of the capacitor Co, the FET Q2, and the coil L2. Moreover, since the FETs Q1 and Q2 are in the ON state,
The current is FET Q1, Q2 as shown in FIG.
It does not pass through the parasitic diode Dq.

Then, in the period C, a positive voltage is output to the non-dotted terminal on the secondary side of the transformer 12,
At this time, the sub winding 16 of the transformer 12 also outputs a positive voltage from the terminal having no dot. The voltage of the sub winding 16 charges the input capacitance Ciss of the FET Q1,
The input capacitance Ciss of the FET Q2 is discharged.

The current flowing out of the sub winding 16 of the transformer 12 is supplied to the sub winding 16 of the transformer 12 and the FET when the input capacitance Ciss of the FET Q2 is discharged.
It flows from the gate of Q1 to the source, from the source of FET Q2 to the gate, and through the path of the sub winding 16 of the transformer 12. Further, when the FET Q2 is discharged and becomes lower than the forward voltage of the diode D2, the sub winding 16 of the transformer 12 and the FET Q
1 flows from the gate to the source, the anode of the diode D2 to the cathode, and the sub winding 16 of the transformer 12. As a result, the FET Q1 is turned on and the FET Q2 is turned off. At this time, the current output from the secondary side of the transformer 12 flows through the path of the transformer 12, the coil L2, the capacitor Co, the FET Q1, and the transformer 12. At this time, the current flowing through the coil L1 is
It is a path for the capacitor Co, the FET Q1, and the coil L1. Therefore, during this period, the coil L2 stores energy and the coil L1 emits energy.

Further, in the period D, the transformer 12
No voltage is output to the secondary side of the sub winding 16 and no voltage is output from the sub winding 16. FET charged in period C
The charge stored in the input capacitance Ciss of Q1 passes through the sub winding 16 of the transformer 12 and the input capacitance Ci of the FET Q2.
Move to ss. That is, as in the period B, half of the input capacitance Ciss of the FET Q1 is transferred to the FET Q2, the voltage of the input capacitance Ciss of the FET Q1 in the period D becomes 1/2 of the voltage charged in the period C, and F
The voltage of ETQ2 becomes equal to the voltage of FETQ1.

By the above operation, the input capacitances Ciss of the FETs Q1 and Q2 are both charged,
The FETs Q1 and Q2 are turned on. Since no current is output from the secondary side of the transformer 12, the coil L
Both 1 and L2 are in a state of releasing energy.
At this time, the current output from the coil L1 is
1, the capacitor Co, the FET Q1, the coil L1, and the current output from the coil L2 flows through the coil L2,
It flows through the path of the capacitor Co, the FET Q2, and the coil L2. Moreover, since the FETs Q1 and Q2 are in the ON state,
The current does not pass through the parasitic diode Dq of the FETs Q1 and Q2 as shown in FIG.

In the current doubler synchronous rectification circuit 14 of this embodiment, the FETs Q1 and Q2 do not turn off during the period when the current flows through the synchronous rectification FETs Q1 and Q2, and the entire period when the current flows through the FETs Q1 and Q2. It is possible to turn on the FETs Q1 and Q2 at
There is no loss due to the current flowing through the parasitic diode,
The efficiency of the switching power supply device 10 can be improved.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 and 4. Here, the same members as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. The current doubler synchronous rectification circuit 24 of the switching power supply device 20 of this embodiment is provided with voltage limiting circuits 22 and 23 between the diode D1 and the FET Q1 and between the diode D2 and the FET Q2, respectively. The voltage limiting circuits 22 and 23 output a voltage equal to or lower than the gate breakdown voltage of the FETs Q1 and Q2.

As shown in FIG. 4, the voltage limiting circuits 22 and 23 connect the reference voltage generator 25 to the Zener diode ZD1.
1. The voltage limiting circuit 22 is composed of the capacitor C11.
Is connected to the base of the transistor Tr11 via the resistor R11, and the reference voltage generator 25 is connected to the transistor Tr1.
The emitter of 1 is connected to the gate of FET Q1.
A diode D11 is provided between the emitter and collector of the transistor Tr11, the emitter of the transistor Tr11 is connected to the anode of the diode D11, and the collector is connected to the cathode. Further, one terminal of the sub winding 16 is connected to the collector of the transistor Tr11 and is also connected to the cathode side of the zener diode ZD11 via the diode D13 and the resistor R13.

Similarly, in the voltage limiting circuit 23, the reference voltage generator 25 is connected to the base of the transistor Tr12 via the resistor R12, and the emitter of the transistor Tr12 is F.
It is connected to the gate of ETQ2. Transistor Tr
A diode D12 is provided between the emitter and collector of the transistor 12, the emitter of the transistor Tr12 is connected to the anode of the diode D12, and the collector is connected to the cathode. The other terminal of the sub winding 16 is
It is connected to the collector of the transistor Tr12.

The reason for providing the voltage limiting circuits 22 and 23 will be described below. The FETs Q1 and Q2 often have a low breakdown voltage of the gate of about 10 to 20 V, and the current doubler synchronous rectification circuit 1 of the first embodiment described above.
In the case of 4, the voltage generated from the sub winding 16 of the transformer 12 is proportional to the input voltage of the switching power supply device 10. Therefore, the upper limit of the input voltage of the switching power supply device 10 of the above embodiment is the current doubler synchronous rectification circuit 14 FE
Limited by the withstand voltage performance of the gates of TQ1 and Q2.

In the switching power supply device 10 of the above embodiment, one input capacitance Ciss of the FETs Q1 and Q2 is charged and the output from the transformer 12 is output while the voltage is output from the sub winding 16 of the transformer 12. By transferring half of the charged charge to the input capacitance Ciss of the other FET Q1 or Q2 during the period when there is no voltage,
1, Q2 is turned on. Here, in order for the FET to turn on, a voltage higher than a certain threshold is required. Therefore, even when there is no output voltage from the transformer 12, the FET cannot be turned on and the loss increases unless the voltage of the input capacitance Ciss is equal to or higher than the threshold voltage. The voltage of the input capacitance Ciss during the period when the output voltage of the transformer 12 is not present is half the voltage during which the voltage is output from the transformer 12. Input capacitance C while voltage is being output from the transformer 12
The voltage of iss is a value obtained by subtracting the forward voltage of the diode D1 or D2 from the voltage generated from the sub winding 16 of the transformer 12. That is, in the switching power supply device 10 of the above embodiment, the voltage generated from the sub winding 16 of the transformer 12 is a voltage obtained by adding the forward voltage of the diode D1 or the diode D2 to the voltage twice the threshold value of the FETs Q1 and Q2. The lower limit is the input voltage that can be generated.

As described above, the switching power supply device of the above embodiment is limited by the gate breakdown voltage and the threshold value of the synchronous rectification FETs Q1 and Q2.

Therefore, as in the second embodiment, the voltage limiting circuit 22, is connected to the gates of the FETs Q1 and Q2 for synchronous rectification.
By providing 23, it is possible to prevent a voltage exceeding the gate breakdown voltage of the FETs Q1 and Q2 from being applied to the gates of the FETs Q1 and Q2. Furthermore, the voltage limiting circuit 2
The set voltage of 2 and 23 is set to be equal to or more than twice the threshold value of the FETs Q1 and Q2, and the turn ratio of the sub winding 16 of the transformer 12 is adjusted so that the input voltage lower limit of the switching power supply device 20 is equal to or more than the set voltage. Voltage is the voltage limiting circuit 2
By adding 2 and 23, a switching power supply device having a wide input voltage range can be constructed.

Next, the operation of the switching power supply device 20 of this embodiment will be described. In this embodiment, the reference voltage generator 25 provided in common to the voltage limiting circuits 22 and 23.
Thus, in the voltage limiting circuit 22, the reference voltage is generated by the current supplied to the Zener diode ZD11 during the period when the positive voltage is generated in the non-dotted terminal of the sub winding 16 of the transformer 12. And transformer 1
In a period in which no voltage is generated in the second sub winding 16 or a positive voltage is generated in the dot side terminal of the sub winding 16 of the transformer 12, the Zener diode ZD
The reference voltage is output by the capacitor C11 connected in parallel with the reference voltage 11.

Then, during the period in which the positive voltage is generated in the dotless terminal of the sub winding 16 of the transformer 12,
The operation is to charge the input capacitance Ciss of the FET Q1.
At this time, the current that charges the input capacitance Ciss of the FET Q1 passes from the collector to the emitter of the transistor Tr11. In order for a current (hereinafter, collector current) to flow from the collector of the transistor Tr11, a current (hereinafter, base current) needs to flow from the base to the emitter.

Since the voltage of the input capacitance Ciss of the FET Q1 is lower than the voltage of the reference voltage generator 25 at the beginning of the period when a positive voltage is generated at the non-dotted terminal of the sub winding 16 of the transformer 12. And the transistor T
Since the collector current also flows in r11 due to the base current flowing, a charging current flows in the input capacitance Ciss of the FET Q1.

Then, when the charging of the input capacitance Ciss of the FET Q1 progresses and the voltage of the input capacitance Ciss increases and approaches the reference voltage, the base current of the transistor Tr11 decreases. When the value obtained by subtracting the threshold voltage of the base of the transistor Tr11 (about 0.5 V in a general transistor) from the reference voltage is reached, the base current of the transistor Tr11 stops flowing and the base current stops, so that the collector current stops. To do. Therefore, regardless of the voltage generated in the sub winding 16, the input capacitance Ciss of the FET Q1 is
From the reference voltage of the reference voltage generator 25 to the transistor Tr1
It is not charged more than the value obtained by subtracting the threshold voltage of the base of 1.

While the input capacitance Ciss of the FET Q1 is being charged, the input capacitance Ciss of the FET Q2 is discharged. The FET Q2 is discharged through a diode D12 connected in parallel to the collector and emitter of the transistor Tr12.

In the voltage limiting circuit 23, the sub winding 1
When the polarity of 6 is opposite to the above, the same operation as described above is performed. Further, the discharge of the FET Q1 is
11 through a diode D11 connected in parallel to the collector and emitter.

The switching power supply device 20 of this embodiment
According to this, a switching power supply device having a wide input voltage range can be configured without being limited by the breakdown voltage performance of the gate of the synchronous rectification FET.

The reference voltage generator 25 of this embodiment is used.
As shown in FIG. 5, a pair of Zener diodes ZD1
2 and 13, the Zener voltage may be used as a reference voltage, and a voltage higher than the reference voltage may not be applied to the bases of the transistors Tr11 and Tr12. With this, the same effect can be obtained, and the circuit configuration can be simplified.

Next, the third embodiment of the present invention will be described with reference to FIG.
It will be explained based on. Here, the same members as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. In the current doubler synchronous rectification circuit 34 of the switching power supply device 30 of this embodiment, as compared with FIG. 4, the transistor Tr11 and the diode D11 are connected to the FET Q11, and the transistor Tr1.
2 and diode D12 have been replaced by FET Q12. The difference between the functions of the transistor Tr11 and the FET Q11 is that the transistor Tr11 is an element through which a collector current flows when a base current flows, while the FE
The TQ11 is an element in which a current (hereinafter referred to as a drain current) flows from the drain to the source when the gate voltage is higher than the source voltage. Then, in the operation of charging the input capacitance Ciss of the FET Q1, in the beginning of the period when the positive voltage is generated in the sub winding 16,
The voltage of the input capacitance Ciss of TQ1 is equal to the reference voltage generator 2
Since it is lower than the voltage of 5, the FET of the voltage limiting circuit 22
The gate voltage of Q11 is higher than the source voltage, and the drain current flows. Because drain current flows, FETQ
The charging current flows through the input capacitance Ciss of 1.

When the input capacitance Ciss of the FET Q1 is further charged and the voltage of the input capacitance Ciss rises and approaches the reference voltage, the source voltage of the FET Q11 rises.
The voltage of the input capacitor Ciss changes from the reference voltage to the FET Q11.
When it reaches the value obtained by subtracting the threshold voltage of the gate of
The drain current of 1 stops flowing. Therefore, sub winding 1
Regardless of the voltage generated at 6, the input capacitance Ciss of the FET Q1 is FE from the reference voltage of the reference voltage generation unit 25.
It will not be charged more than the value obtained by subtracting the threshold voltage of the gate of TQ11.

The input capacitance Ciss of the FET Q2 is discharged while the input capacitance Ciss of the FET Q1 is being charged. The discharge of the FET Q2 is performed through the parasitic diode of the FET Q12.

Further, in the other voltage limiting circuit 23 of FIG. 6, when the polarity of the sub winding 16 is opposite to the above,
The same operation as above is performed, and the discharge of the FET Q1 is
Through the parasitic diode.

The switching power supply device 30 of this embodiment
Also, the switching power supply device having a wide input voltage range can be configured without being limited to the synchronous rectification FET. Further, the configurations of the voltage limiting circuits 22 and 23 can be formed more simply.

The reference voltage generator 25 of this embodiment is used.
As shown in FIG. 7, a pair of Zener diodes ZD1
2 and 13, the Zener voltage may be used as a reference voltage and a voltage higher than the reference voltage may not be applied to the gates of the FETs Q11 and Q12. With this, the same effect can be obtained, and the circuit configuration can be simplified.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. Here, the same members as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. The current doubler synchronous rectification circuit 44 of the switching power supply device 40 of this embodiment has the circuit configuration shown in FIG.
6 and 27 are provided to solve the problem when the input capacitance Ciss of the synchronous rectification FETs Q11 and Q12 becomes unbalanced.

Here, this problem will be described. F
Assuming that the input capacitance Ciss of the ETQ1 is larger than the Ciss of the FET Q2, considering a period in which a positive voltage is generated at the terminal with a dot on the secondary side of the transformer 12, the FET Q1 is off and the FET Q2 is on during this period. There must be. At the beginning of this period, the input capacitance Ciss of the FET Q1 is discharged and the input capacitance Ciss of the FET Q2 is charged. The discharging current of the input capacitance Ciss of the FET Q1 is the charging current of the FET Q2. Where FET
When the input capacitance Ciss of Q2 reaches the voltage determined by the voltage limiting circuit 23, the charging current of the FET Q2 stops. The input capacitance Ciss of the FET Q1 is the FET
If it is larger than the input capacitance Ciss of Q2, the charging current of the FET Q2 (discharge current of the FET Q1) will stop before the discharge of the input capacitance Ciss of the FET Q1 is completed.

As a result, a voltage remains in the gate of the FET Q1. If this voltage is higher than the threshold voltage of the gate of the FET Q1, the FET Q1 cannot be turned off. During this period, a positive voltage is generated in the secondary dot terminal of the transformer 12, and the FET Q1,
When both Q2 are turned on, the secondary side of the transformer 12 is in the same state as being short-circuited, and in the worst case, the switching power supply device is destroyed.

Therefore, in this embodiment, the FE for synchronous rectification is used.
The discharge circuits 26 and 27 are connected to TQ1 and Q2.

The switching power supply device 40 of this embodiment
The operation will be described with reference to FIG. First, it is assumed that a positive voltage is generated at the dot terminal of the secondary winding of the transformer 12. At this time, since the base current flows in the transistor Tr21, the transistor Tr21 can flow the collector current, and the charge stored in the input capacitance Ciss of the FET Q1 is changed to the FET Q1.
, The collector of the transistor Tr21, the emitter, and the source of the FET Q1 to be discharged. As a result, the FET Q1 is turned off.

Then, the input capacitance Ciss of the FET Q2
Causes a charging current to flow by passing through the transformer 12, the voltage limiting circuit 23, the gate and the source of the FET Q2, the anode and the cathode of the diode D1, and the transformer 12. When the input capacitance Ciss of the FET Q2 reaches the voltage set by the voltage limiting circuit 23 in the process of flowing the charging current, the charging current stops flowing.

Next, during the period when no voltage is generated in the secondary winding of the transformer 12, the transistors Tr21 and Tr22 are
FE does not work together (the discharge circuit does not work)
The charge of the input capacitance Ciss of TQ2 moves to the FET Q1, and both the FETs Q1 and Q2 are turned on.

When a positive voltage is generated at the non-dotted terminal of the secondary winding of the transformer 12, the transistor Tr22 is connected to the transistor Tr21, as described above.
The FET Q2 operates similarly to the FET Q1.

The switching power supply device 40 of this embodiment
According to, the discharge current of the synchronous rectification FETs Q1 and Q2 is
The other FETQ is discharged by the discharge circuits 26 and 27.
Even if there is an imbalance in each input capacitance Ciss without being affected by the charging current of 1 or Q2, the above-mentioned problem does not occur. Furthermore, each input capacitance C
Since the discharge of iss is performed through the discharge circuits 26 and 27, a large current can momentarily flow, and the FETs Q1 and Q2 can be turned off quickly.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
0, it demonstrates based on FIG. Here, the same members as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. The current doubler synchronous rectification circuit 54 of the switching power supply device 50 of this embodiment includes a current doubler synchronous rectification circuit 54 on the secondary side of the transformer 12, and the current doubler synchronous rectification circuit 54 is the same as the above embodiments. And the FET 12 is provided with two sets of sub windings 36 and 37.

The sub windings 36 and 37 are one of the sub windings 3
One end of FET 6 and the gate of one FET Q1 are connected via a capacitor C1, and the other end of sub winding 36 and FET Q1
Source is connected. Furthermore, one sub winding 3
The other end of 6 is connected to one end of the other sub winding 37. Further, the other end of the other sub winding 37 and the other FET Q
2 gate is connected via another capacitor C2,
One end of the other sub winding 37 is connected to the source of the FET Q2. Then, as in the above embodiment, one FE
The diode D1 is connected between the gate and the source of TQ1, and the diode D2 is connected between the gate and the source of the other FET Q2. The anodes of the diodes D1 and D2 are connected to the sources of the FETs Q1 and Q2, and the cathode is It is connected to the gates of FETs Q1 and Q2.

Next, the operation of the switching power supply device 50 of this embodiment will be described with reference to FIG. Here, (a) of FIG. 11 is the output voltage VT on the secondary side of the transformer 12, (b) is the output voltage Vsub1 of the sub winding 36,
(C) is the output voltage Vsub2 of the sub winding 37, (d) is the gate-source voltage VGS (Q1) of the FET Q1,
(E) is the gate-source voltage VGS (Q
2) and (f) are the current I (L1) of the coil L1, the (g) is the current I (L2) of the coil L2, (h) is the drain current I (Q1) of the FET Q1, and (i) is the drain current of the FET Q2. I (Q2).

In the period A, the current doubler synchronous rectification circuit 54 of this embodiment outputs a positive voltage to the terminal with the dot on the secondary side of the transformer 12, and at this time, the voltage of the sub winding 36 of the transformer 12 causes , The input capacitance Ciss of the FET Q1 is discharged. The discharge path at this time flows through the sub winding 36 of the transformer 12, the source of the FET Q1, the gate, the capacitor C1, and the sub winding 36 of the transformer 12. And the input capacitance Ci of the FET Q1
When the discharge of ss is completed, the current path flows through the sub winding 36 of the transformer 12, the anode to the cathode of the diode D1, the capacitor C1, and the sub winding 36 of the transformer 12. Then, when the voltage of the capacitor C1 reaches a value obtained by subtracting the forward voltage of the diode D1 from the voltage of the sub winding 36, the current stops.

Further, depending on the voltage of the sub winding 37, the FET
The input capacitance Ciss of Q2 is charged. The current path at this time is the sub winding 37 of the transformer 12 and the capacitor C.
2. From the gate of the FET Q2 to the source and the sub winding 37 of the transformer 12. Where capacitor C2
Is charged with a voltage generated from the sub winding 37 during a period (a period C) in which the positive voltage is output from the dot terminal of the sub winding 37. Therefore, the sum of the voltages of the sub winding 37 and the capacitor C2 is applied to the input capacitance Ciss of the FET Q2. In the period A, the FETQ1 is turned off and the FETQ2 is turned on by the above operation.

In the period B, the voltage is not output to the secondary side of the transformer 12, and the sub windings 36 and 3 of the transformer 12 are stopped.
The voltage is no longer output from 7. And FETQ
The capacitors C1 and C are connected to the input capacitors Ciss of Q1 and Q2.
Only the voltage stored in 2 is applied. During this period, the FETs Q1 and Q2 are both turned on by the above operation.

Next, in the period C, a positive voltage is output to the non-dotted terminal on the secondary side of the transformer 12, and the voltage opposite to that in the period A is output from the sub windings 36 and 37 of the transformer 12. To be done. Then, by the voltage of the sub winding 36, F
The input capacitance Ciss of ETQ1 is charged. At this time, the current path flows from the sub winding 36 of the transformer 12, the capacitor C1, and the gate of the FET Q1 to the source and the path of the sub winding 36. Here, the capacitor C1 is charged with the voltage generated from the sub winding 36 in the period A. Therefore, the input capacitance Ciss of the FET Q1 is
And the voltage of the capacitor C1 is applied.

Further, depending on the voltage of the sub winding 37, FETQ
The two input capacitors Ciss are discharged. The current path at this time flows through the sub winding 37 of the transformer 12, the source of the FET Q2, the gate, the capacitor C2, and the sub winding 37. Here, when the discharge of the input capacitance Ciss of the FET Q2 is completed, the current path flows through the sub winding 37, the anode to the cathode of the diode D2, the capacitor C2, and the sub winding 37. When the voltage of the capacitor C2 reaches the value obtained by subtracting the forward voltage of the diode D2 from the voltage of the sub winding 37, the current flow is stopped. In period C,
With the above operation, the FET Q1 is turned on and the FET Q2 is turned off.

Then, in the period D, the transformer 12
No voltage is output to the secondary side of the above, and the same operation as in the above period B is performed.

The switching power supply device 50 of this embodiment
According to the above, the FET can be turned on during the entire period when the current flows through the synchronous rectification FETs Q1 and Q2.
As a result, the current does not pass through the parasitic diode of the FET, and the loss due to this does not occur, and the efficiency of the switching power supply device 50 can be improved.

Next, a sixth embodiment of the present invention will be described with reference to FIG.
It will be described based on 2. Here, the same members as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. The current doubler synchronous rectification circuit 54 of the switching power supply device 60 of this embodiment is provided with the voltage limiting circuits 22 and 23 in the circuit of the fifth embodiment, as in the second embodiment. The voltage limiting circuits 22 and 23 are FETs Q1 and Q.
It outputs a voltage equal to or lower than the gate breakdown voltage of 2.
Also according to this embodiment, a switching power supply device having a wide input voltage range can be configured.

In the above embodiment, the synchronous rectifying element has n-
Channel MOS-FET was used, but p channel M
The current doubler synchronous rectification circuit may be configured using OS-FET. Further, a switching element having a similar function other than the MOS-FET may be used.

[0072]

According to the switching power supply device of the present invention, the synchronous rectification element can be turned on during the entire period in which the current flows through the synchronous rectification device, and there is no loss due to the flow of the parasitic diode. The efficiency can be improved.

Further, by providing the voltage limiting circuit in the preceding stage of the gate of the synchronous rectifying element, a switching power supply device having a wide input voltage range can be constructed.

Further, by providing the discharge circuit in front of the gate of the synchronous rectifying element, even if there is an imbalance in each input capacitance of the synchronous rectifying element, there is no problem such as the fact that the synchronous rectifying element cannot be turned off. . Further, a large current can momentarily flow when discharging each input capacitance, and the synchronous rectifying element can be turned off promptly.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of a switching power supply device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the switching power supply device of this embodiment.

FIG. 3 is a schematic circuit diagram of a switching power supply device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a voltage limiting circuit of the switching power supply device of this embodiment.

FIG. 5 is a circuit diagram showing another example of the voltage limiting circuit of the switching power supply device of this embodiment.

FIG. 6 is a circuit diagram of a switching power supply device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing another example of the voltage limiting circuit of the switching power supply device of this embodiment.

FIG. 8 is a schematic circuit diagram of a switching power supply device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a voltage limiting circuit and a discharging circuit of the switching power supply device of this embodiment.

FIG. 10 is a schematic circuit diagram of a switching power supply device according to a fifth embodiment of the present invention.

FIG. 11 is a timing chart showing the operation of the switching power supply device of this embodiment.

FIG. 12 is a schematic circuit diagram of a switching power supply device according to a sixth embodiment of the present invention.

FIG. 13 is a schematic circuit diagram of a switching power supply device including a conventional current doubler synchronous rectification circuit.

FIG. 14 is a timing chart showing the operation of the conventional switching power supply device.

FIG. 15 is a diagram showing a parasitic diode and a parasitic capacitance of a MOS-FET.

[Explanation of symbols]

10 Switching power supply 12 transformers 14 Current doubler synchronous rectification circuit 16 sub winding 22, 23 Voltage limiting circuit 25 Reference voltage generator 26, 27 discharge circuit

[Procedure amendment]

[Submission date] December 28, 2001 (2001.12.
28)

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14

Claims (7)

[Claims] 1. A push-pull circuit, a half-bridge circuit,
Alternatively, a drive circuit for generating a voltage similar to that when driven by these circuits on the secondary side of the transformer is provided on the primary side of the transformer, and a current doubler synchronous rectification circuit is provided on the secondary side of the transformer. In a switching power supply device for performing synchronous rectification by configuring a synchronous rectification element of this current doubler synchronous rectification circuit by a MOS-FET or an element having a function similar to this, a transformer is provided with one set of sub-windings. One end of the sub-winding is connected to the gate of one synchronous rectifying element, the other end of the sub-winding is connected to the gate of the other synchronous rectifying element, and a diode is connected between the gate and the source of the one synchronous rectifying element. Connect the diode between the gate and the source of the other synchronous rectifier,
Each diode has an anode connected to the source of each synchronous rectification element and a cathode connected to the gate of each synchronous rectification element. 2. The switching device according to claim 1, further comprising a voltage limiting circuit provided between the terminal of the sub winding and the gate of the synchronous rectifying element, the voltage limiting circuit outputting a voltage equal to or lower than a breakdown voltage of the gate. Power supply. 3. The voltage limiting circuit includes a transistor provided between the terminal of the sub winding and the gate of the synchronous rectifying element, the emitter of the transistor is connected to the gate of the synchronous rectifying element, and the collector is the above. It is connected to the terminal of the sub winding, the reference voltage generator is connected to the base of the transistor, and the diode is connected between the emitter and collector of the transistor.The diode connects the anode to the emitter of the transistor and the collector to the collector. The switching power supply device according to claim 2, wherein a cathode is connected to the. 4. The voltage limiting circuit comprises a MOS-FET between the terminal of the sub winding and the gate of the synchronous rectifying element.
The source of the MOS-FET is connected to the gate of the synchronous rectifier, the drain is connected to the terminal of the sub-winding, and the reference voltage generator is connected to the gate of the MOS-FET. The switching power supply device according to claim 2. 5. The switching power supply device according to claim 2, wherein a discharge circuit is provided between the voltage limiting circuit and the gate of the synchronous rectifying element. 6. A push-pull circuit, a half-bridge circuit,
Alternatively, a drive circuit for generating a voltage similar to that when driven by these circuits on the secondary side of the transformer is provided on the primary side of the transformer, and a current doubler synchronous rectification circuit is provided on the secondary side of the transformer. In a switching power supply device for performing synchronous rectification by configuring a synchronous rectification element of this current doubler synchronous rectification circuit with a MOS-FET or an element having a function similar to this, in the transformer, two sets of sub windings are provided. , One end of the sub-winding and the gate of the one synchronous rectifying element are connected via a capacitor, the other end of the one sub-winding is connected to the source of the synchronous rectifying element,
The other end of the one sub-winding is connected to one end of the other sub-winding, and the other end of the other sub-winding is connected to the gate of the other synchronous rectification element via another capacitor, One end of the other sub-winding is connected to the source of the other synchronous rectifier, a diode is connected between the gate and the source of the one synchronous rectifier, and the gate and the source of the other synchronous rectifier are connected. A switching power supply device characterized in that an anode is connected to a source of each synchronous rectifying element and a cathode is connected to a gate of each synchronous rectifying element. 7. The switching power supply device according to claim 6, wherein a voltage limiting circuit that outputs a voltage equal to or lower than the breakdown voltage of the gate is provided between the capacitor and the gate of the synchronous rectifying element.