JP2003188772A - Synchronizing detector and portable terminal having the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronizing detector capable of accelerating processing or to provide a synchronizing detector and a portable terminal having the same in which a frame phase can be detected in any arbitrary phase. <P>SOLUTION: By separately providing a correlative value holder shared with a memory for integration in the conventional configuration, pipeline processing is enabled. Besides, a memory used corresponding to a storage range is replaced with a plurality of memories capable of digital received spread signals of single- fold over-sampling for one symbol. With the replacement, the slot phase is detected in the arbitrary phase and a plurality of phases are processed within a slot time. Further, by changing the order of processing, memories can be reduced. Besides, the inside of the slot is divided into a plurality of time ranges and by fixing a timing of processing, a circuit can be simplified. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronism detector, and more particularly to a circuit for executing synchronism acquisition necessary for despreading a spectrum in a communication system using a spread spectrum communication system, particularly a direct spread system. The present invention relates to a mobile terminal having such a synchronization detector.

[0002]

2. Description of the Related Art In a spread spectrum communication system, particularly a direct spread system, a reception spread signal received by a receiver on the receiving side is A / D converted, and a digital received spread signal which is A / D converted and Despreading the digital received spread signal with the duplication of the spreading code used to perform the spread spectrum. In order to perform despreading, it is necessary for the receiving side to detect the spreading code used when the transmitting side performs spread spectrum and the transmission phase of the spreading code. On the receiving side, the slot synchronization is detected using the slot synchronization signal transmitted in the leading symbol of each slot, and the frame synchronization is detected using the frame synchronization signal.

In the conventional method, when slot synchronization detection is performed after frame synchronization detection, a digital reception spread signal is accumulated and processed using the configuration shown in FIG. A
A / D converter 100 enables N times oversampling
The / D converted digital reception spread signal is stored in the memory 101 so as to include the phase detected by the slot synchronization detection. Using the control circuit 104, the spreading factor S is calculated for every N signals starting from the digital reception spreading signal having the phase detected by the frame synchronization detection from the digital reception spreading signal stored in the memory 101.
F pieces are read out and input to the matched filter 102. The control circuit 104 is used to control the code generator 103 to generate a code for frame synchronization detection and set it in the matched filter 102.

The code generator 103 sequentially generates codes of the type used for slot synchronization and sets them in the matched filter 102. The correlation value output from the matched filter 102 for each code set by the code generator 103 is held in the integration memory 105. Using the integration correspondence table 106, the integration memory 1
One of the correlation values held in 05 is selected, and one of the values also held in the integration memory 105 is selected, added, and written in the integration memory 105. Of the phases detected by the slot phase detection, the ones stored in the memory 101 are repeatedly processed.

[0005]

However, in the above conventional method, since the correlation value is held in the integration memory 105, the correlation value cannot be stored and integrated at the same time. I will end up. Further, in order to perform the slot phase detection for an arbitrary phase detected by the slot phase detection, it is necessary to store the digital reception spread signal oversampled by N times the slot time in the memory 101. It is difficult to realize because of the large number.

Therefore, an object of the present invention is to provide a synchronization detector capable of increasing the processing speed.
Another aspect of the present invention is to provide a synchronization detector capable of performing frame phase detection at an arbitrary phase, and a mobile terminal having such a synchronization detector.

[0007]

In order to achieve the above object, in the present invention, a correlation value holder which is shared with the integration memory in the conventional configuration is separately provided, thereby enabling pipeline processing and high-speed processing. I am trying to make it. In addition, in another aspect of the present invention, in addition to the above-mentioned configuration, the memory used according to the storage range is replaced with a plurality of memories capable of storing 1-times oversampling digital reception spread signal for one symbol. Is being replaced. By this replacement, slot phase detection can be performed with an arbitrary phase, and a plurality of phases can be processed within the slot time. Furthermore, in another aspect of the present invention, the memory is reduced by changing the processing procedure. Also,
In another aspect of the present invention, the circuit is simplified by dividing the slot into a plurality of time ranges and fixing the processing timing.

That is, according to the present invention, an A / D converter for converting a received spread signal into a digital received spread signal, a memory for storing the digital received spread signal, and a matching device for responding to an output signal of the memory. A filter, a code generator for generating a code for detecting the correlation of the digital reception spread signal with the matched filter, and a correlation value holder for holding the correlation value output from the matched filter, An integration correspondence table for showing correspondence for selecting one of the correlation values held in the correlation value holder, an integration memory for holding a result of integrating the correlation value, and the integration memory A correlation detector for performing phase detection using the integrated value held at, the A / D converter, a memory for accumulating the digital reception spread signal, the matched filter, the Signal generator, the correlation value holder, the integration correspondence table, the integration memory, a control circuit for controlling the correlation detector and performing pipeline processing using the correlation holder, synchronization A detector is provided.

With this configuration, the processing speed can be increased.

Further, according to the present invention, an A / D converter for converting a reception spread signal into a digital reception spread signal, a plurality of memories for storing the digital reception spread signal, a matched filter, and the plurality of memories. A switch for receiving an output signal of the memory and selecting an input signal to the matched filter; a code generator for generating a code for detecting the correlation of the digital reception spread signal by the matched filter; Correlation value holder for holding the correlation value output from the matched filter, an integration correspondence table for showing the correspondence to select one of the correlation values held in the correlation value holder, the correlation value Integration memory for holding the result of integration, a correlation detector for performing phase detection using the integration value held in the integration memory, the A / D converter, and the digital Controlling a plurality of memories for accumulating spread spectrum signals, the matched filter, the switch, the code generator, the correlation value holder, the integration correspondence table, the integration memory, the correlation detector, A synchronization detector having a control circuit for controlling the synchronization detection at an arbitrary phase by converting the reception diffusion signal into the digital reception diffusion signal and then storing it in the plurality of memories is provided.

With this configuration, slot phase detection can be performed with an arbitrary phase and a plurality of phases can be processed within the slot time.

Further, according to the present invention, an A / D converter for converting a reception spread signal into a digital reception spread signal, a plurality of memories for storing the digital reception spread signal, a matched filter, and the plurality of memories. A switch for accepting the output signal of and selecting the input signal to the matched filter,
A code generator for generating a code for detecting the correlation of the digital received spread signal with the matched filter;
A correlation value holder for holding the correlation value output from the matched filter, and an integral correspondence table for showing the correspondence to select one of the correlation values held in the correlation value holder, An integration memory for holding a result of integrating the correlation value, a correlation detector for performing phase detection using the integration value held in the integration memory, and the A / D
Converter, a plurality of memories for accumulating the digital reception spread signal, the matched filter, the switch, the code generator, the correlation value holder, the integration correspondence table, the integration memory, the correlation detector Control so that the reception spread signal is converted to the digital reception spread signal, accumulated in the plurality of memories, and sequentially processed from the end of accumulation, thereby performing synchronization detection at an arbitrary phase. And a circuit.

With this configuration, the memory can be reduced.

Further, according to the present invention, an A / D converter for converting a reception spread signal into a digital reception spread signal, a plurality of memories for storing the digital reception spread signal, a matched filter, and the plurality of memories. A switch for receiving an output signal of the memory and selecting an input signal to the matched filter; a code generator for generating a code for detecting the correlation of the digital reception spread signal by the matched filter; Correlation value holder for holding the correlation value output from the matched filter, an integration correspondence table for showing the correspondence to select one of the correlation values held in the correlation value holder, the correlation value Integration memory for holding the result of integration, a correlation detector for performing phase detection using the integration value held in the integration memory, the A / D converter, and the digital Controlling a plurality of memories for accumulating spread spectrum signals, the matched filter, the switch, the code generator, the correlation value holder, the integration correspondence table, the integration memory, the correlation detector, A control circuit for controlling the synchronization detection in an arbitrary phase so as to divide the time in a slot and process it by converting the reception spread signal into the digital reception spread signal and then storing it in the plurality of memories. A sync detector is provided.

With this configuration, the circuit can be simplified.

Further, according to the present invention, there is provided a mobile terminal having any one of the above synchronization detectors.

With this configuration, the same effect as that described for the synchronization detector can be obtained in the mobile terminal.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 shows a first embodiment of a synchronization detector according to the present invention.
It is a block diagram showing an embodiment of. The sync detector includes an A / D converter 200 responsive to the received spread signal, and an A / D converter 200.
A memory 201 that stores the output digital signal of the A / D converter 200, a matched filter 202 that responds to the signal read from the memory 201, a code generator 203 that generates a code for frame synchronization detection, and a matched filter Correlation value holder 205 responsive to output signal, integration correspondence table 206
, Integration memory 207, correlation detector 208, A / D
Converter 200, memory 201, matched filter 202, code generator 203, correlation value holder 205, integration correspondence table 20
6, a memory for integration 207, and a control circuit 204 for controlling each of the correlation detectors 208. Note that, in FIG. 1 and FIGS. 2 and 3 showing other embodiments described later, the control signal from the control circuit 204 is shown by a dotted line. The control circuit 204 can be configured by a CPU (central processing unit) not shown. In this case, a program for instructing the operation of the CPU is stored in advance in the ROM (not shown), and the CPU performs the following control operation according to the program. An appropriate interface is provided between the CPU and each controlled circuit as needed.

The sync detector operates as follows. A
A / D converter 200 for N times oversampling
The / D converted digital reception spread signal is stored in the memory 201 so as to include the phase detected by the frame synchronization detection. Using the control circuit 204, the spreading factor S is calculated for every N digital spreading signals having the phase detected by the slot synchronization detection from the digital spreading signals stored in the memory 201.
The data corresponding to F (for example, 256) are read out and input to the matched filter 202. The control circuit 204 is used to control the code generator 203 to generate a code for frame synchronization detection and set it in the matched filter 202. Code generator 20
3 sequentially generates the types of codes used for frame synchronization,
The matched filter 202 is set.

The correlation value output from the matched filter 202 for each code set by the code generator 203 is stored in the correlation value holder 2.
Hold at 05. Using the integration correspondence table 206, one of the correlation values held in the correlation value holder 205 is selected, and one of the values held in the integration memory 207 is selected, and the values are added and integrated. Write to the memory for use 207. The correlation detector 208 detects the phase using the integrated value stored in the integration memory 207. Of the phases detected by the slot phase detection, the ones stored in the memory 201 are repeatedly processed. The processing timing is shown in FIG.

<Second Embodiment> FIG. 2 is a block diagram showing a second embodiment of the synchronization detector according to the present invention. Explaining only the points different from the first embodiment in FIG. 1, the memory 101 in FIG. 2 is replaced with a combination of a memory group 301 and a switch 309 for switching its output signal and supplying it to a matched filter 302. The memory group 301 is
Two memory planes (hereinafter referred to as memory plane 1 and memory plane 2)
And each memory surface 1, 2 has M memories (M
Indicates the number of memory banks and has positive integers 11 to M1 and 12 to M2 corresponding to the maximum number of simultaneous processes.
The sync detector operates as follows. The reception spread signal received on the receiving side is A / D converted into an N-fold oversampling digital reception spread signal using the A / D converter 300. Under the control of the control circuit 304, 1 is changed from the memory 11 of the memory group 301 to the memory K1 (1 ≦ K ≦ M) for the K phases detected by the slot phase detection.
Accumulation of digital reception spread signal is performed by double oversampling. In the next slot, the digital reception spread signals stored in the memory K1 to the memory K1 are sequentially switched to the switching unit 30.
The memory i1 (1 ≦ i ≦ K) is selected at 9 and the 1 × oversampling data accumulated in the memory i1 is input to the matched filter 302. Further, the digital reception spread data is stored using the memory surface 2.

Under the control of the control circuit 304, the code generator 303 sequentially generates the codes necessary for despreading, and sets them in the matched filter 302. Matched filter 302
Then, the correlation values of the 1 × oversampling data for one symbol read from the memory i1 and the code sequentially generated by the code generator 303 are obtained, and the correlation value holder 30
Hold at 5. Using the integration correspondence table 306, one of the values held in the integration memory 307 and one of the values held in the correlation value holder 305 are added and saved in the integration memory 307. . The above processing is performed by alternately using the memory surface 1 and the memory surface 2 of the memory group 301. The integrated value held in the integration memory 307 is input to the correlation detector 308 to detect the frame phase. The processing timing is shown in FIG.

<Third Embodiment> FIG. 3 is a block diagram showing a third embodiment of the synchronization detector according to the present invention. Explaining only the points different from the first embodiment of FIG. 1, the memory 101 of FIG. 1 is replaced with a combination of a memory group 401 and a switch 409 for switching its output signal and supplying it to a matched filter 402. The sync detector operates as follows. Received spread signal received on the receiving side is A / D
The converter 400 is used to perform A / D conversion into a digital reception spread signal of N times oversampling. Under the control of the control circuit 404, the digital received spread signal is obtained by oversampling the K phases detected by the slot phase detection from each memory 1 of the memory group 401 to the memory K (1 ≦ K ≦ M) by a factor of 1. Accumulation of. Of the memories 1 to K, the memory i (1 ≦ i ≦ K) is selected by the switch 409 in order from the end of the accumulation of the digital reception spread signal, and the 1 × oversampling data accumulated in the memory i is matched. Input to the filter 402. When the matched filter 402 is being input from another memory, the matched filter 402 is put in a queue and the matched filter 402 is input as soon as the previous process is completed.
To enter.

Under the control of the control circuit 404, the code generator 403 sequentially generates the codes required for despreading, and sets them in the matched filter 402. Matched filter 402
Then, the correlation value of the 1-times oversampling data for one symbol read from the memory i and the code sequentially generated by the code generator 403 are obtained, and the correlation value holder 405 is used.
Hold on. Integration memory 4 using integration correspondence table 406
One of the values held in 07 and the correlation value holder 4
One of the values held in 05 is added and stored in the integration memory 407. The integrated value held in the integration memory 407 is input to the correlation detector 408 to detect the frame phase. The processing timing is shown in FIG.

<Fourth Preferred Embodiment> A fourth preferred embodiment of a synchronization detector according to the present invention is shown in the same block diagram as FIG. 3 showing the third preferred embodiment. The sync detector operates as follows. The received spread signal received at the receiving side is A
Using the / D converter 400, A / D conversion is performed on the N-fold oversampling digital reception spread signal. Control circuit 40
By the control from 4, the digital reception spread signal is stored in the memory group 401 from the memory 1 to the memory K (1 ≦ K ≦ M) by 1 time oversampling for the K phases detected by the slot phase detection. To do. Memory group 401
Of the memories 1 to K, the one in which the accumulation of the digital reception spread signal is completed in the first division of the slot is selected by the switch 409 in the next division, and the 1 × oversampling data is sequentially input to the matched filter 402. To do.

Under the control of the control circuit 404, the code generator 403 sequentially generates the codes required for despreading, and sets them in the matched filter 402. Matched filter 402
Then, the 1-fold oversampling data for one symbol read from the memory and the correlation value of the code sequentially generated by the code generator 403 are obtained and held in the correlation value holder 405. Using the integration correspondence table 406, the integration memory 40
One of the values held in 7 and the correlation value holder 40
One of the values held in 5 is added and stored in the integration memory 407. The integrated value held in the integration memory 407 is input to the correlation detector 408 to detect the frame phase. The processing timing is shown in FIG.

In the above embodiment, the sync detector has been described.
It can be applied to mobile terminals such as S and PDA to process digital reception spread signals.

[0028]

As described above, according to the present invention, when the digital reception spread signal is processed in the sync detector,
By independently providing a means for holding the correlation value obtained by the matched filter, the processing speed can be increased. Also, when processing the digital received spread signal,
By accumulating in a plurality of memories, frame phase detection can be performed in an arbitrary phase. Further, by providing the mobile terminal having the synchronization detector having the above configuration, the same effect can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment and a fourth embodiment of the present invention.

FIG. 4 is a timing chart according to the first embodiment of the present invention.

FIG. 5 is a timing chart according to the second embodiment of the present invention.

FIG. 6 is a timing chart according to the third embodiment of the present invention.

FIG. 7 is a timing chart according to the fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional example.

[Explanation of symbols]

200, 300, 400 A / D converter 201 memory 202, 302, 402 Matched filter 203, 303, 403 Code generator 204, 304, 404 Control circuit 205, 305, 405 Correlation holder 206, 306, 406 Integration correspondence table 207, 307, 407 Integration memory 208, 308, 408 Correlation detector 301, 401 memory group 309,409 Switch

Claims (5)

[Claims] 1. An A / D converter for converting a reception spread signal into a digital reception spread signal, a memory for storing the digital reception spread signal, a matched filter responsive to an output signal of the memory, and the matching. A code generator for generating a code for detecting a correlation of the digital reception spread signal with a filter, a correlation value holder for holding a correlation value output from the matched filter, and the correlation value holder Integral correspondence table for indicating the correspondence for selecting any of the correlation values held in, an integration memory for holding the result of integrating the correlation value, and an integration held in the integration memory A correlation detector for performing phase detection using a value, the A / D converter, a memory for accumulating the digital reception spread signal, the matched filter, the code generator,
A synchronization detector comprising: the correlation value holder, the integration correspondence table, the integration memory, and a control circuit that controls the correlation detector to perform pipeline processing using the correlation holder. 2. An A / D converter for converting a reception spread signal into a digital reception spread signal, a plurality of memories for storing the digital reception spread signal, a matched filter, and output signals of the plurality of memories. A switch for accepting the input signal to the matched filter, a code generator for generating a code for detecting the correlation of the digital received spread signal with the matched filter, and output from the matched filter Correlation value holder for holding the correlation value, the integration correspondence table for showing the correspondence to select one of the correlation values held in the correlation value holder, the result of integrating the correlation value An integration memory for holding, a correlation detector for performing phase detection using the integrated value held in the integration memory, the A / D converter, and the digital reception spread signal A plurality of memories for accumulating, the matched filter, the switch, the code generator, the correlation value holder, the integration correspondence table, the integration memory, the correlation detector to control the received spread signal. A synchronization detector comprising: a control circuit that controls the synchronization detection in an arbitrary phase by converting the conversion signal into the digital reception spread signal and then storing it in the plurality of memories. 3. An A / D converter for converting a reception spread signal into a digital reception spread signal, a plurality of memories for storing the digital reception spread signal, a matched filter, and an output signal of the plurality of memories. A switch for selecting an input signal to the matched filter, a code generator for generating a code for detecting the correlation of the digital reception spread signal with the matched filter, and an output from the matched filter Correlation value holder for holding the correlation value, an integration correspondence table for showing the correspondence to select one of the correlation values held in the correlation value holder, the result of integrating the correlation value , A correlation detector for performing phase detection using the integrated value held in the integration memory, the A / D converter, and the digital reception spread signal. A plurality of memories for accumulating signals, the matched filter, the switch, the code generator, the correlation value holder, the integration correspondence table, the integration memory, the correlation detector, and the reception spread. A synchronization detection circuit having a control circuit for performing synchronization detection at an arbitrary phase by converting the signal into the digital reception spread signal, accumulating in the plurality of memories, and sequentially processing the accumulation-completed signals. vessel. 4. An A / D converter for converting a reception spread signal into a digital reception spread signal, a plurality of memories for storing the digital reception spread signal, a matched filter, and output signals of the plurality of memories. A switch for accepting the input signal to the matched filter, a code generator for generating a code for detecting the correlation of the digital received spread signal with the matched filter, and output from the matched filter Correlation value holder for holding the correlation value, the integration correspondence table for showing the correspondence to select one of the correlation values held in the correlation value holder, the result of integrating the correlation value An integration memory for holding, a correlation detector for performing phase detection using the integrated value held in the integration memory, the A / D converter, and the digital reception spread signal A plurality of memories for accumulating, the matched filter, the switch, the code generator, the correlation value holder, the integration correspondence table, the integration memory, the correlation detector to control the received spread signal. A synchronization detector having a control circuit for controlling the synchronization detection in an arbitrary phase by dividing the time into slots and processing the converted signals after the conversion into the digital reception spread signal and the storage in the plurality of memories. 5. A mobile terminal having the synchronization detector according to claim 1. Description: