JP2003188079A - Mask, manufacturing method therefor, and manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mask of high pattern precision which is stress-controlled and a manufacturing method therefor, and to provide a method for manufacturing a semiconductor device by which a minute pattern is transferred at high precision. <P>SOLUTION: A manufacturing method for a mask comprises a process where an internal stress distribution is calculated using the data of mask's material, structure, and a pattern, which is assumed as initial internal stress; a process where the displacement amount by which a plurality of calculation points on the mask move is calculated, which is required for the internal stress of the mask to dynamically balance, to acquire the optimum initial internal stress where the average value of displacement amounts of calculation points is minimum; a process which acquires a prescribed impurities addition amount which eliminates a difference, based on the relationship between a pre-examined impurities addition amount and a stress change, with the difference between the optimum initial internal stress and an initial internal stress acquired in advance at each calculation point; a process in which a transmission part and a blocking part are formed at a thin film; and a process to add impurities to the thin film by a prescribed impurities addition amount including a space distribution. The manufacturing method manufactures a mask, and a semiconductor device is manufactured using the mask. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask used for lithography or the like and a method for manufacturing the same, and a method for manufacturing a semiconductor device having a lithography process using the mask.

[0002]

2. Description of the Related Art As a next-generation exposure technique replacing photolithography, a transfer type exposure method using an electron beam, an X-ray or an ion beam has been developed. These new technologies have in common that a thin film region (hereinafter referred to as a membrane) is formed on a mask and a transfer pattern is arranged on the membrane.

The one in which the transfer pattern is formed by the holes of the membrane is called a stencil mask. On the other hand, a transfer pattern formed by a charged particle beam scatterer (or X-ray scatterer) such as a metal thin film is called a membrane mask. In order to realize next-generation exposure technology, it is essential to establish a mask manufacturing method with high positional accuracy.

[0004]

However, the film thickness distribution of the membrane, the stress that the scatterer exerts on the membrane in the membrane mask, or the stress release by providing holes in the membrane in the stencil mask, etc. This will cause unevenness. As described above, when the stress of the membrane becomes non-uniform, the positional accuracy of the pattern is significantly reduced (for example, M. Oda et al.,
Jpn. J. Appl. Phys. 31, 4189 (1992)).

As a solution to such a decrease in the positional accuracy of the pattern, there is a method of using a highly rigid material such as diamond for the membrane (for example, Japanese Patent Laid-Open No. 9-26).
No. 0251). However, highly uniform diamond thin films are difficult and expensive to manufacture. Further, in general, a membrane using diamond has extremely large internal stress. Therefore, the problem of pattern distortion is still unsolved, especially when there is significant sparseness in the pattern.

A method has also been proposed in which a "transfer function" for connecting a design position of a pattern and an actual position is experimentally obtained, and a pattern whose distortion is corrected by inverse conversion thereof is designed (Japanese Patent Laid-Open No. 8-203817). reference). However, according to this method, the mask needs to be manufactured twice, which requires time and cost.

On the other hand, as a method of manufacturing a mask from an SOI (silicon on insulator or semiconductor on insulator) wafer, a method of controlling the stress of the membrane by implanting ions such as boron into the silicon active layer has been proposed ( For example, Japanese Patent Laid-Open No. 2000-243
692). This method is excellent in that the ion implantation technology established in the semiconductor manufacturing process can be used as it is, and the number of manufacturing steps is small.

Further, Japanese Patent Laid-Open No. 10-260523,
JP-A-11-16804, JP-A-11-2636
No. 8 and Japanese Patent Application Laid-Open No. 11-54409 describe that in the process of manufacturing a stencil mask for an EB stepper, ions are uniformly implanted into the entire surface of a Si or SOI wafer to reduce stress.

However, even if the internal stress of the entire membrane is lowered by uniform ion implantation over the entire surface of the mask, the nonuniformity of the stress due to the density of the pattern still causes the displacement of the pattern. Also,
When the internal stress is reduced as a whole, although the in-plane displacement is reduced, the vertical out-of-plane strain due to gravity is increased.

A method is also known in which the stress of the membrane mask is adjusted by locally heating the metal scatterer using a laser (see Japanese Patent Application Laid-Open No. 9-306812). According to this method, it is possible to change the stress at each position instead of the entire surface of the mask, and the degree of freedom in stress control is great.

However, it takes a very long time to scan the laser while changing the irradiation amount on the entire surface of the mask. The spatial resolution of the laser is about 1 μm,
It is impossible to control the stress of the transfer pattern on the scale of several tens of nm, which is required for the next-generation exposure method. further,
When the mask material is a non-metal such as silicon, the stress change due to heating is small, so that the applicable material is limited.
Also, this method cannot be applied to stencil masks.

Japanese Unexamined Patent Publication No. 2001-100395 discloses that
It is described that a part of the membrane of the mask for X-ray lithography is removed to reduce strain caused by stress. However, it is difficult to remove a part of the membrane, and stress control based on accurate stress calculation is not disclosed.

The present invention has been made in view of the above problems, and therefore, the present invention aims to provide a mask and a method for manufacturing the mask, which can prevent deterioration of pattern accuracy due to imbalance of internal stress. And It is another object of the present invention to provide a method for manufacturing a semiconductor device that can transfer a fine pattern with high accuracy.

[0014]

In order to achieve the above object, a mask of the present invention has a thin film in which a transmission part and a blocking part of a charged particle beam or an electromagnetic wave are formed in a predetermined pattern. The thin film is non-uniformly doped with impurities so as to reduce the displacement of the pattern due to the internal stress.

Preferably, the transmission part is a hole formed in the thin film, and the blocking part is the thin film other than the hole. Alternatively, preferably, the thin film allows the charged particle beam or the electromagnetic wave to pass therethrough, and the blocking section is a portion where the charged particle beam or the electromagnetic wave scatterer is formed on the thin film.

In order to achieve the above object, the method of manufacturing a mask according to the present invention includes at least a mask having a thin film in which a transparent portion and a blocking portion of a charged particle beam or an electromagnetic wave are formed in a predetermined pattern. A step of calculating the internal stress distribution using the data of the material, the structure and the pattern and setting it as the initial internal stress, and a plurality of calculation points on the mask are moved to bring the internal stress of the mask into a mechanical equilibrium state. Calculating the amount of displacement, and the step of determining the internal stress distribution that minimizes the average value of the amount of displacement at the calculation point as the optimum initial internal stress, and the step of obtaining the difference between the optimum initial internal stress and the initial internal stress at each calculation point And a step of obtaining a predetermined impurity addition amount at each calculation point that eliminates the difference based on the relationship between the impurity addition amount and the stress change which has been examined in advance, and And having a step of forming a part, and adding a non-uniformly impurities into the thin film at the predetermined doping amount.

Preferably, in the step of obtaining the predetermined impurity addition amount, a predetermined ion implantation amount that eliminates the difference is calculated at each calculation point based on the relationship between the ion implantation amount and the stress change which has been examined in advance. Including the step of obtaining, the step of adding the impurity includes the step of implanting ions in the thin film non-uniformly with the predetermined amount of ion implantation. As a result, the pattern position accuracy of the mask used for lithography or the like can be made higher than in the conventional case.

Further, in order to achieve the above object, the method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device, which comprises a step of exposing a photosensitive surface to a charged particle beam or an electromagnetic wave through a mask, As the mask, a thin film in which a transmitting portion and a blocking portion of a charged particle beam or an electromagnetic wave are formed in a predetermined pattern is provided, and the thin film is non-uniform so as to reduce displacement of the pattern due to internal stress of the thin film. It is characterized in that a mask to which impurities are added is used. This makes it possible to transfer a fine pattern with higher accuracy in a next-generation exposure technique that uses an electron beam, an X-ray, or an ion beam.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a mask, a method of manufacturing the mask and a method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. The mask manufacturing method of this embodiment will be described with reference to the flowchart of FIG. The membrane before transfer pattern formation has a certain internal stress value σ ₀
have. For example, chemical vapor deposition (CVD)
The diamond thin film formed by the al vapor deposition method has a tensile stress of about several hundred MPa. In addition, the silicon active layer of the SOI wafer is several 10M.
It has a compressive stress of about Pa.

Since the internal stress value σ ₀ depends not only on the composition of the membrane and the synthesis method but also on the film thickness distribution, it is generally not a constant but a function of the position (x, y) on the membrane. The internal stress distribution σ ₀ (x, y) of the membrane can be experimentally determined by measuring the warp of the mask blank with a laser interferometer or a capacitance sensor (M. Oda
et al., Jpn. J. Appl. Phys. 34, 6729 (1995)). In the case of the stencil mask, the stress at the hole is zero, so the initial internal stress distribution σ (x, y) is expressed by the following equation (I).

[0021]

[Equation 1]

In the case of a membrane mask, the pattern part
The stress is not zero, the stress that the scatterer exerts on the membrane
Value is σ₀ Join (x, y). Initial internal stress distribution and mass
The relationship with the black structure is shown in FIGS. 2 and 3. Figure 2 (a)
The vertical axis of the graph is the internal stress σ ₀ The horizontal axis corresponds to
The position x in one direction of Ren is shown.

As shown in FIG. 2 (a), assuming that the thickness of the membrane is constant, the internal stress of the membrane is a constant value σ _{0 in} the portion other than the hole and is 0 in the hole portion. The process of determining this σ (x, y) is step 1 in FIG. The mask given the initial internal stress distribution is
It deforms to balance the stress and reaches a mechanical equilibrium state. The state of this deformation is shown in FIGS. 2 (b) and 2 (c). FIG. 2B is a cross-sectional view of a membrane having a constant film thickness, in which the membrane 2 has holes 2 formed therein. Figure 2 (b)
The membrane 1 shown in 1 is deformed, for example, as shown in FIG.

Assuming that the displacements in the x and y directions at each position of the membrane are u (x, y) and v (x, y), these displacements can be obtained by solving the partial differential equation described in the literature. Computable (M. Oda et al., Jpn. J. Appl. Phy
s. 31, 4189 (1992): Equations (1) and (2)). The partial differential equation itself is a well-known one described in the textbook of elastic mechanics. As described above, the pattern displacement u (x, y), v (x, y) of the membrane without stress control
Is unacceptably large.

In this embodiment, the initial internal stress of the membrane is changed by ion implantation to minimize the displacement amount. Ion implantation is widely used in semiconductor manufacturing processes to change electrical characteristics, but it is also known to change the internal stress of crystals at the same time.

In general, when ions having a larger radius than the atoms constituting the base material are implanted, the internal stress changes in the compression direction, and when ions having a smaller radius are implanted, the internal stress changes in the tensile direction. The relationship between the amount of implanted ions and the internal stress has been well investigated experimentally, and a theoretical model has also been established (eg, A. Degen et al., Proc. SPIE 3997,395.
(2000)).

As described above, attempts have been made to reduce the internal stress by implanting ions uniformly on the entire surface of the mask (for example, Japanese Patent Laid-Open No. 2000-2436).
92 publication). However, even if the internal stress is reduced as a whole, if the pattern is sparse and dense, it may cause a large deformation. Therefore, the pattern accuracy is obviously insufficient only by reducing the internal stress as a whole.

Therefore, in this embodiment, the implantation amount of ions is changed according to the position of the mask, and the degree of freedom in stress control is dramatically improved. As a result, it is possible to manufacture a mask with much higher pattern accuracy than ever before. Figure 3 (a)
As shown in FIG. 3, when the initial internal stress distribution is spatially changed by ion implantation, the displacement of the mask is smaller than that in the case where stress control is not performed (see FIG. 2A) (see FIG. See b) and (c)). The vertical axis of the graph in FIG. 3A corresponds to the stress-controlled optimum initial internal stress σ _opt . FIG. 3B is a cross-sectional view of the membrane to which the initial internal stress distribution is given, and FIG. 3C is a cross-sectional view of the membrane in the mechanical equilibrium state.

Since high precision is required for the mask used in the next-generation exposure technique, it is desirable to control the stress of the mask for both the stencil mask and the membrane mask. The stencil mask is an electron beam transfer lithography (EPL) or an ion beam lithography (IPL).
used for ction lithography).

As an EPL using a stencil mask, PREVAIL (projection) of reduction projection type electron beam lithography using highly accelerated electrons of several tens keV or more is used.
exposure with variable axis immersion lenses) and S
CALPEL (scattering with angular limitation i
n projection electron-beam lithography). In addition, EB using highly accelerated electrons of several tens keV or more
A stencil mask is also used for the stepper.

Furthermore, LEEPL (low) of the same size proximity transfer type electron beam lithography using low acceleration electrons of several keV is used.
energy electron-beam proximity projection lithogra
A stencil mask is also used for phy). On the other hand, the membrane mask is a proximity X-ray lithography (PXL; prox
imity X-ray lithography) and E using highly accelerated electrons
Used for PL. Mask stress control is important in all these exposure methods.

The material of the membrane is, for example, Si,
Examples thereof include SiN, SiC, diamond, diamond-like carbon (DLC) and the like. In a membrane mask, when a metal thin film is formed as a charged particle beam scatterer on the surface of the mask, conductivity is imparted to the mask.

On the other hand, when a charged particle beam enters the stencil mask made of an insulating material in the lithography process,
The mask may be charged and affect the traveling direction of the beam (charge-up). A conductive metal coating may be applied to the mask surface for the purpose of preventing such charge-up. For coating, for example, W, T
Materials such as a, Mo, Au, Pt, Cr and alloys thereof can be used. These metals or alloys are also used as a charged particle beam scatterer for the membrane mask.

Examples of the ion species implanted into the mask for controlling stress include B, P, As, Ga and In. In addition, the membrane material is diamond or DL
In the case of a non-silicon-based material such as C, Si can be implanted in the mask. The implantation energy is set to about 10 keV to 200 keV, though it depends on the film thickness of the membrane (usually about 0.1 μm to several μm). The ions implanted in the mask may be diffused by heating. Alternatively, instead of implantation, ion doping can be performed by a thermal diffusion method.

In order to determine the amount of ion implantation, the displacement u (x) is changed by changing the initial internal stress σ (x, y) under the constraint condition that the stress is zero at the hole portion for a given mask pattern. , Y) and v (x, y) are repeated. As a measure of pattern accuracy, a reliability factor R represented by the following equation (II) is defined.

[0036]

[Equation 2]

Here, N is the number of calculation points, and u _i , v _i
Is the displacement at each calculation point. R is the average value of the mask displacement. Not only the average value R but also the variances of u _i and v _i may be used together as a measure of the pattern accuracy, and monitoring may be performed so that an unacceptable large displacement does not occur at a specific point. The number of calculation points may be determined in consideration of the balance between required accuracy and calculation time.

The membrane is divided into a plurality of blocks in a mesh shape. First, global optimization is performed on the blocks divided by the sparse mesh, and then fine optimization is performed on the blocks divided by the dense mesh. Then, the time required for optimization can be shortened. The initial internal stress is changed in the direction in which R becomes smaller, and the point where R becomes minimum is taken as the optimum initial internal stress. This is step 2 in FIG. Examples of this optimization algorithm include Simplex method, Marquardt method,
Mathematical algorithms such as Simulated Annealing method and genetic algorithm method can be used.

The optimum initial internal stress thus obtained is σ
_{If opt} (x, y), the difference δσ from the initial internal stress
(X, y) = σ _opt (x, y) −σ (x, y) is the internal stress at each point to be changed by ion implantation. When the difference value has positive and negative regions, the ion species to be implanted may be changed according to the case where there are tensile stress and compressive stress regions, but δσ (x, y) is positive (or negative). You may optimize by adding the constraint condition.

Since the internal stress that can be changed by ion implantation has an upper limit, it is necessary to limit δσ (x, y) so that it does not exceed a certain value. In step 3 of FIG. 1, δσ (x, y) is set to the ion implantation amount D (x, y) at each position by using the relationship between the stress variation and the ion implantation amount obtained experimentally or theoretically. Convert.

The above is the mask design process. Next, an example of a method for actually manufacturing a mask using the results of simulation will be described. Many stencil mask and membrane mask manufacturing methods have been proposed so far, and the mask manufacturing process of the present invention is not limited to the following. The steps other than the ion doping can be arbitrarily changed to other conventionally known mask manufacturing processes.

According to the mask manufacturing method of this embodiment,
First, as shown in FIG. 4A, the mask blanks 11
Then, an SOI wafer is prepared. The SOI wafer has a structure in which a silicon active layer 14 is formed on a silicon wafer 12 via a silicon oxide film 13.

Next, as shown in FIG. 4B, the low voltage CV
The SiN layers 15a and 15 are formed on the entire surface of the SOI wafer by D.
b is formed. Next, as shown in FIG.
Etching the SiN layer 15b on the back surface of the wafer,
The SiN layer 15b in the membrane formation region is removed. This etching may be performed by forming a resist (not shown) on the SiN layer 15b in a predetermined pattern and then using the resist as a mask, and performing either dry etching or wet etching.

Next, as shown in FIG. 5D, the silicon wafer 12 is etched from the back surface using the SiN layer 15b as a mask to expose the silicon oxide film 13. The silicon active layer 14 in the portion where the silicon wafer 12 is removed becomes a membrane. Further, the silicon wafer left so as to surround the membrane is used as a support frame for reinforcing the mechanical strength of the stencil mask. After the etching of the silicon wafer 12, the SiN layer 15a protecting the silicon active layer 14 is removed.

Next, as shown in FIG. 5E, the silicon active layer 14 is etched to form holes 16 corresponding to the mask pattern. This etching is performed by forming a resist (not shown) in a predetermined pattern on the silicon active layer 14 and then using the resist as a mask, usually dry etching. After etching, the resist is removed by, for example, ashing.

After that, as shown in FIG. 5F, the silicon oxide film 13 in the membrane portion is removed by, for example, dry etching. Through the above steps, the stencil mask is formed. According to the mask manufacturing method of the present embodiment, ions are implanted into the membrane (silicon active layer 14) with the ion implantation amount determined by the procedure shown in FIG.

The ion implantation step may be carried out in the state of the mask blank 11 shown in FIG. 4A, after etching the silicon wafer 12 as shown in FIG. 5D, and before forming the holes 16, or As shown in FIGS. 5 (e) and 5 (f), it does not matter even after the holes 16 are formed.

It is also possible to implant ions in a plurality of steps. For example, in the state of the mask blank 11 shown in FIG. 4A, ions are uniformly implanted into the silicon active layer 14 to reduce or increase the internal stress as a whole, and then spatially in another step. It is also possible to make a modulated implant.

As a method of implanting ions having a spatial distribution, three methods shown in FIGS. 6 to 8 can be considered. In general, the ion implantation amount D (x, y) is a two-dimensional continuous function, but actually has a certain value only in a dense pattern portion, and is zero (no implantation) in other areas. It is also possible to optimize as a discrete function.

FIG. 6 (a) shows a method of implanting ions through a stencil mask, and FIG. 6 (b) shows the distribution of the amount of ion implantation D (x, y). According to this method, the stencil mask 3 that shields a portion where the ion implantation amount D (x, y) is zero is manufactured as a shielding mask.
By scanning the ion beam on the shielding mask, ion implantation can be performed extremely quickly.

FIG. 7A shows the method without using a mask, and FIG. 7B shows the distribution of the ion implantation amount D (x, y). This method scans an ion beam to implant a predetermined amount of ions at a predetermined location. According to this method, although ion implantation takes time as compared with the method shown in FIG. 6, it is not necessary to prepare a shielding mask.

FIG. 8A shows a method of directly forming a resist or a thin film 4 for shielding an ion beam on the stencil mask instead of producing the shielding mask shown in FIG. 6A, and FIG. Indicates the distribution of the ion implantation amount D (x, y). When performing ion implantation on the stencil mask using the resist as a mask, the resist is applied on the membrane, an ion implantation pattern is drawn by lithography, and then the resist is developed. As a result, a resist is formed on the portion where the ion beam is not implanted.

When ion implantation is performed on the stencil mask using the thin film as a mask, the thin film is vapor-deposited on the membrane and a resist is formed on the thin film. The thin film is etched by using the resist as a mask, and the thin film is left only in the portion that shields the ion beam. Then, the resist is removed. As the material for the thin film, besides metal, SiN or SiO ₂
Various materials that can be formed and processed by a normal semiconductor process are used.

The resist or thin film 4 directly formed on the membrane 1 as described above is used as a mask to implant ions in a specific portion of the membrane 1 and then the resist or thin film 4 is removed. The resist can be removed by, for example, ashing. The thin film can be removed by etching, for example.

According to the mask and its manufacturing method of the above-described embodiment of the present invention, the internal stress of the mask can be controlled extremely accurately by the combination of the stress simulation and the ion implantation. The internal stress control of the membrane that combines the stress simulation and the ion implantation has not been performed so far, but since the technology of the stress simulation and the ion implantation is well established, the internal stress can be controlled with high accuracy. According to the mask manufacturing method of the present embodiment, the internal stress of the mask can be made uniform and the transfer mask for the next-generation exposure method can be manufactured with high accuracy regardless of the density of the pattern.

The method of manufacturing the semiconductor device of this embodiment includes a step of performing lithography using the mask of this embodiment. In the lithography process, since the pattern accuracy of the mask is high, positional deviation and distortion of the transferred pattern can be prevented. Therefore, according to the method of manufacturing the semiconductor device of the present embodiment, it is possible to transfer the fine pattern with high accuracy and further integrate the semiconductor device.

The embodiments of the mask, the method for manufacturing the mask, and the method for manufacturing the semiconductor device of the present invention are not limited to the above description. For example, in FIGS. 6 to 8, an example is shown in which ions are implanted in the stencil mask to control stress.
Ions can be similarly implanted into the membrane mask. It is also possible to use wafers other than SOI as mask blanks. Alternatively, the holes may be formed in the silicon active layer prior to etching the silicon wafer. Besides, various modifications can be made without departing from the scope of the present invention.

[0058]

According to the mask of the present invention, it is possible to prevent the deterioration of pattern accuracy due to the imbalance of internal stress. According to the method for manufacturing a mask of the present invention, it is possible to manufacture a mask in which a decrease in pattern accuracy due to internal stress is prevented. Further, according to the method for manufacturing a semiconductor device of the present invention, it is possible to transfer a fine pattern with high accuracy and further integrate the semiconductor device.

[Brief description of drawings]

FIG. 1 is a flowchart showing a stress control procedure in a mask manufacturing method of the present invention.

FIG. 2 is a diagram showing the relationship between the initial internal stress distribution and the mask structure when the stress control of the mask is not performed.

FIG. 3 is a diagram showing the relationship between the initial internal stress distribution and the mask structure when the stress control of the mask is performed according to the present invention.

FIG. 4A to FIG. 4C are cross-sectional views showing a manufacturing process of the mask manufacturing method of the present invention.

5 (d) to 5 (f) are cross-sectional views showing a manufacturing process of a mask manufacturing method of the present invention, showing a process following FIG. 4 (c).

FIG. 6A shows an example of a method of implanting ions in the mask manufacturing method of the present invention, and FIG. 6B is a diagram showing the distribution of the amount of ion implantation.

FIG. 7A shows an example of a method of implanting ions in the mask manufacturing method of the present invention, and FIG. 7B is a diagram showing a distribution of the amount of ion implantation.

8A shows an example of a method of implanting ions in the mask manufacturing method of the present invention, and FIG. 8B is a diagram showing a distribution of the amount of ion implantation.

[Explanation of symbols]

1 ... Membrane, 2 ... Hole, 3 ... Stencil mask, 4 ...
Resist or thin film, 11 ... Mask blanks, 12 ...
Silicon wafer, 13 ... Silicon oxide film, 14 ... Silicon active layer, 15a, 15b ... SiN layer, 16 ... Hole.

Claims (14)

[Claims] 1. A thin film having a charged particle beam or an electromagnetic wave transmitting part and a blocking part formed in a predetermined pattern, and the thin film is formed so as to reduce displacement of the pattern due to internal stress of the thin film. A mask with impurities added uniformly. 2. The transmission part is a hole formed in the thin film, and the blocking part is the thin film other than the hole.
The listed mask. 3. The mask according to claim 1, wherein the thin film allows the charged particle beam or the electromagnetic wave to pass therethrough, and the blocking section is a portion where the charged particle beam or the electromagnetic wave scatterer is formed on the thin film. 4. The mask according to claim 1, further comprising a support portion for supporting the thin film on one surface side of the thin film. 5. A mask having a thin film in which a charged particle beam or electromagnetic wave transmitting portion and a shielding portion are formed in a predetermined pattern is used to determine an internal stress distribution by using at least the material and structure of the mask and data of the pattern. Calculate, the step of the initial internal stress, and calculate the displacement amount that a plurality of calculation points on the mask to move in order to take a mechanical equilibrium state of the internal stress of the mask,
A step of setting an internal stress distribution that minimizes the average value of the displacement amount at the calculation points as an optimum initial internal stress; a step of obtaining a difference between the optimum initial internal stress and the initial internal stress at each calculation point; Based on the relationship between the addition amount and the stress change, a step of obtaining a predetermined impurity addition amount that eliminates the difference at each calculation point, a step of forming the transmission part and the blocking part in the thin film, and the predetermined A method of manufacturing a mask, which comprises: non-uniformly adding impurities to the thin film with an impurity addition amount. 6. The step of obtaining the predetermined impurity addition amount comprises:
Based on the relationship between the amount of ion implantation and the stress change examined in advance, including a step of obtaining a predetermined amount of ion implantation to eliminate the difference at each calculation point, the step of adding the impurity, the step of adding the predetermined ion implantation The method for manufacturing a mask according to claim 5, further comprising the step of implanting ions into the thin film in a non-uniform amount. 7. The method of manufacturing a mask according to claim 6, wherein ions are implanted into the thin film before the blocking portion is formed in the thin film. 8. The method for manufacturing a mask according to claim 6, wherein ions are implanted into the thin film after the blocking portion is formed in the thin film. 9. The method of implanting ions in a plurality of times.
A method for manufacturing the described mask. 10. The method of manufacturing a mask according to claim 6, further comprising the step of thermally diffusing the impurities after implanting the ions. 11. The method of manufacturing a mask according to claim 5, wherein the step of forming the blocking portion includes the step of forming a hole in the thin film that blocks the charged particle beam or the electromagnetic wave. 12. The mask manufacturing method according to claim 5, wherein the step of forming the blocking portion includes the step of forming a scatterer of the charged particle beam or the electromagnetic wave on a thin film that transmits the charged particle beam or the electromagnetic wave. Method. 13. A step of forming a thin film forming layer on a base material, and a part of the base material is removed from a surface opposite to the thin film forming layer to expose the thin film forming layer. 6. The method for manufacturing a mask according to claim 5, further comprising the step of using the formed portion as the thin film and the remaining portion of the base material as a supporting portion of the thin film. 14. A method of manufacturing a semiconductor device, which comprises a step of exposing a photosensitive surface to a charged particle beam or an electromagnetic wave through a mask, wherein the mask has a charged particle beam or an electromagnetic wave transmitting part and a blocking part. A method of manufacturing a semiconductor device, comprising a thin film formed in a pattern, and using a mask in which impurities are unevenly added to the thin film so as to reduce displacement of the pattern due to internal stress of the thin film.