JP2003186938A - スコアボードを用いた検証方法 - Google Patents

スコアボードを用いた検証方法

Info

Publication number
JP2003186938A
JP2003186938A JP2001386132A JP2001386132A JP2003186938A JP 2003186938 A JP2003186938 A JP 2003186938A JP 2001386132 A JP2001386132 A JP 2001386132A JP 2001386132 A JP2001386132 A JP 2001386132A JP 2003186938 A JP2003186938 A JP 2003186938A
Authority
JP
Japan
Prior art keywords
scoreboard
data
read
address
storage element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001386132A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003186938A5 (https=
Inventor
Daisuke Kuroki
大輔 黒木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2001386132A priority Critical patent/JP2003186938A/ja
Priority to US10/309,091 priority patent/US7028146B2/en
Publication of JP2003186938A publication Critical patent/JP2003186938A/ja
Publication of JP2003186938A5 publication Critical patent/JP2003186938A5/ja
Priority to US11/331,145 priority patent/US7210007B2/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2001386132A 2001-12-19 2001-12-19 スコアボードを用いた検証方法 Pending JP2003186938A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001386132A JP2003186938A (ja) 2001-12-19 2001-12-19 スコアボードを用いた検証方法
US10/309,091 US7028146B2 (en) 2001-12-19 2002-12-04 Method of verifying a system in which a plurality of master devices share a storage region
US11/331,145 US7210007B2 (en) 2001-12-19 2006-01-13 Method of verifying a system in which a plurality of master devices share a storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001386132A JP2003186938A (ja) 2001-12-19 2001-12-19 スコアボードを用いた検証方法

Publications (2)

Publication Number Publication Date
JP2003186938A true JP2003186938A (ja) 2003-07-04
JP2003186938A5 JP2003186938A5 (https=) 2005-07-28

Family

ID=19187906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001386132A Pending JP2003186938A (ja) 2001-12-19 2001-12-19 スコアボードを用いた検証方法

Country Status (2)

Country Link
US (2) US7028146B2 (https=)
JP (1) JP2003186938A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006227668A (ja) * 2005-02-15 2006-08-31 Ricoh Co Ltd メモリモデルとプログラムと論理回路検証方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7949148B2 (en) * 2006-01-23 2011-05-24 Digimarc Corporation Object processing employing movement
EP4429203A1 (en) * 2023-03-09 2024-09-11 Abb Schweiz Ag Method for enabling an efficient data processing in a distributed network of devices

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2875909B2 (ja) * 1991-07-12 1999-03-31 三菱電機株式会社 並列演算処理装置
JPH10143365A (ja) * 1996-11-15 1998-05-29 Toshiba Corp 並列処理装置及びその命令発行方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006227668A (ja) * 2005-02-15 2006-08-31 Ricoh Co Ltd メモリモデルとプログラムと論理回路検証方法

Also Published As

Publication number Publication date
US20060117151A1 (en) 2006-06-01
US20030115425A1 (en) 2003-06-19
US7210007B2 (en) 2007-04-24
US7028146B2 (en) 2006-04-11

Similar Documents

Publication Publication Date Title
CN107506312B (zh) 在不同高速缓存一致性域之间共享信息的技术
US20130275691A1 (en) Method, apparatus and system for memory validation
JP2006521637A (ja) データ処理システムにおけるメモリ管理
CN1996254A (zh) 用于冗余控制器固件更新的装置、系统和方法
WO2012049914A1 (ja) 組込プログラム更新方法、組込プログラム更新プログラム、電子機器、ネットワークシステム
US9250920B2 (en) Initializing processor cores in a multiprocessor system
US11029852B2 (en) Dedicated interface for coupling flash memory and dynamic random access memory
TWI556110B (zh) 用於提供存取裝置函數的設備、系統及方法
US8650414B2 (en) Logic device having status and control registers for recording the status and controlling the operation of memory slots such that each memory slot is identified using a bus address and port number
US20070101114A1 (en) Method and apparatus for memory initializing in a computer system
EP4315047A1 (en) Adaptive memory consistency in disaggregated datacenters
TW457419B (en) Microcomputer, electronic machine and emulation method
US5928338A (en) Method for providing temporary registers in a local bus device by reusing configuration bits otherwise unused after system reset
JP2003186938A (ja) スコアボードを用いた検証方法
US20100217957A1 (en) Structured Virtual Registers for Embedded Controller Devices
US20090213755A1 (en) Method for establishing a routing map in a computer system including multiple processing nodes
JPH1117098A (ja) メモリモジュール
US20050223265A1 (en) Memory testing
CN105739927B (zh) 一种基于软核处理器的移动存储卡读写方法及文件升级系统
JP4083474B2 (ja) メモリ装置の制御方法およびそのプログラムならびに記録媒体
US7333106B1 (en) Method and apparatus for Z-buffer operations
CN116108782B (zh) 一种mcu外设控制寄存器行为模拟方法与相关装置
CN121391585B (zh) 图形处理单元封装体及其安全启动方法
CN111984491B (zh) 一种用于原型验证的虚拟存储设备
JP2007087176A (ja) 論理回路の記憶素子検証手法

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20041206

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041220

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041220

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070411

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070611

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070828

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071029

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20071211