JP2003186823A - Priority control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a priority control system by which complicated priority order control can be made without impairing real-time performance in a common bus mediation device of a control device in which real-time performance is required. <P>SOLUTION: The priority order control system 13 which controls the priority order of access to a bus slave device 12 from a plurality of bus master devices 110-112 connected to at least one bus slave device 12 via a common bus 10, is provided with a first priority order control means 20 which simply speed up priority order control processing, a second priority order control means which controls complicated priorities, and gate means 220-222 which perform ON/OFF control the requests for access to the first priority order control means 20 based on the output result of the second priority order control means 21. Complicated priority order control can be made by the priority order control means 21 in parallel, while implementing priority order control of a low latency by the priority order control means 20. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a priority control system, and more particularly to a priority control system for controlling the priority of access requests from a plurality of bus master devices to a bus slave device without impairing real-time performance. .

[0002]

2. Description of the Related Art In a system in which a plurality of bus master devices and a bus slave device are connected via a shared bus, when an access request from a plurality of bus master devices to the bus slave devices occurs at the same time, the shared access is arbitrated. Bus arbitration device is required.

As a shared bus arbitration method, there are a centralized arbitration method in which an access request is issued to an arbitration device to obtain an access right by the permission thereof, and a daisy chain method in which an access request is permitted based on a predetermined priority. When controlling complicated priorities, the centralized arbitration method is mainly used.

[0004]

In order to improve the performance of the entire system, it is important to use the shared bus efficiently. In this case, complicated priority control such as managing the access status from each bus master device and controlling the priority of the shared bus based on the information is required.

As an example of controlling a complicated priority order based on the number of times the bus is used, the allowable waiting time for use, etc.
There is a bus arbitration control device and the like described in Japanese Patent Publication No. 0-334042.

The conventional shared bus arbitration device has a problem that when controlling complicated priorities, latency (waiting time) increases and it cannot be used as a priority control system requiring real-time performance.

An object of the present invention is to provide a priority control system capable of performing complex priority control in a shared bus arbitration device of a control device which requires real-time performance without impairing real-time performance.

[0008]

In order to achieve the above object, the present invention provides a priority order of access to a bus slave device from a plurality of bus master devices connected to at least one bus slave device via a shared bus. In a priority control system for controlling, a first priority control means for simply speeding up priority control processing, a second priority control means for controlling a complicated priority order, and a first priority order. There is proposed a priority control system including a gate means for ON / OFF controlling an access request to the control means according to an output result of the second priority control means.

The present invention also provides a priority control system for controlling priority of access to a bus slave device from a plurality of bus master devices connected to at least one bus slave device via a shared bus. Access request is given to the access request once, the first priority control means continues to issue the access permission as long as the access requests are continuously issued, and the access from the other bus master device is issued. Feedback control means for generating a feedback signal for temporarily turning off the access request when the request is issued, and gate means for ON / OFF controlling the access request to the first priority control means according to the output result of the feedback control means. We propose a priority control system equipped with it.

The present invention further provides a priority control system for controlling priority of access to a bus slave device from a plurality of bus master devices connected to at least one bus slave device via a shared bus. Access request is given to the access request once, the first priority control means continues to issue the access permission as long as the access requests are continuously issued, and the access from the other bus master device is issued. Feedback control means for generating a feedback signal for temporarily turning off the access request when the request is issued,
Second priority control means for controlling complex priorities;
Feedback signal control means for ON / OFF controlling a feedback signal corresponding to a bus master device to be preferentially processed by a feedback control signal output from the second priority control means, and access to the first priority control means. A priority control system including a gate means for controlling ON / OFF of a request according to the output result of the feedback signal control means is proposed.

If the second priority control means is provided with an access request management means for managing the access request amount from a plurality of bus master devices, the priority order can be controlled based on the access request amount.

More specifically, the access request management means is a queue memory for temporarily storing an access request from the bus master device, and the data amount is at least one of access frequency and access waiting data amount.

According to the present invention, the priority control is divided into a first priority control means for controlling a simple and high-speed priority and a second priority control means for controlling a complicated priority. The access request to the first priority control means is turned on / off using the control result of the second priority control means.
Control. As a result, since complicated priority control can be processed in parallel while realizing the low latency priority control by the first priority control means, the complicated priority control can be performed without deteriorating the real-time property.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a priority control system according to the present invention will be described with reference to FIGS.

[0015]

First Embodiment FIG. 1 is a block diagram showing the configuration of a first embodiment of a priority control system according to the present invention. Although three bus master devices 110 to 112 are shown here, the number of bus master devices may be any number.

In the first embodiment, the shared bus 10 is connected with bus master devices 110 to 112, a bus slave device 12, and a priority control system 13 for controlling arbitration of the shared bus.

The priority control system 13 of the first embodiment
Is a first priority control means 20 for controlling the priority of low latency, a second priority control means 21 for controlling a complicated priority, and a control result of the second priority control means 21. It is composed of gate means 220 to 222 for ON / OFF controlling access requests 140 to 142 to the first priority control means 20.

The bus master device 110 issues an access request 140 to the priority control system 13 and, when the access permission 150 is obtained, accesses the bus slave device 12. The bus master devices 111 and 112 operate similarly.

In the priority control system 13 which requires real-time performance, it is required to reduce the latency from issuing the access request 140 to obtaining the access permission 150.

In the priority control system 13, if the priority control is complicated in order to control high-level arbitration, the latency generally increases.

On the other hand, in the first embodiment, the first priority control means 20 has the gate means 220 to 22.
The access requests 140 to 142 from the bus master devices 110 to 112 that have passed through 2 are evenly distributed, and access permissions 150 to 152 are output.

If only the simplified control is executed as described above, the bus master devices 110 to 112 cause the access request 14 to access.
The latency from issuing 0 to 142 to obtaining access permission 150 to 152 can be shortened.

On the other hand, the second priority control means 21 generates control signals 230 to 232 for controlling the gate means 220 to 222 which pass only the access request of the bus master device to be preferentially processed.

An example will be described in which the access request 140 from the bus master device 110 is preferentially processed. The second priority control means 21 activates only the control signal 230 and deactivates the control signals 231 and 232. As a result, of the access requests 240 to 242 to the first priority control means 20, only the access request 240 is valid, the access requests from the bus master devices 111 and 112 are blocked, and only the bus master device 110 is given priority. It is processed.

As described above, the provision of the second priority control means 21 enables more complicated priority control in addition to the priority control of the first priority control means 20 which is distributed evenly.

[0026]

Second Embodiment The second priority control means 21 may include access request management means. The access request management means manages information such as the access frequency and the amount of data waiting to be accessed for the access requests from the bus master devices 110 to 112. The second priority control means 21 controls the priority order based on the information of the access request management means.
For example, there is a method of preferentially processing a bus master device having a large amount of data waiting to be accessed.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the priority control system according to the present invention in which a queue memory is installed as access request management means. In the second embodiment, in the configuration of the first embodiment, queue memories 300 to 302 for temporarily storing access from the bus master devices 110 to 112 are installed as means for managing access requests. The queue memories 300 to 302 may be built in the priority control system 13.

The bus master devices 110 to 112 are connected to the queue memories 300 to 302 installed inside or outside the priority control system 13.

The bus master devices 110 to 112 temporarily store data in the queue memories 300 to 302 when the access permission 150 to 152 to the shared bus 10 cannot be obtained. When data is stored in the queue memories 300 to 302, access permission to the shared bus 10 to 150 to 15
When 2 is obtained, the bus slave device 13 is accessed with the data in the queue memories 300 to 302.

By monitoring the amount of data in the queue memories 300 to 302, the access request management information 31 such as the amount of data waiting to be accessed can be obtained.

According to the second embodiment, since the priority control of low latency can be realized by the first priority control means, the complicated priority control can be processed in parallel, so that it can be applied to the control device requiring the real-time performance. A possible priority control system can be realized.

[0032]

Third Embodiment FIG. 3 is a block diagram showing the configuration of a third embodiment of the priority control system according to the present invention in which feedback control is installed. The priority control system 13 according to the third exemplary embodiment includes a first priority control unit 20, gate units 220 to 222, and a feedback control circuit 40.
And feedback signal control circuits 410 to 412.

The first priority control means 20 in the first embodiment, once the access permission 150, 151, 152 is given, unless the access request 140, 141, 142 disappears, the access permission 150, 151, 15 is obtained.
The process of continuing to output 2 was executed.

In the case of random access in which access requests are not continuously output from one bus master device 110, for example, the access can be averaged only by the first priority control means 20.

However, when access is made by transfer processing in which access requests are continuously output from one bus master device 110, the access requests from the other bus master devices 111 and 112 are cut off, and the accesses are not averaged.

Therefore, in the third embodiment, by accessing the access permissions 150, 151 and 152 as feedback, the access is averaged using the current priority.

In the feedback circuit 400, the access permission 150 is issued, and the other bus master device 11
A feedback signal 420 which becomes active when access requests 141 and 142 from 1,112 are issued is generated.

The feedback control circuits 401 and 402 similarly generate feedback signals 421 and 422.

Basically, the first priority control means 20 is basically provided that once the bus master devices 110, 111, 112 have obtained the access permission 150, 151, 152, as long as the access requests 140, 141, 142 are issued. Continue to issue access permissions 150, 151, 152.

Therefore, the feedback signals 420, 42
1, 422 to access requests 140, 141, 1
42 is temporarily cut off, and the access permission is given to another bus master device.

[0041]

[Fourth Embodiment] FIG. 4 is a block diagram showing a configuration of a fourth embodiment of a priority control system according to the present invention, which is a combination of the first and third embodiments.

In the fourth embodiment, the feedback signal 4
20 to 422 and the feedback control signals 430 to 432 output by the second priority control means 21 are connected to the feedback signal control circuits 410 to 412.

Feedback signal control circuits 410-41
2 cuts off the feedback signals 420 to 422 according to the feedback control signals 430 to 432 and controls the priority.

For example, when it is desired to process the bus master device 110 preferentially, when the second priority control means 21 makes the feedback control signal 430 active, that is, the High level, the feedback signal 420 can be cut off.
The access permission 150 to the bus master device 110 can be continuously issued.

Therefore, the flexibility of priority control is expanded.

[0046]

According to the present invention, in a priority control system for controlling the priority of access to a bus slave device from a plurality of bus master devices connected to at least one bus slave device via a shared bus, a priority control system is provided. A first priority control unit that simply speeds up the priority control process, a second priority control unit that controls a complicated priority, and an access request to the first priority control unit that is a second request. Since the first priority control means realizes the low-latency priority control, the complicated priority control is performed in the second priority, since the gate means controls ON / OFF according to the output result of the priority control means. Parallel processing can be performed by the rank control means.

Therefore, complicated priority control for efficiently using the shared bus can be realized with a low latency as a whole, and a large amount of operations such as image processing and signal processing can be processed with a low latency without impairing real-time performance. It is possible to realize a priority control system that can be applied to a control device that needs to operate.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a priority control system according to the present invention.

FIG. 2 is a second embodiment of a priority control system according to the present invention, which has a queue memory as an access request management means.
3 is a block diagram showing the configuration of FIG.

FIG. 3 is a block diagram showing a configuration of a third embodiment of a priority control system according to the present invention in which feedback control is installed.

FIG. 4 is a block diagram showing a configuration of a fourth embodiment of a priority control system according to the present invention, which is a combination of the first embodiment and the third embodiment.

[Explanation of symbols]

10 shared buses 110-112 Bus Master Device 12-bus slave device 13 Priority control system 140-142 access request 150-152 access permission 20 First priority control means 21 Second Priority Control Means 220-222 gate means 230-232 control signal 240-242 Access request 300-302 queue memory 31 Access request management information 400-402 Feedback control circuit 410-412 Feedback signal control circuit 420-422 Feedback signal 430-432 Feedback control signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Tanzawa             216 Totsuka Town, Totsuka Ward, Yokohama City, Kanagawa Prefecture             Ceremony Hitachi Defense Systems             Within the department (72) Inventor Takuya Okamura             216 Totsuka Town, Totsuka Ward, Yokohama City, Kanagawa Prefecture             Ceremony Hitachi Defense Systems             Within the department F-term (reference) 5B061 BC02

Claims (5)

[Claims] 1. A priority control system for controlling the priority of access to a bus slave device from a plurality of bus master devices connected to at least one bus slave device via a shared bus. A first priority control means for simply increasing the speed, a second priority control means for controlling a complicated priority, and an access request to the first priority control means for the second priority control. A priority control system, comprising: a gate means for performing ON / OFF control according to an output result of the means. 2. A priority control system for controlling priority of access to a bus slave device from a plurality of bus master devices connected to at least one bus slave device via a shared bus, wherein access from the bus master device is performed. Once the access permission is given to the request, the first priority control means that keeps issuing the access permission as long as the access requests are continuously issued, and the access permission is issued and another bus master device Feedback control means for generating a feedback signal for temporarily turning off the access request when the access request is issued, and ON / OFF control of the access request to the first priority control means according to the output result of the feedback control means. A priority control system characterized by comprising gate means Tem. 3. A priority control system for controlling priority of access to a bus slave device from a plurality of bus master devices connected to at least one bus slave device via a shared bus, wherein access from the bus master device is performed. Once the access permission is given to the request, the first priority control means that keeps issuing the access permission as long as the access requests are continuously issued, and the access permission is issued and another bus master device Feedback control means for generating a feedback signal for temporarily turning off the access request when an access request is issued, second priority control means for controlling a complicated priority, and output from the second priority control means Device to be preferentially processed by a feedback control signal Corresponding the feedback signal ON / OF
F / F feedback signal control means, and access request to the first priority control means is turned ON / OF according to the output result of the feedback signal control means.
A priority control system comprising a gate means for controlling F. 4. The priority order control system according to claim 1, wherein the second priority order control means includes access request management means for managing access request amounts from the plurality of bus master devices, and access. A priority control system characterized by controlling priorities based on a request amount. 5. The priority control system according to claim 4, wherein the access request management means is a queue memory for temporarily storing an access request from the bus master device, and the data amount is an access frequency and an access wait state. A priority control system characterized by being at least one of the amount of data.