JP2003186451A - Matrix type image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a matrix type image display device which can make higher-definition multigradation display without increasing the circuit scale. <P>SOLUTION: The individual pixels of the matrix type image display device 10 are divided into a 1st pixel display part 11 and a 2nd pixel display part 12 with an area ratio of 2M:1 provided that a digital video signal written to a pixel 2 consists of higher-order M bits and lower-order L bits (M≠0, L≠0). A 2M gradation signal corresponding to the higher-order M bits of the digital video signal is outputted to a data signal line SL1 and a 2L gradation signal corresponding to the lower-order L bits of the digital video signal is outputted to a data signal line SL2; and the gradation signals are written, respectively, to the 1st and 2nd pixel display parts 11 and 12 through switching elements T1 and T2. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type image display device for displaying an image based on an input digital video signal, and more particularly to dividing a pixel into
The present invention relates to a matrix-type image display device capable of performing gradation display in a greater number than the input number of video signal potentials by inputting a video signal potential to each of the divided pixels.

[0002]

2. Description of the Related Art An active matrix type display device will be described below as an example of a conventional matrix type image display device.

As shown in FIG. 15, this active matrix type image display device has a pixel array 101, a scanning signal line drive circuit GD102 and a data signal line drive circuit SD10.
3 and 3.

The active matrix type image display device shown in FIG. 15 generally has a data signal line drive circuit SD103.
And the scanning signal line drive circuit GD102 as an external IC
Is equipped with.

In recent years, as shown in FIG. 16, a pixel array 1
01, the data signal line driving circuit SD103 and the scanning signal line driving circuit GD102 are formed on one insulating substrate,
A so-called monolithic active matrix type image display device has been proposed. Such a monolithically formed active matrix image display device can reduce mounting cost and improve reliability during mounting.

The data signal line drive circuit SD103 of FIG.
The scanning signal line drive circuit GD102 includes a control circuit CTL105 that supplies various control signals and a power supply circuit SPL10.
6 and 6 are connected. Then, the control circuit CTL105
The digital video signal DAT inputted from the data signal line S is converted into an analog potential corresponding to the inputted digital amount in the data signal line drive circuit SD103.
It is output to L.

Here, the data signal line drive circuit SD103
17 shows a reference voltage selection type D / A conversion circuit which is generally used as a circuit for converting an input digital amount into a corresponding analog potential.
Will be explained. For convenience of explanation, it is assumed that the input digital video signal DAT has 4 bits.

[0008] D / A conversion circuit shown in FIG. 17, 4-bit digital video signal D ₁ to D ₄ reference voltage corresponding 16 gradations in Vref0~Vref15 is inputted from the outside, to the data signal lines SL, respectively Analog switches ANS0 to ANS15 for selecting connection / non-connection of are provided. These analog switches ANS0-A
NS15 is an output DCO0 of the decoder circuit DC110.
Controlled by the DCO 15, a desired reference potential is applied to the data signal line SL according to the input digital video signal.
Output to. As a result, the digital video signals D _{1 to} D ₄ input from the outside can be converted into analog signals corresponding to the digital video signals D _{1 to} D _4, and an image can be displayed with 16 gradations.

Further, the pixel 104 includes a switching element 112, an auxiliary capacitance Cs, and a pixel display section 116, as shown in FIG.

The auxiliary capacitor Cs has one end electrode connected to the drain electrode of the switching element 112 and the other end connected to a common electrode 113 which is an electrode common to all the pixels 104.

The pixel display section 116 includes the pixel electrode 111 and the counter electrode 115 which are arranged to face each other with the liquid crystal 114 interposed therebetween.

In the pixel 104, the source electrode is connected to the data signal line SL and the gate electrode is connected to the scanning signal line GL, and the pixel P is connected by the scanning signal line GL.
1X104 are sequentially selected, the potential of the data signal line SL is applied to the pixel electrode 111 via the switching element 112, and the transmittance of the pixel display unit 116 is changed.

As shown in FIG. 19, the relationship between the transmittance and the signal potential in the pixel display section 116 indicates a normally white mode as an example of the signal voltage when the counter potential is set to 0V. For example, the transmittance becomes 100% when the signal voltage is 0 V, and the transmittance decreases as the signal voltage increases. In the conventional matrix type image display device, arbitrary gradation display is possible in this way.

[0014]

However, in the conventional active matrix type image display device as described above, when the D / A conversion of the reference voltage selection system is performed, the data that can be expressed by N bits of the digital video signal. It is necessary to externally input 2 ^N reference voltages corresponding to the number. Therefore, as the number of pins for external connection increases and it is necessary to install 2 ^N reference voltage lines in the data signal line drive circuit SD103, the drive circuit width is increased, and as a result, the overall size of the device is reduced. It causes a problem that it cannot meet the request of.

Therefore, in order to avoid this problem, the number of reference voltages input from the outside is reduced and the data signal line drive circuit SD10 is formed by using capacitive coupling or resistance voltage division.
3 is used to generate the required data potential.

However, the pixel array 101 shown in FIG.
When the data signal line driving circuit SD103 and the scanning signal line driving circuit GD102 are formed on one insulating substrate, the characteristic variation becomes large among the elements forming the circuit for generating the data potential, and the multi-gradation potential is increased. It is very difficult to generate with high accuracy.

On the other hand, in Japanese Patent Laid-Open No. 4-247431, in the pixels divided into a plurality of sub-pixels, the sub-pixels other than the smallest sub-pixel are in the binary mode, and the smallest sub-pixel is the plurality of transmission level modes. A display device that performs gradation display is disclosed.

According to the structure of the above publication, the total number of adjustable transmission levels can be increased by combining the discrete adjustment of the transmission level with the analog adjustment of the transmission level, and the multi-gradation display can be realized.

Further, in Japanese Unexamined Patent Publication No. 7-261155, one pixel is divided into a plurality of pixels having a predetermined area ratio, and each bit component of a digital video signal input from the outside corresponds to the corresponding area ratio. There is disclosed an active matrix liquid crystal display element which performs gradation display by writing in a pixel having a.

According to the configuration of the above publication, by combining the display in the divided pixels divided into a plurality, it is possible to perform a desired gradation display according to the area ratio of the divided pixels, improve the display quality, and the peripheral circuit. The effect of reducing the number of parts of the element can be obtained.

However, the configurations disclosed in the above two publications also have the following problems.

That is, normally, in an active matrix type display device, when a pixel is divided into a plurality of means as one means for realizing multi-gradation display, in each sub-pixel, a signal writing and a signal holding are carried out. A switching element and a data signal line and a scanning signal line corresponding to each switching element are required.

As a result, since it is necessary to increase the number of pixel divisions in order to perform multi-gradation display, the larger the number of pixel divisions, the larger the scale of the switching element and the drive circuit inevitably becomes, resulting in recent years. It becomes impossible to meet the demand for miniaturization of the entire device. Further, since the minimum area of the divided pixels becomes considerably small when the number of divisions increases, the number of pixel divisions is also limited by the display device definition or the pixel division accuracy, that is, the formation accuracy of each signal line, the division processing accuracy, and the like. Since a problem such as a decrease in aperture ratio caused by optical characteristics occurs, it is difficult to say that the desired gradation display can be actually obtained by freely dividing the pixel.

The present invention has been made in view of the above problems, and an object thereof is to achieve low power consumption and high-definition multi-gradation display without increasing the circuit scale. Another object is to provide a matrix type image display device.

[0025]

In order to solve the above-mentioned problems, the matrix type image display device of the present invention has a plurality of data signal lines and a plurality of scanning signal lines intersecting with the data signal lines. In the matrix type image display device having a plurality of pixel display portions arranged in a matrix at each intersection of the plurality of data signal lines and the scanning signal lines, the upper bits of a digital signal input as a video signal. Is M bits (M ≠ 0), the pixel display section is 2 ^M : 1.
Of the divided pixel display portions, and the pixel display portion corresponding to 2 ^M of the area ratio among the divided pixel display portions has a video signal potential corresponding to the digital signal of the upper M bits. Is written, and the video signal potential corresponding to the digital signal of the other lower bits is written in the pixel display portion corresponding to the above area ratio of 1.

According to the above arrangement, the pixel display section has 2 ^M :
It is divided at an area ratio of 1, and the video signal potential is independently written in each of the divided pixel display portions. Therefore,
Even if video signal potentials of the same value are written in each pixel display unit, the video signals are weighted according to their area ratios, and the sum of the number of gradation signals written in each divided pixel display unit is calculated as a whole pixel. Can be set as the number of real gradation signals.

That is, the number of gradations that can be actually displayed in the whole pixel can be made larger than the number of gradations of the video signal written in the pixel display section, and it is necessary to obtain a desired gradation display. The number of gradation signals to be input can be reduced as compared with the related art. Therefore, according to the area ratio of the divided pixel display portions, even when a signal with a gradation number smaller than the gradation number actually displayed is input, image display with a desired gradation number can be realized.

Further, the divided pixel display portion is 2 ^M : 1.
Since each pixel is only divided into two at an area ratio of 1, the divided pixels are provided in comparison with the case where the divided pixel is divided into a plurality of three or more as in the conventional image display device. The number of data signal lines and scanning signal lines corresponding to the existing switching elements can be reduced to two at maximum. Therefore, compared with the conventional matrix type image display device, the power consumption of the device can be reduced, the area occupied by the wiring on the substrate can be reduced, and the display area can be enlarged to enable higher-definition image display. .

Further, for the divided pixel display section,
If a gradation display is performed by writing an analog video signal corresponding to a digital signal, and a D / A conversion circuit for converting the digital video signal into an analog video signal is provided, the D / A conversion circuit is included. The device size can be reduced by reducing the circuit scale of the peripheral circuit.

In order to solve the above-mentioned problems, the matrix type image display device of the present invention has a plurality of data signal lines and a plurality of scanning signal lines intersecting with the data signal lines. In a matrix-type image display device including a plurality of pixel display units arranged in a matrix at each intersection of a signal line and a scanning signal line, the upper bits of a digital signal input as a video signal are M bits (M ≠). 0),
^Assuming that the lower bits are L bits (L ≠ 0), the pixel display section is divided into two at an area ratio of 2 ^M : 1. A video signal potential of 2 ^M gradations is written to the pixel display unit corresponding to ^M, and a video signal potential of 2 ^L gradations is written to the pixel display unit corresponding to 1 of the above area ratio. It is characterized by that.

According to the above configuration, gradation display is performed with (M + L) -bit gradation, which is the sum of the numbers of bits of the M-bit gradation signal and the L-bit gradation signal written in each divided pixel display section. Will be possible. Therefore, the number of gradation signals actually displayed can be increased more than the number of gradation signals of the input reference potential.

That is, the upper M bits input from the outside
And a total of N bits of lower L bits (M ≠ 0, L ≠ 0)
For digital video signals, for example, M> L
And 2 ^MJust prepare the reference voltage for gradation,
2 in the divided pixel display^M2 for gradation^MLess than gradation
I 2^LWrite the reference voltage for each gradation.
By 2^NIt is possible to display images for gradation. Tsuma
Of the higher bits or lower bits
Just input the reference voltage for the corresponding number of gradations
And the floor for the total number of high-order bits and low-order bits
Key display becomes possible.

Further, the divided pixel display portion is 2 ^M : 1.
Since each pixel is only divided into two at an area ratio of 1, the divided pixels are provided in comparison with the case where the divided pixel is divided into a plurality of three or more as in the conventional image display device. The number of data signal lines and scanning signal lines corresponding to the existing switching elements can be reduced to two at maximum. Therefore, compared with the conventional matrix type image display device, the power consumption of the device can be reduced, the area occupied by the wiring on the substrate can be reduced, and the display area can be enlarged to enable higher-definition image display. .

Furthermore, for the divided pixel display section,
If a gradation display is performed by writing an analog video signal corresponding to a digital signal, and a D / A conversion circuit for converting the digital video signal into an analog video signal is provided, the D / A conversion circuit is included. The device size can be reduced by reducing the circuit scale of the peripheral circuit.

Further, it is more preferable that each of the divided pixel display portions has a switching element for video signal writing / holding control.

As a result, it becomes easy to control the first and second pixel display sections independently of each other, and as described above, it is possible to perform multi-gradation display with a smaller number of input gradation signals than before. A matrix type image display device can be obtained.

The switching element of the divided pixel display section has a drain electrode connected to the pixel electrode of the divided pixel display section and a gate electrode connected to a common scanning signal line. More preferably, the source electrodes are connected to different data signal lines.

As a result, data to be written in different data signal lines can be output in parallel, and a long time for writing a video signal in both data signal lines can be secured. As a result, for example, it is possible to reduce the driving capability of the output unit such as the selection circuit, reduce the circuit scale, reduce power consumption, and avoid display unevenness due to insufficient charging of the data signal lines.

The switching element of the divided pixel display section has a drain electrode connected to the pixel electrode of the divided pixel display section, and a gate electrode connected to different scanning signal lines. More preferably, the source electrode and the source electrode connected to the common data signal line are provided.

Therefore, in consideration of the interference between the pixel electrode and the pixel electrode of the data signal line, it is necessary to lay out the data signal line and the pixel electrode so as not to overlap in the manufacturing process. According to the configuration of the present invention, even in that case, the ratio of the pixel display unit to the entire pixel can be made larger than that in the conventional case.

It is more preferable that the pixel display section, the drive circuit for driving the data signal lines, and the drive circuit for driving the scanning signal lines are formed on the same substrate.

As a result, compared with the case where each pixel display section and each drive circuit are mounted on separate substrates, the cost associated with mounting can be reduced and the reliability at the time of mounting can be improved. You can Further, the number of external connection pins and the width of the data signal line drive circuit can be reduced.

Further, the switching elements provided in the pixel display section, the drive circuit for driving the data signal lines, and the drive circuit for driving the scanning signal lines are more preferably polycrystalline silicon thin film transistors.

As a result, the pixel display section and the drive circuit can be formed on the same substrate by the same process, and the manufacturing cost of the matrix type image display device can be reduced.

It is more preferable that the switching element is formed on a glass substrate by a process at 600 ° C. or lower.

As a result, the polycrystalline silicon thin-film transistor can use an inexpensive glass substrate having a low melting point, which can reduce the cost of the matrix type image display device and increase the area of the display portion.

Further, the polycrystalline silicon thin film transistor has a large variation in characteristics among the elements as compared with the single crystalline silicon transistor, but with the above configuration, the polycrystalline silicon thin film transistor is used as a highly accurate reference. The present invention is particularly effective in that it is not necessary to create an electric potential.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] FIG. 1 shows an embodiment of a matrix type image display device of the present invention.
The following is a description with reference to FIG.

Matrix-type image display device 1 of this embodiment
As shown in FIG. 2, 0 is a pixel array 3 in which a plurality of pixels 2 are arranged in a matrix, and a data signal drive circuit SD5.
And the scanning signal line drive circuit GD6 is a single insulating substrate 7.
It is monolithically formed on the top.

The pixel array 3 includes a plurality of scanning signal lines GL1, GL2, ..., Gly (hereinafter collectively referred to as GL) and data signal lines SL1, SL2, ...
, SLx (hereinafter collectively referred to as SL). Then, the pixel 2 is arranged in a portion surrounded by the two adjacent scanning signal lines GL and the adjacent data signal lines SL.

The data signal line drive circuit SD5 samples the input digital video signal DAT in synchronization with a timing signal such as a clock signal SCK, converts and amplifies the signal as necessary, and each data signal line SL. Write in.

The scanning signal line drive circuit GD6 synchronizes with the scanning signal line GL in synchronization with a timing signal such as a clock signal GCK.
Are sequentially selected to open and close the switch element in the pixel 2. As a result, a signal corresponding to the digital video signal DAT written in each data signal line SL is written in each pixel 2, and the written signal is held within the range of the capacity of each pixel 2.

A control circuit CTL8 for supplying various control signals and a power supply circuit SPL9 are connected to the data signal line drive circuit SD5 and the scanning signal line drive circuit GD6. Then, the digital video signal DAT input from the control circuit CTL8 is converted into an analog potential corresponding to the input digital amount in the data signal line drive circuit SD5 and output to the data signal line SL.

As described above, the pixel array 3 and the data signal driving circuit SD5 and the scanning signal line driving circuit GD6 are formed on the same insulating substrate 7, that is, monolithically formed. The manufacturing cost and the mounting cost of each drive circuit can be reduced as compared with the case where the drive circuits 5 and 6 are separately configured and mounted. Furthermore, by forming them on the same substrate, it is possible to reduce the occurrence of connection failure during mounting and improve the reliability of the device.

Each pixel 2 of the matrix type image display device 10
In FIG. 1, as shown in FIG. 1, an externally input digital video signal which is a source of a video signal to be written in the pixel 2 has upper M bits and lower L bits (M ≠ 0, L ≠).
0) for a total of N bits, the pixel 2 has an area ratio of 2 ^M : 1 and the first pixel display unit 11 and the second pixel display unit 1
It is divided into two areas of 2 and the switching element T1 is provided in each of the first and second pixel display sections 11 and 12.
・ T2 is provided.

The switching element T1 has a drain electrode connected to the pixel electrode forming the first pixel display section 11, a gate electrode connected to the scanning signal line GL, and a source electrode connected to the data signal line SL1. It has and.

Similarly, the switching element T2 is also connected to the drain electrode connected to the pixel electrode forming the second pixel display section 12, the gate electrode connected to the scanning signal line GL, and the data signal line SL2. And a source electrode.

That is, the switching elements T1 and T2
Writes the signal potentials respectively input to the two data signal lines SL1 and SL2 to the first and second pixel display sections 11 and 12 according to the High / Low of the scanning signal line, and holds the written signals. is doing.

In this way, the divided pixel display section (first
-The second pixel display section 11 and 12) is the switching element T
By having 1 and T2 respectively, the first and second
It is possible to control the pixel display units 11 and 12 independently of each other, and arbitrary gradation display is possible.

Of the N-bit digital video signals of upper M bits and lower L bits input from the outside, a 2 ^M gradation signal corresponding to the upper M bits of the digital video signal is applied to the data signal line SL1. In addition to being output, a 2 ^L gradation signal corresponding to the lower L bits of the digital video signal is output to the data signal line SL2, and each signal is displayed through the switching elements T1 and T2 to display the first and second pixels. Written in the sections 11 and 12, respectively.

At this time, the table in the first pixel display section 11 is
The actual transmittance for the first pixel display unit is the transmittance A.
11 display gradations (integers) are A display gradations (0 ≦ A display gradations
<2 ^M),   Transmittance A = (A display gradation / 2^M) × (area of first pixel display area / total pixel surface Product) × 100           = (A display gradation / 2^M) × {2^M/ (2^M+1)} × 100           = {A display gradation / (2^M+1)} × 100 (%) ... It is represented by.

As for the second pixel display section 12, similarly to the above, the actual transmittance for the display of the second pixel display section 12 is the transmittance B, and the display gradation (integer) of the second pixel display section is the same. If it is expressed as B display gradation (0 ≦ B display gradation <2 ^L ), transmittance B = (B display gradation / 2 ^L ) × (area of second pixel display unit 12 / total area of pixels) × 100 = (B display gradation / ^2L ) × {1 / ( ^2M + 1)} × 100 = {B display gradation / ^2L ( ^2M + 1)} × 100 (%) ... It

Therefore, the final transmittance of the whole pixel is calculated by the following equation: pixel transmittance = transmittance A + transmittance B = {A display gradation / (2 ^M +1) + B display gradation / 2 ^L (2 ^M +1)} × 100 = {(A display gradation + B display gradation / 2 ^L ) / (2 ^M +1)} × 100 (%) ...

Here, in the equation, the total number of gradations represented as pixel transmittance is as follows.

Total gradation number = A display gradation number 2 ^M × B display gradation 2 ^L = 2 ^{M + L} = 2 ^N That is, the upper M bits and lower L bits (M ≠ 0, L Assuming that M> L for a total of N bit digital video signals (≠ 0), 2 ^M reference voltages are prepared, and the reference is provided to each of the first pixel display unit 11 and the second pixel display unit 12. By writing a voltage, 2 ^N gradation display is possible.

In order to more specifically explain the gradation display by the matrix type image display device 10 as described above, the present invention is applied by dividing the 4-bit digital video signal into upper 3 bits and lower 1 bit. The pixel configuration example will be described below with reference to FIG.

In the above case, the first and second pixel display portions 11 and 12 are divided by the area ratio of 8 (= 2 ³ ): 1, and the first and second pixel display portions 11 and 12 are divided. Display 11
A switching element T1 and a switching element T2 are provided in 12 respectively.

As a result, in each of the first and second pixel display portions 11 and 12, writing / writing of signals is performed independently.
It becomes possible to hold, and signals of 8 gradations and 2 gradations are written in the first pixel display section 11 and the second pixel display section 12, respectively. The gradation signal is expressed by reference voltages Vref0 to Vref7 input from the outside, and Vref0 to Vref is displayed in the first pixel display unit 11.
7 is written in the second pixel display unit 12, either Vref0 or Vref4.

The transmittances of the first and second pixel display portions 11 and 12 for each Vref are Vref as shown in FIG.
0 is 0% transmittance, Vref1 is 14.3% transmittance,
Each Vre so that the transmittance is 100.0% at Vref7.
f is set.

At this time, the respective transmittances of the first and second pixel display portions 11 and 12 of the pixel configuration shown in FIG. 3 are as shown in FIG. 5A, and as a result, the transmittance of the entire pixel is increased. Sixteen ratios can be obtained by combining the A transmittance and the B transmittance shown in FIG. 5B. That is, according to the matrix-type image display device 10 of the present invention, 16 gradations can be expressed by inputting reference voltages for 8 gradations, and more gradations than the input reference voltage can be displayed. become.

In FIG. 5B, the maximum value of the A transmittance and the maximum value of the B transmittance are not 100% even if they are added. This is because in the second pixel display unit 12,
100% can be obtained by adding the gradation voltage at Vref7 in addition to the addition of the gradation voltage at Vref0 and Vref4, because Vref7 is not added in order to minimize the gradation voltage line. is there. However, naturally, in the second pixel display section 12, the effect of the present invention can be obtained even when Vref7 is added to make the total 100%.

Here, the data signal line drive circuit SD5 is provided, and according to the digital video signal input from the outside to the data signal lines SL1 and SL2 of FIG.
An example of the configuration of the D / A conversion circuit that outputs an analog video signal will be described with reference to FIG.

As shown in FIG. 6, this D / A conversion circuit includes a decoder circuit DCM15, a selection circuit SEM17, a decoder circuit DCL16, and a selection circuit SEL18.

The decoder circuit DCM15 generates a predetermined output signal according to the upper M bits of the digital video signal input from the outside. That is, one of the output lines DOM (1) to DOM (2 ^M ) is activated and the other output lines are deactivated according to the input digital signal.

The selection circuit SEM17 is a decoder circuit DC.
A predetermined reference voltage is selected by receiving the output of M15. That is, by receiving the output of the decoder circuit DCM15 and connecting a predetermined reference voltage line to the data signal line SL1, the output SOM corresponding to the upper M bits of the digital video signal is written to SL1.

The decoder circuit DCL16 also generates a predetermined output signal according to the lower L bits of the digital video signal input from the outside. In other words, one of the active of in accordance with the input digital signal output line ^{DOL (1) ~DOL (2 L} ), other output line DOL is inactive.

The selection circuit SEL18 is a decoder circuit DC.
The output of L16 is received and a predetermined reference voltage is selected. That is, by receiving the output of the decoder circuit DCL16 and connecting a predetermined reference voltage line to the data signal line SL2, the output SOL corresponding to the lower L bits of the digital video signal is written to the data signal line SL2.

Then, each of the two data signal lines SL
The outputs SOM and SOL corresponding to the lower L bits of the digital video signal input to 1 and SL2 are written to the first and second pixel display units 11 and 12, and the first and second pixel display units 11 and 12 are also written. -Retained within the 12 capacity range.

Matrix-type image display device 1 of this embodiment
At 0, as described above, the data signal line drive circuit S
Output to D5 data signal lines SL1 and SL2 SOM and SO
An output SOM having a D / A conversion circuit for inputting L and corresponding to upper M bits and upper L bits (M ≠ 0, L ≠ 0) of an externally input digital video signal
SOL (video signal potential) is written in each of the divided first and second pixel display portions 11 and 12.

As a result, more gradation display than the input reference voltage can be performed, the number of input reference voltages can be reduced as compared with the prior art, and multi-gradation display can be performed. Further, by reducing the number of input reference voltages, the load on the D / A conversion circuit can be reduced and the circuit can be downsized. Furthermore, the number of external connection pins and the width of the data signal line drive circuit can be reduced, and it is possible to provide a matrix type image display device capable of reducing power consumption and reducing the frame area of the device.

[Second Embodiment] A matrix type image display device 30 showing another embodiment of the image display device of the present invention will be described with reference to FIGS. 7 to 14.

For convenience of explanation, the same members as the members described in the drawings described in the first embodiment will be designated by the same reference numerals, and the description thereof will be omitted.

The present embodiment and the first embodiment are different from each other in the data signal line SL and the scanning signal line G connected to one pixel.
The difference is that the number of L is different. That is, the pixel 2 of the matrix-type image display device 10 of the first exemplary embodiment includes two data signal lines SL1 and SL2 and one scanning signal line GL.
While the pixel 2 ′ of the matrix type image display device 30 of the present embodiment is connected to one data signal line S,
L and the two scanning signal lines GL1 and GL2 are connected.

Matrix-type image display device 3 of this embodiment
As shown in FIG. 7, 0 is a pixel array 3 in which a plurality of pixels 2 ′ are arranged in a matrix, and a data signal drive circuit SD5, as in the matrix type image display device 10 of FIG. 2 described in the first embodiment. The scanning signal line drive circuit GD6 and the scanning signal line drive circuit GD6 are monolithically formed on the same insulating substrate 7.

Further, the matrix type image display device 30 is
As in the first embodiment, the pixel 2 ′ is divided into two regions, and the digital video signal input from the outside is classified into the upper M
Assuming a total of N bits including 1 bit and lower L bits (M ≠ 0, L ≠ 0), the area ratio of the divided first pixel display section 11 ′ and second pixel display section 12 ′ is 2 ^M : 1. Therefore, the first and second pixel display portions 11 'and 12' are provided with the switching elements T1 and T2 independently of each other.

The drain electrode of the switching element T1 provided in the first pixel display section 11 'is connected to the pixel electrode forming the first pixel display section 11', and the gate electrode is connected to the scanning signal line GL1. The source electrode is connected to the data signal line SL.

On the other hand, the drain electrode of the switching element T2 included in the second pixel display section 12 'is connected to the pixel electrode forming the second pixel display section 12', and the gate electrode is connected to the scanning signal line GL2. The source electrode is connected to the data signal line SL similarly to the switching element T1.

That is, the switching elements T1 and T2
Respectively write the signal potentials, which are time-divisionally input to the data signal line SL, to the first and second pixel display portions 11 ′ and 12 ′ according to the High / Low of the scanning signal lines GL1 and GL2, respectively. Holds the signal.

Among the N-bit digital video signals of upper M bits and lower L bits input from the outside, a 2 ^M gradation signal corresponding to the upper M bits of the digital video signal is supplied to the scanning signal line GL1. , Digital video signal lower L
A 2 ^L gradation signal corresponding to a bit is output to the data signal line SL in a form synchronized with the scanning signal line GL2, and the respective signals are passed through the switching elements T1 and T2 to the first and second portions.
Are written in the pixel display portions 11 'and 12'.

Here, the D / A conversion circuit for outputting the analog video signal voltage to the data signal line SL in FIG. 8 according to the digital video signal input from the outside will be described with reference to FIG. To do.

This D / A conversion circuit is composed of a latch circuit LAT.
M19, decoder circuit DCM21, selection circuit SEM2
3, latch circuit LATL20, decoder circuit DCL2
2. Select circuit SEL24 and analog switch ANS
Equipped with 1.ANS2.

The latch circuit LATM19 holds the upper M bits of the digital video signal input from the outside. On the other hand, the latch circuit LATL20 holds the lower L bits of the digital video signal input from the outside. That is, the digital signals input to each are held for a predetermined period, and a signal having the same value as the signal or a signal corresponding thereto is output to the decoder circuit D.
Output to the CM 21/22 for a predetermined period.

The decoder circuit DCM21 has a latch circuit L.
A predetermined output signal is generated according to the signal corresponding to the upper M bits of the digital video signal input from the outside and output from the ATM 19. That is, one of the output lines DOM (1) to DOM (2 ^M ) is activated and the other output lines are deactivated according to the input signal.

On the other hand, the decoder circuit DCL22 generates a predetermined output signal according to the signal corresponding to the lower L bits of the digital video signal input from the outside which is output from the latch circuit LATL20. That is, according to the input digital signal, the output lines DOL (1) to DOL
One of (2 ^L ) is active and the other output lines are inactive.

The selection circuit SEM23 is a decoder circuit DC.
A predetermined reference voltage is selected by receiving the output of M21, that is, a predetermined reference voltage line potential is output SO
Let M. On the other hand, the selection circuit SEL24 receives the output of the decoder circuit DCL22 and selects a predetermined reference voltage, that is, sets a predetermined reference voltage line potential as the output SOL.

The analog switches ANS1 and ANS2 are
The output S of the selection circuit SEM23 with respect to the data signal line SL
The output / non-output of the output SOL of the OM and the selection circuit SEL24 is controlled. That is, each selection circuit SEM2
The outputs SOM and SOL which are the outputs of the 3.SEL 24 are selectively output in accordance with the driving of the scanning signal lines GL1 and GL2 in FIG.

Matrix-type image display device 3 of this embodiment
With the above-described configuration, 0 is provided in each of the first and second pixel display portions 11 ′ and 12 ′ divided into 2 ^M : 1 as in the matrix type image display device 10 of the first embodiment.
A signal corresponding to the upper M bits and the lower L bits (M ≠ 0, L ≠ 0) of the externally input digital video signal is written.

As a result, even with the configuration of the matrix-type image display device 30 of the present embodiment, it is possible to display more gradations than the number of gradation signals of the input reference voltage, as in the first embodiment. Therefore, it is possible to perform multi-gradation display while reducing the number of input reference voltages as compared with the related art. Further, by reducing the number of input reference voltages, the load on the D / A conversion circuit can be reduced and the circuit can be downsized. Further, it is possible to reduce the number of external connection pins and the width of the data signal line drive circuit, and it is possible to provide a matrix-type image display device that performs multi-gradation / high-quality image display.

Here, the scanning signal line GL in the pixel configuration of the matrix type image display device 10 shown in FIG. 2 and the pixel configuration of the matrix type image display device 30 shown in FIG.
FIG. 10 shows the temporal relationship between the data signal line SL and the data signal line SL.
The following is a description with reference to (a) and FIG. 10 (b).

The matrix type image display device 10 described in the first embodiment can output the data written in the data signal lines SL1 and SL2 in parallel (in parallel), as shown in FIG. As a result, the selection circuit SEM1
7 and the output of the selection circuit SEL18 make it possible to secure a long time for writing the video signal to the data signal lines SL1 and SL2. As a result, the selection circuit SEM17
Also, the driving capability of the output section of the selection circuit SEL18 can be reduced, and the circuit scale can be reduced and the power consumption can be reduced. Furthermore, display unevenness due to insufficient charging of the data signal line can be avoided.

On the other hand, since the matrix type image display device 30 of this embodiment has only one data signal line SL to be output, as shown in FIG. 10B, data is serially output to the same data signal line. There is a need to. Further, for example, in the layer structure shown in FIG. 11, in order to avoid the overlap between the data signal line SL and the pixel electrode, considering the interference of the data signal line, which is a layer relatively close to the pixel electrode, with the pixel electrode. When the layout is performed, the number of each signal line SL / GL can be set to a maximum of two as compared with the conventional matrix type image display device in which one pixel is divided into a plurality of pixels. The area occupied by the signal lines SL and GL can be reduced, and the area of the display portion can be increased.
It is possible to obtain a matrix type image display device capable of displaying a higher definition image.

Further, regarding the matrix type image display device 10 of the first embodiment and the matrix type image display device 30 of the present embodiment, each device 10/30 is constructed by using a polycrystalline silicon thin film transistor 31 as shown in FIG. In this case, the data signal line driving circuit SD5 and the scanning signal line driving circuit GD6 having a practical driving capability can be formed on the same insulating substrate 7 as the pixel array 3 by the same manufacturing process. Manufacturing cost can be reduced.

The polycrystalline silicon thin film transistor 31 described here has a forward stagger (top gate) structure in which a polycrystalline silicon thin film on an insulating substrate is used as an active layer, but the present invention is not limited to this. Not something.
For example, even if the structure is another structure such as an inverted stagger structure, the same effect as described above can be obtained.

The manufacturing process for forming the polycrystalline silicon thin film transistor 31 at 600 ° C. or lower will be briefly described below with reference to FIGS. 14 (a) to 14 (k).

Matrix-type image display device 1 according to the present invention
In the manufacturing process of the thin film transistor which constitutes 0.30,
On the glass substrate 32 shown in FIG.
As shown in FIG. 1, an amorphous silicon thin film 33 is deposited, and FIG.
4C, the excimer laser 34 is irradiated to form a polycrystalline silicon thin film 33 '.

Next, as shown in FIG. 14 (d), this polycrystalline silicon thin film 33 'is patterned into a desired shape, and a gate insulating film 36 made of silicon dioxide is formed as shown in FIG. 14 (e). Form.

Further, as shown in FIG. 14 (f), after forming the gate electrode 37 of the thin film transistor with aluminum or the like, as shown in FIGS. 14 (g) and 14 (h), the source / drain region of the thin film transistor is formed. Impurities (phosphorus P in the n-type region and boron B in the p-type region) are implanted into.

Thereafter, as shown in FIG. 14I, the interlayer insulating film 3 made of silicon dioxide, silicon nitride, or the like is used.
8 is deposited and a contact hole 39 is opened as shown in FIG. 14 (j), and then a metal wiring 40 of aluminum or the like is formed as shown in FIG. 14 (k).

In this step, since the maximum temperature of the process is 600 ° C. at the time of forming the gate insulating film, high heat resistant glass such as Corning 1737 glass can be used.

If the matrix type image display device is, for example, a transmissive liquid crystal display device, a transparent electrode is formed via another interlayer insulating film, and if it is a reflective liquid crystal display device, a reflective electrode is formed. Will be formed.

As described above, in the manufacturing process as shown in FIGS. 14A to 14K, the polycrystalline silicon thin film transistor 31 is formed at 600 ° C. or less,
An inexpensive glass substrate having a large area can be used, and the cost reduction and the area increase of the matrix type image display device can be realized.

Although the embodiments of the present invention have been shown above, the present invention is not limited to these, and the same effects can be obtained even with other configurations including the number, types, and polarities of signals used. Can be obtained.

The matrix type image display device of the present invention
Cross a plurality of data signal lines and the data signal lines
A plurality of scanning signal lines, and a plurality of data signal lines
Arranged in a matrix at each intersection with the scanning signal line
Equipped with a plurality of pixel display units, the upper M as a video signal
Bit (M ≠ 0), lower L bits (L ≠ 0) digital
In a matrix type image display device to which a signal is input,
The pixel display section has 2 ^MDivided into two with an area ratio of: 1
The divided pixel display section has the above digital signal.
The converted analog video signal potential is written
And a matrix type image display device characterized by
You can also do it.

With the above structure, the same effects as the effects of the present invention described above can be obtained.
It is possible to reduce the load on the D / A conversion circuit that converts a digital signal input from the outside into an analog video signal, and reduce the size of the D / A conversion circuit.

[0115]

According to the matrix type image display device of the present invention,
As described above, when the upper bits of the digital signal input as the video signal are M bits (M ≠ 0), the pixel display section is divided into two at an area ratio of 2 ^M : 1. In the pixel display portion corresponding to the area ratio of 2 ^M , the video signal potential corresponding to the digital signal of the upper M bits is written to the pixel display portion corresponding to the area ratio of 2 ^M The video signal potential corresponding to the digital signal of the other lower bits is written in the display section.

Therefore, the pixel display portion is divided at an area ratio of 2 ^M : 1 and the video signal potential is written independently for each divided pixel display portion. Therefore, even when the video signal potential of the same value is written in each pixel display unit, the video signal is weighted by the area ratio,
It is possible to obtain the effect that the sum of the numbers of gradation signals written in the divided pixel display sections can be set as the actual number of gradation signals of the entire pixel.

The divided pixel display area is 2 ^M : 1.
Since each pixel is only divided into two at an area ratio of 1, the divided pixels are provided in comparison with the case where the divided pixel is divided into a plurality of three or more as in the conventional image display device. The number of data signal lines and scanning signal lines corresponding to the existing switching elements can be reduced to two at maximum. Therefore, compared with the conventional matrix type image display device, the power consumption of the device can be reduced, the area occupied by the wiring on the substrate can be reduced, and the display area can be enlarged to enable higher-definition image display. .

Further, for the divided pixel display section,
If a gradation display is performed by writing an analog video signal corresponding to a digital signal, and a D / A conversion circuit for converting the digital video signal into an analog video signal is provided, the D / A conversion circuit is included. The device size can be reduced by reducing the circuit scale of the peripheral circuit.

As described above, in the matrix type image display device of the present invention, the upper bits of the digital signal input as the video signal are M bits (M ≠ 0) and the lower bits are L bits (L ≠ 0). , The pixel display section is divided into two at an area ratio of 2 ^M : 1. Among the divided pixel display sections, a pixel display section corresponding to 2 ^{M of the} above area ratio has 2
A video signal potential of ^M gray scales is written, and a video signal potential of 2 ^L gray scales is written to the pixel display section corresponding to 1 of the above area ratio.

Therefore, it is possible to perform gradation display with (M + L) -bit gradation, which is the sum of the numbers of bits of the M-bit gradation signal and the L-bit gradation signal written in each divided pixel display section. . Therefore, the number of gradation signals actually displayed can be increased more than the number of gradation signals of the input reference potential.

The divided pixel display area is 2 ^M : 1.
Since each pixel is only divided into two at an area ratio of 1, the divided pixels are provided in comparison with the case where the divided pixel is divided into a plurality of three or more as in the conventional image display device. The number of data signal lines and scanning signal lines corresponding to the existing switching elements can be reduced to two at maximum. Therefore, compared with the conventional matrix type image display device, the power consumption of the device can be reduced, the area occupied by the wiring on the substrate can be reduced, and the display area can be enlarged to enable higher-definition image display. .

Furthermore, for the divided pixel display section,
If a gradation display is performed by writing an analog video signal corresponding to a digital signal, and a D / A conversion circuit for converting the digital video signal into an analog video signal is provided, the D / A conversion circuit is included. The device size can be reduced by reducing the circuit scale of the peripheral circuit.

Further, it is more preferable that each of the divided pixel display portions has a switching element for video signal writing / holding control.

Therefore, it becomes easy to independently control the first and second pixel display portions, and as described above, multi-gradation display can be performed with a smaller number of input gradation signals than the conventional one. The matrix type image display device can be obtained.

Further, the switching element included in the divided pixel display section has a drain electrode connected to the pixel electrode of the divided pixel display section and a gate electrode connected to a common scanning signal line. More preferably, the source electrodes are connected to different data signal lines.

Therefore, the data to be written in different data signal lines can be output in parallel,
It is possible to secure a long time for writing the video signal to both the data signal lines. As a result, for example, it is possible to reduce the driving ability of the output unit such as the selection circuit, reduce the circuit scale, reduce power consumption, and avoid display unevenness due to insufficient charging of the data signal lines.

The switching element included in the divided pixel display section includes a drain electrode connected to a pixel electrode of the divided pixel display section, and a gate electrode connected to different scanning signal lines. More preferably, the source electrode and the source electrode connected to the common data signal line are provided.

Therefore, considering the interference between the pixel electrode and the pixel electrode of the data signal line, it is necessary to lay out the data signal line and the pixel electrode in the manufacturing process so as not to overlap each other. According to the configuration of the present invention, even in that case, the ratio of the pixel display portion to the whole pixel can be made larger than that of the conventional one.

It is more preferable that the pixel display section, the drive circuit for driving the data signal lines, and the drive circuit for driving the scanning signal lines are formed on the same substrate.

Therefore, compared with the case where each pixel display section and each drive circuit are mounted on different substrates, the cost involved in mounting can be reduced and the reliability at the time of mounting can be improved. In addition, the number of externally connected pins and the width of the data signal line drive circuit can be reduced.

Further, the switching elements provided in the pixel display section, the drive circuit for driving the data signal lines and the drive circuit for driving the scanning signal lines are more preferably polycrystalline silicon thin film transistors.

Therefore, the pixel display section and the driving circuit can be formed on the same substrate by the same process, and the manufacturing cost of the matrix type image display device can be reduced.

It is more preferable that the switching element is formed on a glass substrate by a process at 600 ° C. or lower.

Therefore, the polycrystal silicon thin film transistor can use an inexpensive glass substrate having a low melting point, and has the effect of reducing the cost of the matrix type image display device and increasing the area of the display portion. .

[Brief description of drawings]

FIG. 1 is a plan view showing a pixel configuration of a pixel display unit included in a matrix-type image display device according to an embodiment of the present invention.

FIG. 2 is a plan view showing an example in which the pixel configuration of FIG. 1 is applied to a driver monolithic matrix type image display device.

FIG. 3 is a plan view showing a specific example of the pixel of FIG.

FIG. 4 is a graph showing a relationship between a signal voltage and a pixel display section transmittance in the pixel configuration of FIG.

5A and 5B are diagrams showing the transmittance of each display section in the pixel configuration of FIG.

6 is a circuit diagram showing a configuration example of a D / A conversion circuit included in a data signal line drive circuit of the matrix type image display device of FIG.

7 is a plan view showing an example of a driver monolithic matrix type image display device shown as an example different from the matrix type image display device of FIG. 1. FIG.

FIG. 8 is a plan view showing a pixel configuration of a pixel display unit included in the driver monolithic matrix type image display device of FIG.

9 is a circuit diagram showing a configuration example of a D / A conversion circuit included in a data signal line drive circuit of the matrix type image display device of FIG.

10A and 10B are diagrams showing drive timings in a pixel display section of the matrix image display device of FIGS. 1 and 8.

11 is a schematic diagram showing an example of a pixel configuration in the matrix type image display device of FIG.

12A and 12B are plan views showing pixel display portions in the matrix-type image display device of FIGS. 1 and 8, respectively.

FIG. 13 is a cross-sectional view showing the structure of a polycrystalline silicon thin film transistor which constitutes the matrix image display device of FIGS. 2 and 7.

14A to 14K are cross-sectional views showing a manufacturing process of the polycrystalline silicon thin film transistor of FIG.

FIG. 15 is a plan view showing a configuration of a conventional active matrix image display device.

FIG. 16 is a plan view showing a configuration of a conventional driver monolithic image display device.

FIG. 17 is a circuit diagram showing a configuration of a 4-bit D / A conversion circuit.

FIG. 18 is a plan view showing a pixel configuration in a conventional matrix type image display device.

19 is a graph showing the relationship between signal voltage and transmittance in the pixel configuration of FIG.

[Explanation of symbols]

2.2 'pixel 3 pixel array 5 Data signal line drive circuit SD 6 Scan signal line drive circuit GD 7 Insulation board 8 Control circuit CTL 9 Power supply circuit SPL 10 Matrix type image display device 11.11 'First pixel display section 12.12 'second pixel display section 15 Decoder circuit DCM 16 Decoder circuit DCL 17 Selection circuit SEM 18 Selection circuit SEL 19 Latch circuit LATM 20 Latch circuit LATL 21 Decoder circuit DCM 22 Decoder circuit DCL 23 Selection circuit SEM 24 Selection circuit SEL 30 Matrix type image display device 31 Polycrystalline silicon thin film transistor 32 glass substrate 33 Amorphous silicon thin film 33 'polycrystalline silicon thin film 34 Excimer laser 36 Gate insulation film 37 Gate electrode 38 Interlayer insulation film 39 contact holes 40 metal wiring SL data signal line GL scanning signal line Cs auxiliary capacity T-transistor

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 641 G09G 3/20 641G H04N 5/66 H04N 5/66 A (72) Inventor Kenichiro Ishikura 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture, F-term in Sharp Corporation (reference) 2H093 NA16 NA53 NA54 NA59 NC13 NC21 NC34 NC40 ND06 ND39 ND42 ND49 NE03 5C006 AA12 BB16 BC03 BC06 BC11 BC16 BC20 BF24 BF26 BF34 FA51 FA42 FA47 FA47 FA56 GA03 5C058 AA06 AB01 BA01 BA07 BB25 5C080 AA10 BB05 DD05 DD23 DD26 DD27 EE29 FF11 JJ02 JJ04 JJ05 JJ06

Claims (8)

[Claims] 1. A plurality of data signal lines and a plurality of scanning signal lines intersecting with the data signal lines, wherein the plurality of data signal lines and the scanning signal lines are arranged in a matrix at respective intersections. In a matrix-type image display device having a plurality of pixel display units, if the upper bits of a digital signal input as a video signal are M bits (M ≠ 0), the pixel display unit
It is divided into two at an area ratio of 2 ^M : 1 and, of the divided pixel display sections, the pixel display section corresponding to 2 ^{M of the} above area ratio corresponds to the digital signal of the upper M bits. And a video signal potential corresponding to the digital signal of the lower bit other than the above is written to the pixel display unit corresponding to the above area ratio of 1. . 2. A plurality of data signal lines and a plurality of scanning signal lines intersecting with the data signal lines, which are arranged in a matrix at each intersection of the plurality of data signal lines and the scanning signal lines. In a matrix-type image display device having a plurality of pixel display units, the upper bits of a digital signal input as a video signal are M bits (M ≠ 0) and the lower bits are L bits (L ≠ 0).
Then, the pixel display section is divided into two at an area ratio of 2 ^M : 1. Among the divided pixel display sections, the pixel display section corresponding to the area ratio of 2 ^M is A matrix-type image display device characterized in that a video signal potential of 2 ^M gradations is written and a video signal potential of 2 ^L gradations is written in a pixel display section corresponding to 1 of the above area ratio. . 3. The matrix type image display device according to claim 1, wherein each of the divided pixel display sections has a switching element for controlling video signal writing / holding. 4. The switching element included in the divided pixel display section includes a drain electrode connected to a pixel electrode of the divided pixel display section, and a gate electrode connected to a common scanning signal line. The matrix-type image display device according to claim 3, further comprising source electrodes connected to different data signal lines. 5. The switching element included in the divided pixel display section includes a drain electrode connected to a pixel electrode of the divided pixel display section, and a gate electrode connected to mutually different scanning signal lines. The matrix type image display device according to claim 3, further comprising a source electrode connected to a common data signal line. 6. The pixel display section, a drive circuit for driving the data signal line, and a drive circuit for driving the scanning signal line are formed on the same substrate. The matrix type image display device according to any one of 1. 7. A switching element provided in the pixel display section, a drive circuit for driving the data signal line, and a drive circuit for driving the scanning signal line is a polycrystalline silicon thin film transistor. Item 7. The matrix type image display device according to any one of items 1 to 6. 8. The matrix type image display device according to claim 7, wherein the switching element is formed on a glass substrate by a process at 600 ° C. or lower.