JP2003179588A - Frame synchronous circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frame synchronous circuit and a method which reduce amount of frame timing offset by using a delay wave under environment of Rayleigh fading and multipath fading. <P>SOLUTION: This frame synchronous circuit which detects a synchronous signal of a receiving signal in digital radio communication and sets up frame synchronization is constituted of an address generating circuit for giving an address to a storage device, the storage device which stores a correlation value between the receiving signal and a prescribed synchronous signal pattern every frame unit, on the basis of an address given by the address circuit, and a frame correlation peak detecting circuit which detects a frame peak value showing the maximum value among stored correlation values, every time when correlation values per frame are stored in the storage device and decides an address corresponding to the frame peak value to be a frame synchronous position. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital radio communication, and more particularly to a frame synchronization circuit and method for extracting time division multiplexed sync word positions.

[0002]

2. Description of the Related Art The structure of a conventional synchronous word detection type frame synchronization circuit is shown in FIG. The received IF (intermediate frequency) signal is separated by the quadrature detector 1 into quadrature I and Q signals. The quadrature I and Q signals are converted into digital signals by the A / D converter 9 at a cycle twice or more the symbol rate and input to the complex number correlator 2, where complex number correlation calculation with the sync word pattern is performed. The correlation value signal a is output in time series. The window circuit 3 performs windowing of a window range b (2 symbols to 5 symbols before and after) on the correlation value signal a, is synchronized with the frame synchronization reproduction signal, and has correlation power (hereinafter referred to as correlation value) other than the vicinity of the frame synchronization reproduction signal position. ) 0
It is a circuit. In the comparator 4, the fact that a correlation peak appears at the time of receiving a synchronization word is used, and a position exceeding the threshold value is compared with a threshold value 5 (for example, set to about 25% to 75% of the maximum value of the correlation peak). (Correlation peak detection position) is detected and output as a coarse synchronization pulse d at the frame position. A PLL (Phase Locked Loop) 6 finely controls the frame synchronization signal in the direction in which the phase is synchronized with the coarse synchronization pulse based on the positional relationship between the frame synchronization reproduction signal and the coarse synchronization pulse.

The mode control circuit 7 controls the following three modes of operation. Initial phase pull-in waiting mode When the frame synchronization is started, the changeover switch 8 is set so that the window circuit 3 is in the through state, and the correlation value signal a is directly input from the complex number correlator 2 to the comparator 4. further,
It is monitored that the output d of the comparator 4 becomes H (a correlation value exceeding the threshold value is generated). When the output d of the initial phase pull-in mode comparator 4 becomes H, the PLL 6 is reset and the phase of the frame synchronization reproduction signal is adjusted. next,
The changeover switch 8 is the output side of the window circuit 3,
The input to the comparator 4 is switched to the output of the window circuit 3, and the correlation value outside the window range is set to zero. In order to detect the correlation peak in the forward protection mode window, the output of the comparator 4 is monitored every frame, and the output of the comparator 4 becomes H in the section of the number N of monitored frames (N is an integer value of 5 or more). The number of times is counted by an internal counter. When the count value e is less than K (K is an integer value of 1 to N), it is determined that the frame synchronization is bad, and the process returns to. However, when it is K or more, the control output for repeating the frame synchronization is repeated. The switch 8 is controlled by f.

FIG. 7 shows the above operation as a signal flow.
become that way. Since the correlation value signal a becomes a signal having a correlation peak in the frame synchronization, in the initial phase pull-in waiting mode, the correlation peak position detection that exceeds the threshold value first is awaited. When the correlation peak exceeding the threshold value is input, the output d of the comparator 4 becomes H, and the window range b which is the initial phase pull-in mode operation is set, and the input to the comparator 4 is switched after passing the window. I do. After that, the forward protection mode is entered, and the quality of the synchronization is checked by monitoring the frame synchronization good counter value e.

[0005]

With the above operation, it is possible to output a frame synchronization reproduction signal synchronized with the transmission frame. However, when the conventional method is applied to a mobile communication line, there are the following problems. Timing offset due to level fluctuation in Rayleigh fading. Timing offset due to the effect of delayed waves in multipath fading.

FIG. 8 shows an example of correlation peak characteristics. The time deviation from the frame synchronization position (0) (horizontal axis) versus the correlation value (vertical axis) is shown. The simulation conditions are: correlator input sampling rate = symbol rate × 8, sync word length = 1
It is a 0 symbol. As can be seen from the figure, the correlation peak characteristic has a peak at the frame synchronization position (0) of about 2T.
It is a mountain-shaped characteristic with a width of In the peak detection by the threshold value as in the conventional method, in consideration of the level fluctuation of the peak value due to Rayleigh fading, the normal peak value of 25 to
It is necessary to set 75% as a threshold value to prevent detection omission, and as a result, detection is performed slightly before the peak position in time. If there is no level fluctuation, the timing offset amount is a fixed amount, and can be adjusted to some extent by the delay circuit. However, the detected position is constantly changed due to the level change, which causes a timing offset.

Further, in the multipath fading, the influence of a delayed wave (reflected wave or the like) complicates the problem in addition to the above level fluctuation. When the level of the preceding wave is low, the peak is detected not at the preceding wave (direct wave) but at the delayed wave position, and the average correlation peak detection position varies between the preceding and delayed waves depending on the fading situation. Will be done. Moreover, it is a big problem that the frame synchronization positions are greatly different depending on the propagation environment (Rayleigh fading and multipath fading). The influence of the delayed wave itself on the demodulator can be improved by removing the influence of the delayed wave by introducing an equalizer, but even in that case, the timing offset of the frame reproduction signal can be used. Degradation of equalizer performance with respect to error rate is a major problem.

In order to improve such drawbacks, the present invention provides a frame synchronization circuit and method for reducing the frame timing offset amount due to a delayed wave even in a Rayleigh fading or multipath fading environment.

[0009]

To achieve this object, a frame synchronization circuit according to the present invention detects an address of a received signal in digital radio communication and establishes a frame synchronization by assigning an address to a memory. An address generating circuit for giving, a memory for accumulating the correlation value between the received signal and a predetermined synchronizing signal pattern in frame units according to the address given by the address circuit,
Each time the correlation value for one frame is accumulated in the memory,
A frame correlation peak detection circuit that detects a frame peak value showing the maximum value among the accumulated correlation values and determines an address corresponding to the frame peak value as a frame synchronization position. Have a configuration.
Further, the frame synchronization circuit according to the present invention detects an synchronization signal of a received signal in digital radio communication and establishes frame synchronization. In the frame synchronization circuit, an address generation circuit for giving an address to a memory, the received signal and a predetermined synchronization signal pattern. A memory that accumulates the correlation value between and in a frame unit according to the address given by the address circuit, and every time the correlation value for one frame is accumulated in the memory, the maximum value among the accumulated correlation values A frame correlation peak detection circuit that detects the frame peak value shown and determines the address corresponding to the frame peak value as the frame synchronization position, and a window that uses the address of the frame synchronization position as the center address and the vicinity before and after the detection range. Is set, and the window pin showing the maximum value among the correlation values in the window is displayed. Detecting a click value and the window peak address, comparing the frame peak value and the window peak value over a predetermined number of frames N,
When the number of frames whose window peak value is larger than the frame peak value is equal to or greater than a predetermined set number K, the window peak address is determined to be the frame synchronization position, and the window peak address is determined to be the frame synchronization position. And a window correlation peak detection circuit for determining out of synchronization.

Furthermore, a frame synchronization method according to the present invention is a frame synchronization method for detecting a synchronization signal of a received signal in digital radio communication to establish frame synchronization,
A correlation value between the received signal and a predetermined synchronization signal pattern is stored in a memory in frame units according to an address given by the address circuit, and the correlation value is stored every time one frame of the correlation value is stored in the memory. Among the correlation values, a correlation value larger than a predetermined threshold value is detected, and the frame synchronization position is determined from the address corresponding to the correlation value.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below.
To do. An embodiment of the frame synchronization circuit of the present invention is shown in FIG.
You The correlation value signal a after complex number correlation is the address generation circuit.
10 generated addresses d_iAccording to the
Sequentially supplied as a column signal, the correlation value a _iIs accumulated.
Correlation value a for one frame_iFrame when the
Maximum value in one frame by the correlation peak detection circuit 12
The memory address g that gives (frame peak value p) is detected.
And the frame synchronization position h is determined.

FIG. 2 shows an embodiment for improving erroneous detection due to noise in the frame synchronization circuit of the present invention. The correlation value signal a after the complex number correlation is sequentially supplied to the memory 21 as a time series signal according to the address d _i generated by the address generator 20, and the correlation value a _i is stored. The following processing is performed for each frame when the correlation value a _i for one frame is stored. The frame correlation peak detection circuit 22 detects the frame peak value p and the address when it is stored in the memory 21 (hereinafter referred to as the frame peak address g), and the window correlation peak detection circuit 23 specifies the window center address h. The window peak value c ′ that gives the maximum value in the window range and the address when it is stored in the memory 21 (hereinafter referred to as window peak address k) are detected. Next, the frame peak value p and the window peak value c ′ are determined by the mode control circuit 2
4, and the frame peak address g and the window peak address k are input to the phase control circuit 25. The phase control circuit 25 uses the information from the mode control circuit 24 to determine the frame peak address g and the window peak address k.
The frame synchronization position (= window center address h) is output based on the information of.

The detailed operation of the mode control circuit 24 will be described. After receiving the correlation value for the first one frame after the start of the initial phase pull-in mode operation, the frame peak address g in the first frame
Is instructed to the phase control circuit 25 to set the frame synchronization position to shift to the forward protection mode (process A). Forward protection mode The peak value in the window and the peak value in the frame × α (α is 0 <α ≦ 1.0) are compared in size. As a result, when the peak value in the window is large, it is the same as the forward protection operation in FIG. Then, the number of times of good frame synchronization is counted up (process B
And). If the number of frames is less than K during N counts, it is determined that the frame synchronization is bad, and the process returns to. When it is K or more, the phase control circuit 25 determines that the frame synchronization is good.
To output the window peak address k as the frame synchronization position in the subsequent frames,
Is repeated (process C).

The above operation is shown in a processing flowchart in FIG. Blocks 40 to 42 in the figure are processes for the initial phase pull-in mode (process A), blocks 43 to 46 are processes for checking the peak value in the window (process B), and blocks 47 to 5
0 corresponds to the determination of whether the synchronization is good or bad (process C).
Further, by providing a function of averaging and outputting the window peak address k as the output of the phase control circuit 25, the fluctuation of the window peak address k is absorbed,
It is possible to stably output the frame synchronization position (h). It judges whether the phase is advanced or delayed by comparing the frame synchronization position (h) set in the previous frame with the window peak address k, and the frame synchronization position (h) is ± 1 as described below by statistical processing of the advance or delay. The fine adjustment is performed so that the relative position between the received signal and the frame synchronization position coincides with each other.

As a concrete example, the window peak address k and the frame synchronization position h in the previous frame are compared, 1 is subtracted when the window peak address k is in the front in the time series, and 1 when it is behind. A phase comparison counter for addition is provided, and when the value of the phase comparison counter is equal to or greater than the set value L (L is an integer value of 2 or more), 1 is added to the window peak address k, and when it is equal to or less than -L, the window peak The position variation of the window peak address k is averaged by subtracting 1 from the address k to obtain the frame synchronization position. With the above configuration, a true correlation peak (optimum frame synchronization position) can be stably detected with high accuracy, and the problem of timing offset due to level fluctuation in Rayleigh fading, which is the problem, can be solved.

Next, the operation in the problematic multipath fading environment will be described below. With the above configuration,
The flow of the signal when receiving the received signal including the delayed wave,
As shown in FIG. The correlation value signal a ′ is a signal having correlation peaks P _a1 , P _a2 , P _a3 , P _a4 ... In the frame period, but the correlation peaks appear at the positions of the preceding wave and the delayed wave. As an example, when the average level ratio of the preceding wave and the delayed wave is 0 dB, both the preceding wave and the delayed wave are selected as peaks with almost equal probability within the window range b ′.

In this case, the phase control circuit 25 operates so that the frame synchronization position (h) is located at the center of the two, and the phase cannot be synchronized with the original preceding wave position. As a second feature of the present invention, in order to solve such a drawback, the window range b _i 'is not equal to the front and rear as shown in FIG. 5, but the window width in front of the window center address h (= frame synchronization position). As b _i ′, W _F (W _F ≧ τ: τ is the maximum delay amount of the target delay wave), and the window width behind the window center address h is W _B (W _B is T _S ˜τ / 2: T _S is set so that the sampling interval of A / D = 1 / f _S ). With such a window setting, the window peak c _i 'always shows the peak position of the preceding wave to reduce the influence of the delayed wave, and it is possible to realize a frame synchronization circuit that synchronizes with the preceding wave even in a multipath environment. Becomes

Further, depending on the setting of W _B (T _{S to} τ / 2),
When the level of the preceding wave decreases and the level of the delayed wave is high for a long time continuously, the phase control circuit 25 can move the window center to the delayed wave position, and the synchronization is lost. Can be avoided. The setting of W _F is set so that the position of the preceding wave will be within the window range b ′ after the subsequent restoration of the preceding wave level, and the phase control circuit 25 can return to the preceding position without loss of synchronization. To

[0019]

As described in detail above, by carrying out the present invention, the frame synchronization position shift due to the influence of the delayed wave in the environment of Rayleigh fading or multipath fading is significantly reduced, so that the effect is remarkable. large.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame peak detection type frame synchronization circuit of the present invention.

FIG. 2 is a diagram showing an embodiment of a frame peak / window peak detection type frame synchronization circuit of the present invention.

FIG. 3 is a processing flowchart for explaining processing of the frame peak / window peak detection type frame synchronization circuit of the present invention.

FIG. 4 is an explanatory diagram showing a problem of a conventional window.

FIG. 5 is an explanatory diagram showing an effect of the window of the present invention.

FIG. 6 is a block diagram showing a configuration example of a conventional frame synchronization circuit.

FIG. 7 is an explanatory diagram of synchronization processing of a conventional method.

FIG. 8 is a correlation peak waveform diagram.

[Explanation of symbols]

1 Quadrature detector 2 Complex number correlator 3 window circuit 4 comparator 5 threshold 6 PLL 7, 24 mode control circuit 8 Changeover switch 9 A / D converter 10,20 address generator 11,21 memory 12,22 frame correlation peak detection circuit 23 Window correlation peak detection circuit 25 Phase control circuit

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[Procedure amendment]

[Submission date] January 24, 2003 (2003.1.2
4)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

4. A sync signal of a received signal in digital wireless communication is detected, and the received signal and a predetermined sync signal pattern are detected.
Before detecting the maximum value of the correlation signal with the
Set the dough width and set the correlation within the window width.
Met frame synchronizing method for detecting the maximum value of the signal, the correlation value of the received signal stored in the memory on a frame-by-frame basis according to the address given by the address circuit, the correlation values for one frame in the memory storage Every time
Search for the accumulated correlation value within the window width period
Then, the frame synchronization method is characterized by detecting a correlation value larger than a threshold value of a predetermined correlation value in the search result and determining a frame synchronization position from an address corresponding to the correlation value.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

Further, according to the present invention, digital wireless communication is provided.
Signal to detect the synchronization signal of the received signal,
And detects the maximum value of the correlation signal between the specified sync signal pattern
When setting the window width beforehand,
Synchronous circuit for detecting the maximum value of the correlation signal within a range
Therefore , the correlation signal contains the peak values of the direct wave and the delayed wave.
Based on the position of the peak value of the delayed wave,
Phase control circuit that sets the window width smaller than the dough width
Maximum of the correlation signal in a provided period of the smaller the window width
Constructing a synchronization circuit characterized by detecting a value
You can The frame synchronization method according to the present invention detects the synchronizing signal of a received signal in a digital radio communication
Of the correlation signal between the received signal and a predetermined synchronization signal pattern
When detecting the maximum value, set the window width in advance and
The maximum value of the correlation signal is detected within the window width
A Sulf frame synchronization method, the correlation value of the received signal stored in the memory on a frame-by-frame basis according to the address given by the address circuit, each time a correlation value for one frame in the memory is stored,
Search for the accumulated correlation value within the window width period
Then, a correlation value larger than a predetermined correlation value threshold value is detected from the search result, and the frame synchronization position is determined from the address corresponding to the correlation value.

Claims (3)

[Claims] 1. A frame synchronization circuit for detecting a synchronization signal of a received signal in digital wireless communication to establish frame synchronization, an address generation circuit for giving an address to a memory, and a correlation value between the received signal and a predetermined synchronization signal pattern. A memory for accumulating in frame units according to the address given by the address circuit, and each time a correlation value for one frame is accumulated in the memory,
A frame correlation peak detection circuit that detects a frame peak value showing the maximum value among the accumulated correlation values and determines an address corresponding to the frame peak value as a frame synchronization position, Frame synchronization circuit. 2. A frame synchronization circuit for detecting a synchronization signal of a received signal in digital wireless communication to establish frame synchronization, an address generation circuit for giving an address to a memory, and a correlation value between the received signal and a predetermined synchronization signal pattern. A memory for accumulating in frame units according to the address given by the address circuit, and each time a correlation value for one frame is accumulated in the memory,
A frame correlation peak detection circuit that detects a frame peak value indicating the maximum value among the accumulated correlation values and determines an address corresponding to the frame peak value as a frame synchronization position; A window having a detection range in the vicinity before and after the address is set as an address, the window peak value showing the maximum value among the correlation values in the window and the window peak address thereof are detected, and the window is detected over a predetermined number N of frames. The peak value is compared with the frame peak value, and when the number of frames with the window peak value larger than the frame peak value is equal to or more than a predetermined set number K, the window peak address is regarded as a synchronization state and the window peak address is determined as a frame synchronization position. If it is less than the set number K, it is determined to be out of synchronization. 1. A frame synchronization circuit, comprising: 3. A frame synchronization method for detecting a synchronization signal of a received signal in digital wireless communication to perform frame synchronization, wherein a correlation value between the received signal and a predetermined synchronization signal pattern is a frame according to an address given by the address circuit. Each time the correlation value for one frame is stored in the memory,
A frame synchronization method characterized by detecting a correlation value larger than a predetermined threshold value from the accumulated correlation values and determining a frame synchronization position from an address corresponding to the correlation value.