JP2003179350A - Method of manufacturing multilayer printed-wiring board and multilayer printed-wiring board - Google Patents

Method of manufacturing multilayer printed-wiring board and multilayer printed-wiring board

Info

Publication number
JP2003179350A
JP2003179350A JP2001379646A JP2001379646A JP2003179350A JP 2003179350 A JP2003179350 A JP 2003179350A JP 2001379646 A JP2001379646 A JP 2001379646A JP 2001379646 A JP2001379646 A JP 2001379646A JP 2003179350 A JP2003179350 A JP 2003179350A
Authority
JP
Japan
Prior art keywords
wiring board
multilayer printed
printed wiring
copper foil
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001379646A
Other languages
Japanese (ja)
Inventor
Hitoshi Kawaguchi
均 川口
Toyomasa Takahashi
高橋  豊誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2001379646A priority Critical patent/JP2003179350A/en
Publication of JP2003179350A publication Critical patent/JP2003179350A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer printed-wiring board which is of high density and high reliability by contributing to the miniaturization of a semiconductor package. <P>SOLUTION: In the method of manufacturing the multilayer printed-wiring board, a photosensitive resin coated on a copper foil is laminated on a printed- wiring board, and a circuit formation operation is repeated so as to be multilayered. In the method of manufacturing the multilayer printed-wiring board, circuits in respective layers are electrically bonded by bumps formed of a metal, positions corresponding to the metal bumps formed in a directly lower layer from among resin layers by the photosensitive resin coated on the copper foil are removed in advance, and the metal bumps and resin openings are aligned so as to be laminated. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体パッケージ
用途などに使われる高密度プリント多層配線板の製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high density printed multilayer wiring board used for semiconductor package applications and the like.

【0002】[0002]

【従来の技術】近年の電子機器の高機能化並びに軽薄短
小化の要求に伴い、電子部品の高密度集積化、さらには
高密度実装化が進んできている。これらの電子機器に使
用される半導体パッケージは、小型化かつ多ピン化して
きており、また、半導体パッケージを含めた電子部品を
実装する実装用基板も小型化してきている。さらには電
子機器への収納性を高めるため、リジット基板とフレキ
シブル基板を積層し一体化して、折り曲げを可能とした
リジットフレックス基板が、実装用基板として使われる
ようになってきている。
2. Description of the Related Art With the recent demand for higher functionality, lightness, thinness, shortness, and miniaturization of electronic equipment, high-density integration and further high-density packaging of electronic parts have been advanced. Semiconductor packages used in these electronic devices have been downsized and have a large number of pins, and mounting substrates for mounting electronic components including the semiconductor packages have also been downsized. Furthermore, in order to enhance the storage property in electronic equipment, a rigid flex substrate, which is made by stacking and integrating a rigid substrate and a flexible substrate and is bendable, has come to be used as a mounting substrate.

【0003】半導体パッケージはその小型化に伴って、
従来のようなリードフレームを使用した形態のパッケー
ジでは、小型化に限界がきているため、最近では回路基
板上にチップを実装したものとして、BGA(Ball
Grid Array)や、CSP(Chip Sc
ale Package)等のエリア実装型の新しいパ
ッケージ方式が提案されている。これらの半導体パッケ
ージにおいて、従来型半導体パッケージのリードフレー
ムの機能を有する半導体パッケージ用基板と呼ばれるプ
ラスチックやセラミックス等各種材料を使って構成され
るサブストレートの端子と、半導体チップの電極との電
気的接続方法として、ワイヤーボンディング方式やTA
B(Tape Automated Bonding)
方式、さらにはFC(Frip Chip)方式などが
知られている。最近では、半導体パッケージの小型化に
有利なFC接続方式を用いた、BGAやCSPの構造が
盛んに提案されている。これに伴い、半導体パッケージ
に用いられるサブストレートはより高密度化、高信頼性
が要求されている。
As semiconductor packages have become smaller,
In a package using a lead frame as in the past, miniaturization has reached its limit, so recently, a BGA (Ball) has been used as a chip mounted on a circuit board.
Grid Array) and CSP (Chip Sc)
A new package method of area mounting type, such as an all package) has been proposed. In these semiconductor packages, the electrical connection between the electrodes of the semiconductor chip and the terminals of the substrate, which is made of various materials such as plastics and ceramics, which is called a semiconductor package substrate, which has the function of the lead frame of the conventional semiconductor package. As a method, wire bonding method or TA
B (Tape Automated Bonding)
A system, further, an FC (Flip Chip) system and the like are known. Recently, BGA and CSP structures using an FC connection method, which is advantageous for miniaturization of semiconductor packages, have been actively proposed. Along with this, substrates used for semiconductor packages are required to have higher density and higher reliability.

【0004】[0004]

【発明が解決しようとする課題】半導体パッケージ用高
密度多層プリント配線板(サブストレート)製造に最も
多く用いられているレーザービルドアップ工法は、層間
接続をビアホール壁面メッキのみで接続しており、回路
密度が高くするためにビアホール径を小さくすると、著
しく信頼性が低下することが指摘されている。
The laser build-up method, which is most often used in the manufacture of high-density multilayer printed wiring boards (substrates) for semiconductor packages, uses interlayer plating only for via-hole wall plating to connect circuits. It has been pointed out that if the via hole diameter is reduced to increase the density, the reliability is significantly reduced.

【0005】また、導電ペーストやメッキ金属により形
成されたバンプ、又は厚みの厚い銅箔をエッチングする
ことにより形成されたバンプをプリント配線板上に設
け、その上に樹脂付銅箔もしくは銅箔とプリプレグを積
層加圧成型することにより、バンプが樹脂を突き抜け銅
箔に到達することにより層間接続をとる方法が提案され
ている。しかし、バンプ・銅箔間に樹脂が残存する可能
性があること、バンプ・銅箔接触面積の内、実際に両者
が金属結合している面積の割合はきわめて低いことか
ら、高密度化が進行した場合、十分な信頼性を得ること
が出来ないと指摘されている。
Further, bumps formed of conductive paste or plated metal, or bumps formed by etching a thick copper foil are provided on a printed wiring board, and a resin-coated copper foil or a copper foil is formed on the bump. A method has been proposed in which prepregs are laminated and pressure-molded to allow the bumps to penetrate through the resin and reach the copper foil to form interlayer connection. However, the resin may remain between the bump and the copper foil, and the ratio of the area where the two are actually metal-bonded is extremely low in the contact area between the bump and the copper foil. It has been pointed out that if you do, you will not be able to obtain sufficient reliability.

【0006】また、絶縁樹脂層に予め孔を空け、導電性
ペーストを埋め込んだものを銅箔とともにプリント配線
板上に積層加圧成型することにより上記導電ペーストを
介して層間接続をとる方法も提案されている。しかし、
バンプ・銅箔間の金属結合が、加圧成型される際の絶縁
樹脂層の厚み変化により導電性ペーストが圧縮され導電
性ペースト中に含まれる金属粉が局所的に金属接合を起
こしているだけであるため、十分な導通抵抗を得るため
には、バンプの細径化が出来ず、回路の高密度化への対
応が困難であることが指摘されている。
A method is also proposed in which a hole is preliminarily formed in an insulating resin layer and a conductive paste is embedded in the insulating resin layer, and a copper foil and a copper foil are laminated and pressure-molded on the printed wiring board to form an interlayer connection through the conductive paste. Has been done. But,
The metal bond between the bump and the copper foil is compressed by the thickness of the insulating resin layer during pressure molding, and the conductive paste is compressed and the metal powder contained in the conductive paste locally causes metal bonding. Therefore, it has been pointed out that it is difficult to reduce the diameter of the bump in order to obtain a sufficient conduction resistance, and it is difficult to cope with a high circuit density.

【0007】そこで発明者らは、種々検討の結果、上記
問題点を解決するために、層間接続のために金属性バン
プを用いるとともに、積層加圧成型時にバンプが樹脂を
貫通することなく最外層銅箔に到達し、且つ積層加圧成
型時に加えられる熱によりバンプと最外層銅箔が金属接
合することにより、回路の高密度化に対応でき、十分な
信頼性を有する半導体パッケージ用多層配線板の製造方
法を提供することを目指した。
As a result of various studies, the inventors have used metal bumps for interlayer connection in order to solve the above-mentioned problems, and the bumps do not penetrate the resin at the time of lamination pressure molding and the outermost layer is formed. A multilayer wiring board for a semiconductor package that reaches the copper foil and is capable of coping with high circuit density and having sufficient reliability because the bumps and the outermost copper foil are metal-bonded by the heat applied during the laminated pressure molding. Aiming to provide a manufacturing method of.

【0008】[0008]

【課題を解決するための手段】本発明は、(1)銅箔に
塗工された感光性樹脂をプリント配線板上に積層し、回
路形成を繰り返すことにより多層化を行うことを特徴と
する多層プリント配線板の製造方法、(2)各層の回路
が金属により形成されたバンプにより電気的に接合され
ている第(1)項記載の多層プリント配線板の製造方
法、(3)金属バンプがメッキ、エッチング、又は金線
ボンディングにより形成されている第(2)項記載の多
層プリント配線板の製造方法、(4)銅箔に塗工された
感光性樹脂の樹脂層のうち、直下層に形成された金属バ
ンプに対応する位置を予め除去し、金属バンプと樹脂開
口部の位置を合わせて積層される第(2)項又は第
(3)項記載の多層プリント配線板の製造方法、(5)
銅箔に塗工された感光性樹脂開口部底の銅箔表面が錫メ
ッキされ、金属バンプの少なくとも先端部が金メッキさ
れており、銅箔に塗工された感光性樹脂が積層成型され
る際の圧力と熱により、銅箔に塗工された感光性樹脂に
用いられている銅箔と金属バンプが固相拡散により金属
結合する第(4)項記載の多層プリント配線板の製造方
法、(6)銅箔に塗工された感光性樹脂を製造するため
に用いる感光性樹脂が、感光性成分及び熱硬化性成分を
含み、紫外線により所定の位置に所定のエネルギー量照
射されることにより所定の位置のみ現像液にて樹脂を除
去することが可能であり、かつその後加熱されることに
より、該熱硬化性成分が硬化する樹脂である第(1)〜
第(5)項いずれか記載の多層プリント配線板の製造方
法、(7)感光性樹脂が、紫外線の所定エネルギー量照
射後の時点で熱硬化性成分により直下層に対して接着性
を持ち、且つ加熱することにより流動性が発現する樹脂
である第(6)項記載の多層プリント配線板の製造方
法、(8)第(1)〜(7)項いずれか記載の多層プリ
ント配線板の製造方法で製造された多層プリント配線
板、である。
The present invention is characterized in that (1) a photosensitive resin coated on a copper foil is laminated on a printed wiring board, and circuit formation is repeated to form a multilayer structure. A method for manufacturing a multilayer printed wiring board; (2) a method for manufacturing a multilayer printed wiring board according to item (1), wherein the circuits of each layer are electrically joined by bumps formed of metal; The method for producing a multilayer printed wiring board according to item (2), which is formed by plating, etching, or gold wire bonding, and (4) a layer directly below the photosensitive resin layer coated on the copper foil. The method for producing a multilayer printed wiring board according to item (2) or (3), wherein the positions corresponding to the formed metal bumps are removed in advance, and the metal bumps and the resin openings are aligned and laminated. 5)
When the surface of the copper foil at the bottom of the photosensitive resin coating on the copper foil is tin-plated and at least the tip of the metal bump is gold-plated, the photosensitive resin coated on the copper foil is laminated and molded. The method for producing a multilayer printed wiring board according to the item (4), wherein the copper foil and the metal bump used in the photosensitive resin coated on the copper foil are metal-bonded by solid-phase diffusion by the pressure and heat of 6) The photosensitive resin used for producing the photosensitive resin coated on the copper foil contains a photosensitive component and a thermosetting component, and is irradiated with ultraviolet rays at a predetermined position to give a predetermined amount of energy, whereby a predetermined amount is obtained. It is possible to remove the resin with the developing solution only at the position of, and the thermosetting component is cured by heating after that.
(5) The method for producing a multilayer printed wiring board according to any one of (5), (7) the photosensitive resin has adhesiveness to the immediate underlying layer due to the thermosetting component after irradiation with a predetermined amount of ultraviolet energy, The method for producing a multilayer printed wiring board according to item (6), which is a resin that exhibits fluidity when heated, and (8) the production of a multilayer printed wiring board according to any one of items (1) to (7). A multilayer printed wiring board manufactured by the method.

【0009】[0009]

【発明の実施の形態】本発明で用いられる銅箔に塗工さ
れた感光性樹脂(Photosensitive Insulation resin wi
th Copper foil : 以後PICと呼称)は感光性成分、
熱硬化性成分、フィラー、硬化剤成分、溶剤を含むワニ
スを銅箔上に塗工し、乾燥することによって得られる。
次に上記樹脂成分は、所定の部位にUVによるエネルギ
ーを照射されることにより、現像液に対する溶解性にコ
ントラストが発現し、所定の部位の樹脂が除去される。
この場合の感光システムはネガ型、ポジ型のいかなるタ
イプでも適用可能であり、現像には有機溶剤もしくはア
ルカリ性水溶液が用いられるが、環境問題の観点からア
ルカリ性水溶液で現像されることが好ましい。
BEST MODE FOR CARRYING OUT THE INVENTION Photosensitive Insulation resin wi coated on the copper foil used in the present invention.
th Copper foil: hereinafter referred to as PIC) is a photosensitive component,
It is obtained by coating a varnish containing a thermosetting component, a filler, a curing agent component, and a solvent on a copper foil and drying it.
Next, the resin component is irradiated with UV energy at a predetermined portion, so that a contrast appears in solubility in a developing solution, and the resin at the predetermined portion is removed.
The photosensitive system in this case can be applied to any type of negative type and positive type, and an organic solvent or an alkaline aqueous solution is used for development, but it is preferable to develop with an alkaline aqueous solution from the viewpoint of environmental problems.

【0010】また、上記PICを積層加圧成型するベー
スとなるプリント配線板には、垂直接合を行いたい部位
に上記PIC樹脂層の厚みの100〜105%の高さと
なる金属製バンプが形成される。バンプの形成には、所
定の厚みの銅箔をエッチング除去して形成する方法、電
解メッキにより形成する方法、又は金線ボンディング手
法のいずれの方法も適用できる。エッチング法、メッキ
法においては少なくともバンプ先端部が金で被覆されて
いる必要があり、金線ボンディング法を適用する場合は
コイニングによりバンプ先端をつぶし平坦な面を形成す
る必要がある。またPICの樹脂除去部はこれらバンプ
の配置に対応する位置に形成されている。
Further, on the printed wiring board which is the base for laminating and press-molding the PIC, metal bumps having a height of 100 to 105% of the thickness of the PIC resin layer are formed at the portions to be vertically joined. It For forming the bumps, any of a method of etching and removing a copper foil having a predetermined thickness, a method of forming by electrolytic plating, and a gold wire bonding method can be applied. In the etching method and the plating method, at least the tip of the bump needs to be covered with gold, and when the gold wire bonding method is applied, it is necessary to crush the tip of the bump by coining to form a flat surface. The resin removal portion of the PIC is formed at a position corresponding to the arrangement of these bumps.

【0011】次に、PIC樹脂除去部はPIC樹脂層を
メッキマスクとして樹脂除去部底が電解錫メッキにより
被覆される。このため、PIC樹脂層は露光・現像が完
了した時点で、メッキ工程でメッキ液や前処理液に耐え
る必要があるのに加え、この後、バンプ付プリント配線
板が積層加圧成型されるため、メッキ工程時に加えられ
る種々の熱履歴の後でも、バンプ付プリント配線板に対
して十分な接着力が得られるだけの反応性を保持しなく
てはならない。
Next, in the PIC resin removing portion, the bottom of the resin removing portion is coated with electrolytic tin plating using the PIC resin layer as a plating mask. For this reason, the PIC resin layer must withstand the plating solution and the pretreatment solution in the plating process when the exposure and development are completed. In addition, the printed wiring board with bumps is then laminated and pressure-molded. Even after various heat history applied during the plating process, it is necessary to maintain reactivity enough to obtain sufficient adhesive force to the bumped printed wiring board.

【0012】さらに、樹脂除去部の底が錫メッキ処理さ
れたPICは、樹脂除去部がプリント配線板に設けられ
た垂直接続用金属製バンプの位置と合致するように配置
された後、バンプ付プリント配線板と1セットとされ、
平坦な金属板とともに真空プレスにより加圧成型され
る。この際、PIC樹脂層の熱硬化性成分を硬化させる
ため、加熱も同時に行われるが、この加熱により、樹脂
除去部底の錫とバンプ先端の金の固相拡散により金属結
合がバンプ先端全面に発現する。加えて、PIC樹脂除
去部はバンプの容積よりも大きく形成されるため、真空
プレスでの加圧成型時に加えられる熱により、流動しバ
ンプ周りに存在する空隙を充填する必要がある。
Further, the PIC having the bottom of the resin removing portion plated with tin is arranged with the bumps after the resin removing portion is arranged so as to match the position of the metal bump for vertical connection provided on the printed wiring board. One set with a printed wiring board,
It is pressure-molded by a vacuum press together with a flat metal plate. At this time, heating is performed at the same time to cure the thermosetting component of the PIC resin layer, but this heating causes solid-phase diffusion of tin at the bottom of the resin removal portion and gold at the tip of the bump to form a metal bond over the entire tip of the bump. Express. In addition, since the PIC resin removal portion is formed to have a larger volume than the bump, it is necessary to flow and fill voids existing around the bump with heat applied during pressure molding in a vacuum press.

【0013】このようにして得られた垂直接続用バンプ
を内臓するシールド板は、サブトラクティブ又はセミア
ディティブ法により必要な回路が形成され、さらに層を
重ねる場合は上記プロセスを繰り返すことにより多層化
が可能である。
The shield plate containing the vertical connection bumps thus obtained has a necessary circuit formed by the subtractive or semi-additive method. When more layers are stacked, the above process is repeated to form a multilayer structure. It is possible.

【0014】[0014]

【実施例】以下、実施例により本発明を具体的に説明す
るが、本発明はこれによって何ら限定されるものではな
い。
EXAMPLES The present invention will be described in detail below with reference to examples, but the present invention is not limited thereto.

【0015】《実施例1》18μm厚みの電解銅箔粗化
面に2官能メタクリレートモノマー14.5%、フェノ
ールノボラック樹脂25%、結晶性エポキシ樹脂30
%、球形シリカフィラー30%、光ラジカル発生剤0.
5%からなるネガ型感光性樹脂をメチルエチルケトン
(MEK)に溶解させたワニスをコンマコーターにより
流延塗布し、80℃で7分間乾燥させることにより樹脂
厚み75μmのPICを得た。
Example 1 On a roughened surface of an electrolytic copper foil having a thickness of 18 μm, 14.5% of a bifunctional methacrylate monomer, 25% of a phenol novolac resin, and 30 of a crystalline epoxy resin.
%, Spherical silica filler 30%, photoradical generator 0.
A varnish in which 5% of a negative photosensitive resin was dissolved in methyl ethyl ketone (MEK) was cast-coated by a comma coater and dried at 80 ° C. for 7 minutes to obtain a PIC having a resin thickness of 75 μm.

【0016】次に、上記PIC樹脂層の所定部位をマス
クした後、UV露光機により露光量200mJとなるよ
う露光し、2.38%水酸化テトラメチルアンモニウム
水溶液(TMAH)で現像し樹脂を除去した。さらに加
水硫酸水溶液により、樹脂除去部底の銅箔を厚さ1μm
除去したのち、上記銅箔を給電層として、樹脂除去部底
に厚さ0.5μmの錫層を電解メッキにより形成した。
Next, after masking a predetermined portion of the PIC resin layer, the PIC resin layer was exposed to a UV exposure of 200 mJ and developed with a 2.38% tetramethylammonium hydroxide aqueous solution (TMAH) to remove the resin. did. Furthermore, the copper foil on the bottom of the resin removal part is made to have a thickness of 1 μm
After the removal, a tin layer having a thickness of 0.5 μm was formed by electrolytic plating on the bottom of the resin-removed portion using the copper foil as a power supply layer.

【0017】次に、プリント配線板の垂直接続を行う部
位に直径90μm、高さ76μmで先端が2μm厚の金
に被覆された銅バンプを電解メッキにより形成した。こ
の銅バンプの位置は上記PIC樹脂除去部と鏡像関係に
ある。
Next, a copper bump having a diameter of 90 .mu.m, a height of 76 .mu.m and a tip of 2 .mu.m thick was covered with gold was formed by electrolytic plating on a portion of the printed wiring board to be vertically connected. The position of the copper bump is in a mirror image relationship with the PIC resin removal portion.

【0018】上記バンプ付プリント配線板を、バンプと
PIC樹脂除去部の位置が合致するよう、位置あわせを
行った後、平坦なSUS板ではさみ、真空プレスにより
積層加圧成型した。この際、最高製品温度は185℃に
達し、150℃以上の保持時間が45分であった。
The printed wiring board with bumps was aligned so that the bumps and the PIC resin removed portion were aligned with each other, then sandwiched between flat SUS plates and laminated and pressure-molded by a vacuum press. At this time, the maximum product temperature reached 185 ° C., and the holding time at 150 ° C. or higher was 45 minutes.

【0019】また、プリント配線板のもう一方の面に同
一の工程を繰り返して行うことにより、プリント配線板
の両面に垂直接続用金属製バンプを内蔵したシールド板
を得た。このシールド板を、加水硫酸により両面の銅箔
厚みが2μmになるまでエッチングした後、セミアディ
ティブ法によりしかるべき回路を形成した後、ソルダー
レジスト層をその両面に形成した。
By repeating the same steps on the other surface of the printed wiring board, a shield plate having metal bumps for vertical connection built in on both surfaces of the printed wiring board was obtained. The shield plate was etched with sulfuric acid until the thickness of the copper foil on both surfaces became 2 μm, and then an appropriate circuit was formed by the semi-additive method, and then a solder resist layer was formed on both surfaces.

【0020】このようにして得られた多層プリント配線
板に、半導体素子をダイアタッチフィルムによりマウン
トし、金線ボンディングによりプリント配線板と半導体
素子とを接合した後、モールド封止材により封止し半導
体パッケージとした。この半導体パッケージの信頼性試
験を行ったが、半導体パッケージとしての動作に支障は
見られなかった。
A semiconductor element is mounted on the thus obtained multilayer printed wiring board by a die attach film, the printed wiring board and the semiconductor element are joined by gold wire bonding, and then sealed by a mold sealing material. It is a semiconductor package. A reliability test was conducted on this semiconductor package, but no problem was found in its operation as a semiconductor package.

【0021】[0021]

【発明の効果】本発明によれば、半導体パッケージ用の
高密度多層プリント配線板の配線密度をさらに向上させ
ことが可能となり、半導体パッケージの小型化に貢献で
きる。
According to the present invention, it is possible to further improve the wiring density of the high-density multilayer printed wiring board for a semiconductor package, which contributes to downsizing of the semiconductor package.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/40 H01L 23/12 N Fターム(参考) 5E317 AA24 BB02 BB11 BB12 BB13 CC25 CC31 CD25 CD27 GG14 5E346 AA15 AA43 CC09 CC32 CC33 CC38 DD03 DD12 EE33 EE38 FF07 FF08 FF09 FF12 FF24 GG15 GG17 GG22 HH22 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 3/40 H01L 23/12 NF term (reference) 5E317 AA24 BB02 BB11 BB12 BB13 CC25 CC31 CD25 CD27 GG14 5E346 AA15 AA43 CC09 CC32 CC33 CC38 DD03 DD12 EE33 EE38 FF07 FF08 FF09 FF12 FF24 GG15 GG17 GG22 HH22

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 銅箔に塗工された感光性樹脂をプリント
配線板上に積層し、回路形成を繰り返すことにより多層
化を行うことを特徴とする多層プリント配線板の製造方
法。
1. A method for producing a multilayer printed wiring board, comprising: stacking a photosensitive resin coated on a copper foil on a printed wiring board and repeating circuit formation to form a multilayer.
【請求項2】 各層の回路が金属により形成されたバン
プにより電気的に接合されている請求項1記載の多層プ
リント配線板の製造方法。
2. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the circuits of the respective layers are electrically joined by bumps made of metal.
【請求項3】 金属バンプがメッキ、エッチング、又は
金線ボンディングにより形成されている請求項2記載の
多層プリント配線板の製造方法。
3. The method for manufacturing a multilayer printed wiring board according to claim 2, wherein the metal bumps are formed by plating, etching, or gold wire bonding.
【請求項4】 銅箔に塗工された感光性樹脂の樹脂層の
うち、直下層に形成された金属バンプに対応する位置を
予め除去し、金属バンプと樹脂開口部の位置を合わせて
積層される請求項2又は3記載の多層プリント配線板の
製造方法。
4. A photosensitive resin layer coated on a copper foil is preliminarily removed at a position corresponding to a metal bump formed directly under the resin layer, and the metal bump and the resin opening are aligned and laminated. The method for manufacturing a multilayer printed wiring board according to claim 2 or 3.
【請求項5】 銅箔に塗工された感光性樹脂開口部底の
銅箔表面が錫メッキされ、金属バンプの少なくとも先端
部が金メッキされており、銅箔に塗工された感光性樹脂
が積層成型される際の圧力と熱により、銅箔に塗工され
た感光性樹脂に用いられている銅箔と金属バンプが固相
拡散により金属結合する請求項4記載の多層プリント配
線板の製造方法
5. A photosensitive resin coated on a copper foil, wherein the copper foil surface at the bottom of the opening of the photosensitive resin is tin-plated and at least the tip of the metal bump is gold-plated. The multilayer printed wiring board according to claim 4, wherein the copper foil used in the photosensitive resin coated on the copper foil and the metal bump are metal-bonded by solid-phase diffusion due to pressure and heat during lamination molding. Method
【請求項6】 銅箔に塗工された感光性樹脂を製造する
ために用いる感光性樹脂が、感光性成分及び熱硬化性成
分を含み、紫外線により所定の位置に所定のエネルギー
量照射されることにより所定の位置のみ現像液にて樹脂
を除去することが可能であり、かつその後加熱されるこ
とにより、該熱硬化性成分が硬化する樹脂である請求項
1〜5いずれか記載の多層プリント配線板の製造方法。
6. A photosensitive resin used for producing a photosensitive resin coated on a copper foil contains a photosensitive component and a thermosetting component, and is irradiated with ultraviolet rays at a predetermined energy amount at a predetermined position. 6. The multilayer print according to any one of claims 1 to 5, wherein the resin can be removed with a developing solution only at a predetermined position, and the thermosetting component is cured by heating thereafter. Wiring board manufacturing method.
【請求項7】 感光性樹脂が、紫外線の所定エネルギー
量照射後の時点で熱硬化性成分により直下層に対して接
着性を持ち、且つ加熱することにより流動性が発現する
樹脂である請求項6記載の多層プリント配線板の製造方
法。
7. The photosensitive resin is a resin which has adhesiveness to a layer directly below it by a thermosetting component after being irradiated with a predetermined amount of ultraviolet rays and has fluidity when heated. 7. The method for manufacturing a multilayer printed wiring board according to 6.
【請求項8】 請求項1〜7いずれか記載の多層プリン
ト配線板の製造方法で製造された多層プリント配線板。
8. A multilayer printed wiring board manufactured by the method for manufacturing a multilayer printed wiring board according to claim 1.
JP2001379646A 2001-12-13 2001-12-13 Method of manufacturing multilayer printed-wiring board and multilayer printed-wiring board Pending JP2003179350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001379646A JP2003179350A (en) 2001-12-13 2001-12-13 Method of manufacturing multilayer printed-wiring board and multilayer printed-wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001379646A JP2003179350A (en) 2001-12-13 2001-12-13 Method of manufacturing multilayer printed-wiring board and multilayer printed-wiring board

Publications (1)

Publication Number Publication Date
JP2003179350A true JP2003179350A (en) 2003-06-27

Family

ID=19186915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001379646A Pending JP2003179350A (en) 2001-12-13 2001-12-13 Method of manufacturing multilayer printed-wiring board and multilayer printed-wiring board

Country Status (1)

Country Link
JP (1) JP2003179350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353660A (en) * 2004-06-08 2005-12-22 Shinko Seisakusho:Kk Multilayer printed circuit board and its manufacturing method
JP2008210885A (en) * 2007-02-23 2008-09-11 Hitachi Cable Ltd Multilayer printed wiring board and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353660A (en) * 2004-06-08 2005-12-22 Shinko Seisakusho:Kk Multilayer printed circuit board and its manufacturing method
JP2008210885A (en) * 2007-02-23 2008-09-11 Hitachi Cable Ltd Multilayer printed wiring board and method for manufacturing the same

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