JP2003179079A - Field effect semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a baking residue due to a double exposure from occurring at the junction between a T-gate electrode and a gate pad. <P>SOLUTION: The field effect transistor comprises a T-gate electrode 20 first formed by a 2-layer resist process using a resistor film for an electron beam and a photoresist film, and a gate pad 22 formed by using a resist pattern formed newly after the gate electrode 20 is formed. In this, the pad 22 has a gate pad connector 22a to be partly superposed on the end of the gate electrode 20. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device and a method of manufacturing the same, and more particularly to a gate pad portion of a T-type gate electrode.

[0002]

2. Description of the Related Art A field effect transistor using a compound semiconductor, such as HEMT (High Electron Mobility Tra)
nistors) have been developed as transistors suitable for high-speed or high-frequency operation, have been improved in performance as low-noise amplifier elements, and have been developed as high-power amplifier elements. In order to increase the output of the field effect transistor, it is necessary to increase the maximum drain current,
Therefore, it is necessary to increase the total gate width.
As a structure for increasing the total gate width, a structure generally called a multi-finger in which a plurality of unit FETs are connected in parallel is adopted. This is a structure in which a source electrode and a drain electrode are shared for size reduction, and each gate electrode called a gate finger is connected to a gate pad portion.

Further, in the field effect transistor, if the gate length is shortened, the performance of the transistor can be improved.
When the gate length is shortened, the gate cross-sectional area is reduced, which causes the gate resistance to increase. To compensate for this increase in gate resistance, a T-shaped gate electrode having a T-shaped cross section is adopted.
To form the T-shaped gate electrode, the T-shaped gate electrode is formed by an electron beam exposure method and a two-layer resist process using a lower layer resist and an upper layer resist, and a gate pad portion is also formed in the same step. In the two-layer resist process, the upper-layer resist pattern formed by the upper-layer resist film is a resist pattern in which the strip-shaped region corresponding to the head of the T-shaped cross section of the T-shaped gate electrode and the region corresponding to the gate pad portion are removed. The formation of this upper layer resist pattern is performed by using the exposure by the reduction projection exposure apparatus.

On the other hand, the lower layer resist pattern formed by the lower layer resist film is a resist pattern obtained by removing the band-shaped region corresponding to the leg portion of the T-shaped cross section of the T-shaped gate electrode and the region corresponding to the gate pad portion. When forming this lower layer resist pattern, the band-shaped region corresponding to the leg portion of the T-shaped cross section of the T-shaped gate electrode is exposed by the electron beam exposure apparatus because the gate length is about 0.2 μm, but the gate pad portion is exposed. The electron beam 12 by the electron beam exposure apparatus
When the exposure is performed by irradiation of No. 8, the aperture of the electron beam is small and it takes a dozen hours to draw each gate pad portion, so the throughput is extremely poor. Therefore, the gate pad portion is exposed by a contact aligner or the like to form the pattern. Forming is a normal forming method.

[0005]

FIG. 15 is a partial plan view of a conventional field effect transistor (hereinafter referred to as FET). 16 is a partial cross-sectional view of the FET in the XVI-XVI cross section of FIG. 15, and FIG. 17 is the XVII-X of FIG.
FIG. 18 is a partial cross-sectional view of the FET in the VII cross section.
5 is a partial cross-sectional view of the FET in the XVIII-XVIII cross section of FIG. In the drawings, the same reference numerals represent the same or corresponding parts. This also applies to the following drawings.

In FIGS. 15, 16, 17, and 18, 100 is a FET, 102 is a GaAs substrate, and 104.
Is an active layer formed by an epitaxial growth method or the like, 1
An active region 04a is a part of the active layer 104. 1
Reference numeral 06 is an element isolation layer, 108 is a recess groove, 110 is a gate electrode, 110a is a head portion of the gate electrode 110, 110b is a leg portion of the gate electrode 110, 112 is a gate pad, 11
2a is a gate pad connecting portion, 114 is a source electrode, 11
6 is a drain electrode.

Next, a conventional FET manufacturing method, particularly a method of forming a T-type gate electrode and a gate pad will be described. FIG. 19, FIG. 20, FIG. 21, and FIG.
A partial cross-sectional view of the FET in one step of the method for manufacturing the ET,
23 is a partial cross-sectional view of the FET in the XXIII-XXIII cross section of FIG. 22, and FIG. 24 is XXIV-XX of FIG.
It is a partial cross-sectional view of the FET in the IV cross section. First, G
An active layer 104 is formed on the aAs substrate 102 by an epitaxial growth method or the like, and then an element isolation layer 106 is formed by implanting hydrogen or the like, and a source electrode 114 and a source electrode 114 are formed on the surface of the active layer 104 by a photolithography technique and a metal film forming technique. The drain electrode 116 is formed.

Referring to FIG. 19, next, the GaAs substrate 10 will be described.
A resist film 118 for electron beam and a photoresist film 120 are sequentially formed on the gate electrode 2, and the cross section T of the gate electrode 110 is
Band-shaped region corresponding to the head portion 110a of the character and the gate pad 1
12 using a reduction projection exposure apparatus (not shown) using a photomask 122 for a photoresist film 120 in which a shielding film 122a that shields a region corresponding to 12 is formed on a glass substrate 122b. The photoresist film 120 is exposed with 124.

Referring to FIG. 20, next, the photoresist film 1 is formed.
20 is developed to remove an unexposed region of the photoresist film 120, and a first resist pattern 126 having a band-shaped region corresponding to the head 110a of the T-shaped cross section of the gate electrode 110 and an opening 126a corresponding to the gate pad 112. To form. Further, the opening 126 of the first resist pattern 126.
In the electron beam resist film 118 exposed in a,
An electron beam 128 is applied to a strip-shaped region of the T-shaped gate electrode 110 corresponding to the leg portion 110b having a T-shaped cross section. The irradiation area of the electron beam 128 is irradiated a little longer so as to overlap with the next exposure area in consideration of the overlapping margin with the photomask for forming the exposure area of the next step.

Referring to FIG. 21, next, a portion of the exposed surface of the electron beam resist film 118 corresponding to the head portion 110a of the T-type gate electrode 110 including the irradiation region of the electron beam 128 is changed to a gate pad connecting portion. The gate pad 112 including a region (gate pad connecting portion 112a) that is shielded except for 112a and slightly overlaps with the irradiation region of the electron beam 128.
Using a contact mask (not shown) using a photomask 122 in which a shielding film 130b having an opening 130a corresponding to is formed on a glass substrate 130c.
The exposed electron beam resist film 118 is exposed with a broadband exposure light 132 having a wavelength in a region such as h or i line.

22, 23, and 24, the electron beam resist film 118 exposed next is developed to irradiate the electron beam 128 irradiation region and the broadband exposure light 132. Remove the area, T
A second resist pattern 134 having an opening 134a corresponding to the leg portion 110b of the mold gate electrode 110 and the gate pad 112 is formed, and wet etching is performed using the second resist pattern 134 as a mask to form the active layer 104.
Recesses 108 in the active region 104a, which is a part of the surface of the
And the recessed groove 136 of the gate pad 112 is formed. Further, the gate electrode 11 is formed on the entire surface of the GaAs substrate 102.
After depositing a metal for 0, the gate electrode 110 shown in FIGS.
And the gate pad 112 is formed.

The conventional gate electrode 110 and gate pad 112 are formed by the manufacturing method as described above.
In this manufacturing method, the exposure of the strip-shaped region corresponding to the leg 110b having the T-shaped cross section of the gate electrode 110 is performed by the electron beam 128.
The exposure of the gate pad 112 is performed by the broadband exposure light 132. Therefore, in consideration of the overlapping margin with the photomask 134 when the gate pad 112 is exposed, the irradiation region of the electron beam 128 is set to be slightly longer than the exposure region when the gate pad 112 is exposed. It

Therefore, the electron beam resist film 118 in the connection portion 112a between the gate electrode 110 and the gate pad 112 is double-exposed with the electron beam 128 and the broadband exposure light 132. Further, the photons having wavelengths in the g, h, and i lines of the current contact aligner have poor sensitivity to the electron beam resist and require exposure time of more than ten minutes per sheet.

Therefore, in some cases, the electron beam resist film 118 at this connection portion may be burned. When the resist film 118 for electron beam is burned, it can be removed by using an asher, but when the asher is used, it is heated at a high temperature, so that the gate electrode may be deformed and deviated from a desired gate width. In addition, there are cases in which predetermined electrical characteristics cannot be expected, and variations occur in the electrical characteristics. Further, if the baked resist is left as it is, it has an adverse effect on the subsequent process and also has an adverse effect on the electrical characteristics of the resulting FET, resulting in a low yield. Further, there is a problem that the reliability of the FET is lowered.

The present invention has been made to solve the above problems, and a first object thereof is to provide a field effect semiconductor device having a high yield and a high reliability, and a second object thereof. An object of the present invention is to provide a manufacturing method capable of manufacturing a field-effect semiconductor device having a high yield and a high reliability in a simple process. As a known document, Japanese Patent Laid-Open No.
There is a publication of -186189. This publication relates to a method of forming a bonding pad of a gate electrode, and in order to eliminate a conduction failure between the first layer electrode pattern and the second layer electrode pattern, the first layer electrode pattern is formed of a Ti / Al layer, It is disclosed that a Ti / Au layer is provided on the surface of the first layer electrode pattern.

[0016]

A field effect semiconductor device according to the present invention has an active region provided on a surface of an active layer provided on a semiconductor substrate and having an active region provided on a part of the active layer. A source electrode and a drain electrode arranged side by side with each other, a gate electrode having a T-shaped cross section disposed on the active region and interposed between the source electrode and the drain electrode, and a part of the gate electrode And a gate extraction electrode portion disposed on the active layer surface while covering the end surface,
In the connection area between the end of the gate electrode and the gate extraction electrode,
There are no resist burn-in residues, and electrical characteristics can be stabilized.

Further, since the recess groove is provided on the surface of the active region and the gate electrode is provided in the recess groove, the T-type gate electrode resistance can be reduced. Also, the breakdown voltage can be increased.

Further, a plurality of gate electrodes are juxtaposed via a source electrode or a drain electrode and each is connected to a gate lead electrode portion. When the gate electrodes have a multi-finger structure, each gate electrode is In the connection area between the end of and the gate extraction electrode,
There are no resist burn-in residues, and electrical characteristics can be stabilized.

Further, the active layer is formed of a compound semiconductor, and in the field effect type semiconductor device of the compound semiconductor, there is no resist burn-in residue in the connection region between the end of the gate electrode and the gate extraction electrode, and the electric field is reduced. The physical characteristics can be stabilized.

In the method of manufacturing a field effect semiconductor device according to the present invention, the first step of sequentially forming the first resist film and the second resist film on the surface of the active layer formed on the semiconductor substrate. And exposing the first resist film using a photomask having a strip-shaped shielding film corresponding to the head of the T-shaped section of the gate electrode having a T-shaped section, and exposing the first opening corresponding to the strip-shaped shielding film. Corresponding to a second step of forming a first resist pattern having a portion and a leg portion having a T-shaped cross section of the gate electrode of the second resist film exposed by the first opening portion of the first resist pattern. A third step of exposing a strip-shaped region narrower than the first opening with an electron beam to form a second resist pattern having a second opening in the exposure region; Using the resist pattern of And a fourth step of forming a gate electrode by lift-off, and a fifth step of removing the first and second resist patterns and forming a third resist film on the active layer to cover the gate electrode. Exposing the third resist film using a photomask having a shielding film that partially covers the end of the gate electrode and partially covers the active layer, and has a third opening corresponding to the shielding film. And a seventh step of forming a gate lead electrode portion by covering the metal film with the third resist pattern as a mask and lifting off the gate lead electrode portion. When forming the electrode portion, double exposure of the resist film at the connecting portion between the gate electrode and the gate lead electrode portion can be eliminated, and the resist film can be prevented from being burned.

Further, in the fourth step, the recess groove is formed by using the second resist pattern as a mask, and then the metal film is covered by using the first and second resist patterns as a mask, which has a low gate resistance and a high breakdown voltage. A high T-shaped gate electrode can be formed.

Further, the photomask of the second step has a plurality of strip-shaped shielding films corresponding to the head of the gate electrode having a T-shaped cross section, and the photomask of the sixth step has each end of the gate electrode. When a gate electrode has a multi-finger structure and has a shielding film that partially covers the gate electrode and a part of the active layer, when forming the gate extraction electrode portion, each gate electrode and the gate extraction electrode portion are formed. Double exposure of the resist film at the connection part can be eliminated, and the resist film can be prevented from burning.

Further, the active layer formed on the substrate is a compound semiconductor, and in forming the gate extraction electrode portion of the field effect semiconductor device of the compound semiconductor, in the connection portion between the gate electrode and the gate extraction electrode portion. 2 of resist film
Double exposure can be eliminated, and image sticking of the resist film can be prevented.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. FIG. 1 is a partial plan view of a field effect semiconductor device according to one embodiment of the present invention. 2 is a partial cross-sectional view of the field effect semiconductor device taken along the line II-II in FIG. 1, and FIG.
FIG. 4 is a partial cross-sectional view of the field-effect semiconductor device in the −III cross section, and FIG. 4 is a partial cross-sectional view of the field-effect semiconductor device in the IV-IV cross section of FIG. 1.

In FIGS. 1, 2, 3, and 4, 1
Reference numeral 0 is an FET, which has a multi-finger structure in which a plurality of unit FETs 10a are connected in parallel. In this multi-finger structure, a source electrode and a drain electrode are commonly used for size reduction, and each gate electrode called a gate finger is connected to a gate pad portion. Reference numeral 12 is a GaAs substrate, 14 is an active layer formed on the GaAs substrate 12 by an epitaxial growth method, and 14a is an active region which is a part of the active layer 14. 16 is an element isolation layer, which is an active layer 14
An insulating region is formed by injecting hydrogen or the like into and surrounding the element region. Reference numeral 18 is a recess groove formed in a part of the surface of the active region 14a.

Reference numeral 20 denotes a gate electrode, which is made of, for example, an Al-based metal. The gate electrode 20 has a T-shaped cross section, and is disposed on the surface of the recess groove 18 formed in a part of the surface of the active region 14a. Recess groove 18
By disposing the gate electrode 20 on the gate electrode, the resistance of the gate electrode can be reduced. Further, by forming the recessed groove 18, the electric field can be concentrated and the gate electrode 20 can be formed.
I-V characteristics are markedly improved. That is, the breakdown voltage can be increased. Reference numeral 20a denotes a T-shaped section head of the gate electrode 20, and 20b denotes a T-shaped section leg of the gate electrode 20.
The width of the leg portion 20b becomes the gate length, and the gate length is 0.
It is about 2 μm. Reference numeral 22 denotes a gate pad as a gate lead electrode portion, which is made of, for example, an Al-based metal and extends in the direction in which the unit FETs 10a are arranged in parallel with each other.
0 is the gate pad 2 via the gate pad connecting portion 22a
Connected to 2. The gate pad connecting portion 22a is arranged so as to partially overlap the end surface of each gate electrode 20. In FIG. 1, the gate pad connecting portion 22a is drawn to project from the gate pad 22, but if each gate electrode 20 and the gate pad 22 are arranged so as to partially overlap each other,
It is not always necessary to form the gate pad connecting portion 22a so as to project.

Reference numeral 24 is a source electrode, and 26 is a drain electrode, which are juxtaposed with the active region 14a interposed therebetween. In order to reduce the size of the device, the source electrode 24 and the drain electrode 26 are shared by the gate electrodes 20 arranged so as to sandwich the source electrode 24 and the drain electrode 26, respectively.

Next, a method of manufacturing an FET, particularly a method of forming a T-type gate electrode and a gate pad will be described. Figure 5,
6, FIG. 8, FIG. 10, FIG. 12, and FIG. 13 are partial cross-sectional views of the field-effect semiconductor device in one step of the method of manufacturing a field-effect semiconductor device according to one embodiment of the present invention. 7 is a partial cross-sectional view of the field effect semiconductor device in the VII-VII cross section of FIG. 6, FIG. 9 is a partial cross sectional view of the field effect semiconductor device in the IX-IX cross section of FIG. 8,
13 is a partial cross-sectional view of the field effect semiconductor device taken along the line XI-XI in FIG. 10, and FIG. 14 is a cross-sectional view taken along the line XIV-XI in FIG.
It is a partial cross-sectional view of the field effect semiconductor device in the V cross section.

First, the active layer 14 is formed on the GaAs substrate 12 by the epitaxial growth method or the like, and then the element isolation layer 16 is formed by injecting hydrogen or the like, and the active layer 14 is formed on the surface of the active layer 14 by the photolithography technique and the metal film forming technique. The source electrode 24 and the drain electrode 26 are formed. Referring to FIG. 5, an electron beam resist film 30 as a first resist film is then formed on the GaAs substrate 12 at a thickness of 1000 to 1000.
The film thickness is 2000 angstroms, and the photoresist film 32 as the second resist film is sequentially formed on the electron beam resist film 30 to have a film thickness of 5000 to 20000 angstroms. An image reversal resist or a negative photoresist is used for the photoresist film 32.

Next, the head 2 having a T-shaped cross section of the gate electrode 20.
Photomask 34 in which a shielding film 34a made of Cr that shields a strip-shaped region corresponding to 0a is formed on a glass substrate 34b.
Using a reduction projection exposure apparatus (not shown), the photoresist film 32 is exposed to light of a single wavelength, for example, i-line exposure light 36. Referring to FIGS. 6 and 7, next, the photoresist film 32 is developed, the unexposed region of the photoresist film 32 is removed, and a strip-shaped opening 38a corresponding to the head 20a having a T-shaped cross section of the gate electrode 20 is formed. A first resist pattern 38 having is formed. VI as shown in FIG.
The cross-sectional shape of the first resist pattern 38 in the I-VII cross section corresponds to the T-shaped head 20 a of the gate electrode 20. Further, the first resist pattern 3
Electron beam resist film 30 exposed through the opening 38a of FIG.
In, the leg portion 20b having a T-shaped cross section of the T-type gate electrode 20
The electron beam 40 is applied to the strip-shaped region corresponding to.

Referring to FIGS. 8 and 9, the exposed electron beam resist film 30 is developed to remove the irradiation region of the electron beam 40, and the leg of the T-shaped gate electrode 20 is removed. A second resist pattern 42 having an opening 42a corresponding to the strip-shaped region of the portion 20b is formed, wet etching is performed using the second resist pattern 42 as a mask, and a recess groove is formed in the active region 14a which is a part of the surface of the active layer 14. 18 is formed. IX-I as shown in FIG.
The sectional shape of the second resist pattern 42 in the X section corresponds to the T-shaped leg portion 20b of the gate electrode 20. Further, an Al-based metal for the gate electrode 20 is deposited on the entire surface of the GaAs substrate 12.

Referring to FIGS. 10 and 11, active region 1 is formed by lift-off after depositing an Al-based metal.
4a on the surface of the recess groove 18 provided in the gate electrode 2
0 is formed. Referring to FIG. 12, next, the gate electrode 2
A photoresist film 44 as a third resist film is formed on the entire surface of the GaAs substrate 12 so as to cover 0. As the photoresist film 44, an image reversal resist or a negative type photoresist is used. Next, the Cr shielding film 46 that shields the region of the gate pad 22 including the gate pad connecting portion 22a that partially overlaps the end portion of the gate electrode 20.
The photoresist film 46 is exposed to light of a single wavelength, for example, i-line exposure light 36, using a reduction projection exposure apparatus (not shown) using the photomask 46 having a formed on the glass substrate 46b.

Referring to FIGS. 13 and 14, the photoresist film 44 is then developed to remove the unexposed region of the photoresist film 44 and a third resist having an opening 48a corresponding to the region of the gate pad 22. A pattern 48 is formed. As shown in FIG. 13, the opening 48a exposes the end of the gate electrode 20 overlapping the gate pad connecting portion 22a. Further, as shown in FIG. 14, the cross-sectional shape of the third resist pattern 48 in the XIV-XIV cross section has a shape corresponding to the gate pad connecting portion 22a. After depositing Al-based metal on the entire surface of the GaAs substrate 12,
By lift-off, the gate pad 22 having the gate pad connecting portion 22a is formed, and the FET 10 shown in FIGS. 1, 2, 3, and 4 is formed.

The FET 10 formed by the above steps
Then, metal is vapor-deposited through a resist pattern formed by a two-layer resist process using an electron beam resist film and a photoresist film, and lift-off is performed to form a T-shaped gate electrode, and then a new resist film is formed. Forming a resist pattern having an opening corresponding to a region of the gate pad having a gate pad connecting portion partially overlapping the end of the T-shaped gate electrode, and depositing an Al-based metal through the resist pattern to form a gate pad Is formed. Therefore, in this manufacturing method, the step of performing double exposure of the resist film is eliminated.

Therefore, in the method of manufacturing the field effect semiconductor device having the T-type gate and the gate pad, by adopting the above-described simple process, the resist film is prevented from being burned and the electric characteristics are dispersed. It is possible to manufacture a field effect type semiconductor device with less power consumption. Further, since no seizure residue is generated, it is possible to prevent the reliability of the field effect semiconductor device from lowering. Furthermore, a step of removing the burn-in residue of the resist film, for example, an asher step is not required, and the yield reduction of the FET due to the variation of the gate length due to thermal deformation can be eliminated. By the way, T
A field-effect semiconductor device including a gate and a gate pad can have a high yield and high reliability, and according to this manufacturing method, a highly reliable semiconductor device can be provided at low cost. .

In the description of this embodiment, the FET is generally described, but the HEMT or MESFE is used.
Not only can it be applied to an element using a T-type gate electrode, such as a T (MEtal Semiconductor Field Effect Transistor), but an IC or MMIC (M
It goes without saying that the same effects can be obtained by applying to semiconductor devices such as onolithic Microwave ICs) and modules, and manufacturing methods thereof.

[0037]

The field effect semiconductor device and the method of manufacturing the same according to the present invention have the following effects because they have the above-described configurations and steps. In the field effect semiconductor device according to the present invention, source electrodes are provided on a surface of an active layer provided on a semiconductor substrate and are juxtaposed to each other via an active region provided in a part of the active layer. And a drain electrode, a gate electrode having a T-shaped cross section disposed on the active region and interposed between the source electrode and the drain electrode, and a part thereof covers an end surface of the gate electrode and an active layer. With a gate extraction electrode portion disposed on the surface, there is no resist burning residue in the connection region between the end of the gate electrode and the gate extraction electrode portion,
The electrical characteristics of the field effect semiconductor device can be stabilized. As a result, the field-effect semiconductor device having the T-type gate and the gate pad can have a high yield and high reliability.

Further, since the recess groove is provided on the surface of the active region and the gate electrode is provided in the recess groove, the resistance of the T-type gate electrode can be reduced. Also, the breakdown voltage can be increased. As a result, a field effect semiconductor device having good electric characteristics can be formed.

Further, a plurality of gate electrodes are juxtaposed via a source electrode or a drain electrode and each is connected to a gate lead electrode portion. When the gate electrodes have a multi-finger structure, each gate electrode is In the connection region between the end portion of the electrode and the gate extraction electrode portion, there is no resist burn-in residue, the electrical characteristics can be stabilized, and the characteristics of the unit FET can be made uniform. By the way, T with multi-finger configuration
A field effect semiconductor device including a mold gate and a gate pad can have a high yield and high reliability.

Further, the active layer is formed of a compound semiconductor, and in the field effect type semiconductor device of the compound semiconductor, there is no resist burn-in residue in the connection region between the end of the gate electrode and the gate extraction electrode, and the The physical characteristics can be stabilized. As a result, a compound semiconductor field effect semiconductor device having a T-type gate and a gate pad can be configured to have a high yield and high reliability.

In the method of manufacturing a field effect semiconductor device according to the present invention, the first step of sequentially forming the first resist film and the second resist film on the surface of the active layer formed on the semiconductor substrate. And exposing the first resist film using a photomask having a strip-shaped shielding film corresponding to the head of the T-shaped section of the gate electrode having a T-shaped section, and exposing the first opening corresponding to the strip-shaped shielding film. Corresponding to a second step of forming a first resist pattern having a portion and a leg portion having a T-shaped cross section of the gate electrode of the second resist film exposed by the first opening portion of the first resist pattern. A third step of exposing a strip-shaped region narrower than the first opening with an electron beam to form a second resist pattern having a second opening in the exposure region; Using the resist pattern of And a fourth step of forming a gate electrode by lift-off, and a fifth step of removing the first and second resist patterns and forming a third resist film on the active layer to cover the gate electrode. Exposing the third resist film using a photomask having a shielding film that partially covers the end of the gate electrode and partially covers the active layer, and has a third opening corresponding to the shielding film. And a seventh step of forming a gate lead electrode portion by covering the metal film with the third resist pattern as a mask and lifting off the gate lead electrode portion. When forming the electrode portion, double exposure of the resist film at the connecting portion between the gate electrode and the gate lead electrode portion can be eliminated, and the resist film can be prevented from being burned. Therefore, it is possible to manufacture a field effect semiconductor device with less variation in electrical characteristics. Further, since no seizure residue is generated, it is possible to prevent the reliability of the field effect semiconductor device from lowering. Furthermore, a step of removing the burn-in residue of the resist film, for example, an asher step is not required, and the yield reduction of the FET due to the variation of the gate length due to thermal deformation can be eliminated. As a result, it is possible to inexpensively provide a field effect semiconductor device including a highly reliable T-type gate and a gate pad.

Further, in the fourth step, the recess groove is formed by using the second resist pattern as a mask, and then the metal film is covered by using the first and second resist patterns as a mask, which has a low gate resistance and a high breakdown voltage. A T-type gate electrode can be formed. As a result, a field effect semiconductor device having good electric characteristics can be formed by a simple process.

Further, the photomask of the second step has a plurality of band-shaped shielding films corresponding to the head of the gate electrode having a T-shaped cross section, and the photomask of the sixth step has each end of the gate electrode. In a field effect semiconductor device having a multi-fingered gate electrode, which has a shielding film that partially covers the gate electrode and a part of the active layer, each gate electrode is formed when the gate extraction electrode portion is formed. It is possible to eliminate double exposure of the resist film at the connection portion between the gate lead electrode portion and the gate lead electrode portion, and prevent the resist film from being burned. Therefore, it is possible to manufacture a field effect semiconductor device having a multi-finger structure in which the characteristics are made uniform and the variation in the electric characteristics is small. As a result, a highly reliable field effect semiconductor device having a multi-fingered T-shaped gate and a gate pad can be provided at low cost.

Further, the active layer formed on the substrate is a compound semiconductor, and in forming the gate lead-out electrode portion of the field effect semiconductor device of the compound semiconductor, at the connecting portion between the gate electrode and the gate lead-out electrode portion. 2 of resist film
Double exposure can be eliminated, and image sticking of the resist film can be prevented. Therefore, it is possible to manufacture a compound semiconductor field effect semiconductor device with less variation in electrical characteristics. Consequently, a highly reliable compound semiconductor field effect semiconductor device having a T-type gate and a gate pad can be provided at low cost.

[Brief description of drawings]

FIG. 1 is a partial plan view of a field effect semiconductor device according to one embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of the field effect semiconductor device taken along the line II-II in FIG.

3 is a partial cross-sectional view of the field effect semiconductor device taken along the line III-III in FIG.

4 is a partial cross-sectional view of the field effect semiconductor device taken along the line IV-IV in FIG.

FIG. 5 is a partial cross-sectional view of the field-effect semiconductor device in a step of the method for manufacturing the field-effect semiconductor device according to the embodiment of the present invention.

FIG. 6 is a partial cross-sectional view of the field-effect semiconductor device in a step of the method for manufacturing the field-effect semiconductor device according to the embodiment of the present invention.

7 is a partial cross-sectional view of the field effect semiconductor device taken along the line VII-VII in FIG.

FIG. 8 is a partial cross-sectional view of the field-effect semiconductor device in a step of the method for manufacturing the field-effect semiconductor device according to the embodiment of the present invention.

9 is a partial cross-sectional view of the field effect semiconductor device taken along the line IX-IX in FIG.

FIG. 10 is a partial cross-sectional view of the field-effect semiconductor device in a step of the method for manufacturing the field-effect semiconductor device according to the embodiment of the present invention.

11 is a partial cross-sectional view of the field effect semiconductor device taken along the line XI-XI in FIG.

FIG. 12 is a partial cross-sectional view of the field effect semiconductor device in a step of the method for manufacturing the field effect semiconductor device according to the embodiment of the present invention.

FIG. 13 is a partial cross-sectional view of the field-effect semiconductor device in a step of the method for manufacturing the field-effect semiconductor device according to the embodiment of the present invention.

14 is a partial cross-sectional view of the field effect semiconductor device taken along the line XIV-XIV in FIG.

FIG. 15 is a partial plan view of a conventional field effect transistor.

16 is an FE in the XVI-XVI cross section of FIG.
It is a partial cross section figure of T.

FIG. 17 is a partial cross-sectional view of the FET in the XVII-XVII cross section of FIG.

FIG. 18 is a partial cross-sectional view of the FET in the XVIII-XVIII cross section of FIG. 15.

FIG. 19 is a partial cross-sectional view of the FET in one step of the conventional FET manufacturing method.

FIG. 20 is a partial cross-sectional view of the FET in one step of the conventional FET manufacturing method.

FIG. 21 is a partial cross-sectional view of the FET in one step of the conventional FET manufacturing method.

FIG. 22 is a partial cross-sectional view of the FET in one step of the conventional FET manufacturing method.

FIG. 23 is a partial cross-sectional view of the FET in the XXIII-XXIII cross section of FIG. 22.

FIG. 24 is a partial cross-sectional view of the FET in the XXIV-XXIV cross section of FIG. 22.

[Explanation of symbols]

12 GaAs substrate, 14 active layer, 14a
Active region, 24 source electrode, 26 drain electrode, 20 gate electrode, 22 gate pad,
18 Recessed groove.

Claims (8)

[Claims] 1. A source electrode and a drain electrode which are disposed on the surface of an active layer disposed on a semiconductor substrate and which are juxtaposed to each other via an active region disposed in a part of the active layer, A gate electrode having a T-shaped cross section disposed between the source electrode and the drain electrode and disposed on the active region, and a part of the gate electrode covers an end surface of the gate electrode and is formed on the active layer surface. A field effect semiconductor device comprising: a gate extraction electrode portion provided. 2. The field effect semiconductor device according to claim 1, wherein a recess groove is provided on the surface of the active region, and a gate electrode is provided in the recess groove. 3. The field effect semiconductor device according to claim 1, wherein a plurality of gate electrodes are juxtaposed via a source electrode or a drain electrode and each is connected to a gate lead electrode portion. . 4. The field effect semiconductor device according to claim 1, wherein the active layer is made of a compound semiconductor. 5. A first step of sequentially forming a first resist film and a second resist film on a surface of an active layer formed on a semiconductor substrate, and a T-shaped section of a gate electrode having a T-shaped section. Forming a first resist pattern having a first opening corresponding to the band-shaped shielding film by exposing the first resist film using a photomask having a band-shaped shielding film corresponding to the head of the 2 step, and a band-shaped region of the second resist film exposed by the first opening of the first resist pattern, which is narrower than the first opening corresponding to the leg of the gate electrode having a T-shaped cross section. Is exposed using an electron beam to form a second resist pattern having a second opening in the exposed region, and a metal film is coated using the first and second resist patterns as a mask, Gate electrode is formed by lift-off A fourth step of removing the first and second resist patterns, and a fifth step of forming a third resist film on the active layer so as to cover the gate electrode, and partially covering the end of the gate electrode. A third resist film is exposed by using a photomask having a shielding film that covers a part of the active layer, and a third resist pattern having a third opening corresponding to the shielding film is formed. A method of manufacturing a field effect semiconductor device, comprising: a step of forming a gate lead electrode portion by covering a metal film with a third resist pattern as a mask and lifting off. 6. The method according to claim 5, wherein in the fourth step, the recess groove is formed by using the second resist pattern as a mask, and then the metal film is covered by using the first and second resist patterns as a mask. Of manufacturing a field effect semiconductor device of. 7. The photomask of the second step has a plurality of strip-shaped shielding films corresponding to the head of the gate electrode having a T-shaped cross section, and the photomask of the sixth step has each end of the gate electrode. 7. The method for manufacturing a field effect semiconductor device according to claim 5, further comprising a shielding film that partially covers the part and partially covers the active layer. 8. The method for manufacturing a field effect semiconductor device according to claim 5, wherein the active layer formed on the substrate is a compound semiconductor.