JP2003178595A5 - - Google Patents
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- Publication number
- JP2003178595A5 JP2003178595A5 JP2002300375A JP2002300375A JP2003178595A5 JP 2003178595 A5 JP2003178595 A5 JP 2003178595A5 JP 2002300375 A JP2002300375 A JP 2002300375A JP 2002300375 A JP2002300375 A JP 2002300375A JP 2003178595 A5 JP2003178595 A5 JP 2003178595A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/976,748 US6459648B1 (en) | 2001-10-13 | 2001-10-13 | Fault-tolerant address logic for solid state memory |
| US09/976748 | 2001-10-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003178595A JP2003178595A (ja) | 2003-06-27 |
| JP2003178595A5 true JP2003178595A5 (enExample) | 2005-12-02 |
Family
ID=25524415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002300375A Pending JP2003178595A (ja) | 2001-10-13 | 2002-10-15 | 固体メモリのフォールトトレラントなアドレスロジック |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6459648B1 (enExample) |
| JP (1) | JP2003178595A (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7157314B2 (en) * | 1998-11-16 | 2007-01-02 | Sandisk Corporation | Vertically stacked field programmable nonvolatile memory and method of fabrication |
| US6466512B1 (en) * | 2001-11-13 | 2002-10-15 | Hewlett Packard Company | Method of generating address configurations for solid state memory |
| US7003713B2 (en) * | 2002-05-16 | 2006-02-21 | Broadcom Corporation | Variable Hamming error correction for a one-time-programmable-ROM |
| US7489583B2 (en) * | 2005-09-06 | 2009-02-10 | Hewlett-Packard Development Company, L.P. | Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays |
| US7684265B2 (en) * | 2007-02-27 | 2010-03-23 | Analog Devices, Inc. | Redundant cross point switching system and method |
| WO2014038081A1 (ja) * | 2012-09-10 | 2014-03-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及び電池電圧監視装置 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4556960A (en) * | 1982-12-13 | 1985-12-03 | Sperry Corporation | Address sequencer for overwrite avoidance |
| JPH0696598A (ja) * | 1992-07-10 | 1994-04-08 | Texas Instr Japan Ltd | 半導体メモリ装置及び欠陥メモリセル救済回路 |
| US5721498A (en) * | 1995-12-11 | 1998-02-24 | Hewlett Packard Company | Block segmentation of configuration lines for fault tolerant programmable logic device |
| US6295231B1 (en) * | 1998-07-17 | 2001-09-25 | Kabushiki Kaisha Toshiba | High-speed cycle clock-synchronous memory device |
| US6360344B1 (en) * | 1998-12-31 | 2002-03-19 | Synopsys, Inc. | Built in self test algorithm that efficiently detects address related faults of a multiport memory without detailed placement and routing information |
| JP2000285694A (ja) * | 1999-03-30 | 2000-10-13 | Mitsubishi Electric Corp | 半導体記憶装置および半導体記憶装置を搭載する半導体集積回路装置 |
| US6304989B1 (en) * | 1999-07-21 | 2001-10-16 | Credence Systems Corporation | Built-in spare row and column replacement analysis system for embedded memories |
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2001
- 2001-10-13 US US09/976,748 patent/US6459648B1/en not_active Expired - Lifetime
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2002
- 2002-10-15 JP JP2002300375A patent/JP2003178595A/ja active Pending