JP2003178581A - Data transfer method for serial access memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a serial access memory of which the chip size is reduced and the cost of process development is saved. <P>SOLUTION: In a serial access memory having first decoders WY1, WY2,... responding to an inputted address signal WYAD, write-registers T1, T2,... temporarily storing data, a first switch SW2, and memory cells 11, and further, having a memory array having a plurality of memory columns 10 in which these memory cells 11 are connected by word lines WL1, WL2,... and a second switch SW1, the write-registers T1, T2,... are connected to the prescribed number of memory columns 10, and the write-registers T1, T2 and only one out of the prescribed number of the memory columns 10 are conducted responding to second selection signals WTR 1-4 through the second switch SW1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial access memory, and more particularly to an asynchronous serial access memory composed of a large capacity DRAM used in a television or the like.

[0002]

2. Description of the Related Art Serial access memories used for televisions, VTRs, etc. have independent input terminals and output terminals, and can use completely different frequencies for the input clock and the output clock. Since such an asynchronous serial access memory can simultaneously perform input / output access, it has various uses. As an example, consider a case where a video tape captured by a video camera is viewed on a television screen using a VTR. In this case, when the video is recorded on the video tape by the video camera, the synchronous clock CLK1 of the video camera system is used. However, VT
When playing a video tape with R, tape expansion and VT
Since the servo system of R is also mechanically operating, its timing clock does not become the synchronous clock CLK1 when reading the video data from the video tape, but becomes an irregular waveform clock. Since the image data synchronized with this irregular waveform clock cannot be image-processed by the VTR, it is necessary to convert it into the image data synchronized with the synchronized clock CLK2 arranged within the VTR system. Therefore, an asynchronous serial access memory is used in which writing can be performed with an irregular waveform clock and reading can be performed with a shaping clock. Another example in which an asynchronous serial access memory is used is when a personal computer screen is moved to a television or LCD panel. The drawing frequency on the PC screen is different from the drawing number on the TV. Therefore, the drawing frequency must be changed in order to display the PC screen on the TV. In this case, an asynchronous serial access memory that can perform input at the drawing frequency of the personal computer and output at the television frequency is very effective.

Such an asynchronous serial access memory has a large number of memory columns in which a plurality of memory cells each including a transistor and a capacitor are connected to a bit line.
It has a large capacity DRAM array of M bits or more as a data storage area. Further, the asynchronous serial access memory is connected to the write data bus for transferring the input data and the input data connected to the write data bus.
A write data register for temporarily storing data is provided. The asynchronous serial access memory is connected to a read data bus for transferring data to be output and a read data bus for temporarily storing the data to be output. It also has a data register.

[0004]

Normally, the number of memory columns in an asynchronous serial access memory is the same as the number of pixels on a line forming an image. When it comes to be compatible with a large-screen high-resolution TV screen and a PC high-resolution LCD panel, a large number of memory columns are required because the amount of pixel information on a unit line forming the screen increases. Therefore, the lengths of the write data bus and the read data bus are increased and the additional capacity is increased. Further, each write data register and read data register whose number has increased are
Since it is connected to the write data bus and the read data bus, the additional capacity of the connection node also increases. Therefore, the access speed becomes slow due to the increased load capacity. Also,
The asynchronous serial access memory has a DRAM array. Since the DRAM array needs to have a large capacity,
It is made by minimizing the bit line pitch and word line pitch. In the asynchronous serial access memory, it is necessary to connect the write data register and the read data register for each one bit line pair. But,
In order to draw each data register pattern with a usable process rule, the bit line pair pitch becomes too small and the bit line pair pitch itself must be widened. With this, the chip area becomes too large, and the cost becomes too high as compared with an ordinary DRAM. The present invention provides a serial access memory that maintains the access speed even if the length of the write data bus and the read data bus is increased and the added capacity is increased, and suppresses the cost increase even when the capacity is increased. The purpose is to do.

[0005]

In order to achieve the above object, the present invention responds to an input circuit to which data is input, a write data bus connected to this input circuit, and an input address signal. A first decoder for outputting a first selection signal, a write register for temporarily storing data, and a connection between the write data bus and the write register,
It has a first switch for electrically connecting the write data bus and the write register in response to a first selection signal, a plurality of memory cells, and a plurality of memory columns in which these memory cells are connected by word lines. And a second switch connected between the write register and the memory column and electrically connecting the write register and the memory column in response to the second selection signal. Connected to the memory column of
The second switch conducts only the write register and one of the predetermined number of memory columns in response to the second select signal.

[0006]

1 is a partial circuit diagram of a serial access memory according to a first embodiment of the present invention. In the memory column 10, a plurality of memory cells 11 are connected to the pair of bit lines BL1 to m and BL1 to m /. Memory cell 1
Reference numeral 1 denotes a DRAM cell, which is composed of one transistor and a capacitor connected to the word lines WL1 to WLn. The memory column 10 also has sense amplifiers SA1 to SAm which are controlled by the sense amplifier activation signals SAP and SAN and which amplify the data of the memory cell 11. One end of the memory column 10 has write data registers T1 and T1 for temporarily storing input data via a transistor pair SW1 which is a first switch.
2. ． ． Connected to. Here, the write data registers T1, T2. ． ． Is an SRAM consisting of two inverters
The write data registers T1 and T are composed of cells.
2. ． ． Four memory columns 10 are connected to one. The write transfer signal WTR is applied to the first switch SW1.
1 to WTR4, one write data register T1, T2. ． ． And one memory column 10 is selectively connected. Write data registers T1, T2. ． ． Is connected to the write data buses WD and WD / to which the signal input via the transistor pair SW2 which is the second switch is transferred. The second switch SW2 has write transfer signals W1, W2. ． ． To output the light Y decoders WY1, WY2. ． ． Are connected. Write transfer signals W1, W2. ． ． In response to the second
The switch SW2 of the write data buses WD, WD / and the write data registers T1, T2. ． ． And connect. On the other hand, the other end of the memory column 10 is connected to the read data registers S1, S2. ． ． Connected to. Here, the read data registers S1, S2. ． ． Is composed of an SRAM cell composed of two inverters, and the read data registers S1, S2. ． ． Four memory columns 10 are connected to one. The read transfer signals RTR1 to RTR4 are given to the third switch SW3, and one read data is read.
Register S1, S2. ． ． And one memory column 10
Are selectively connected. Read data registers S1, S2. ． ． Is connected to the read data buses RD and RD / to which the signal inputted through the transistor pair SW4 which is the fourth switch is transferred. Fourth
Switch SW4 of the received read Y address R
Read transfer signals R1, R2. ． ． To output the lead Y decoders RY1, RY2. ． ． Are connected. Read transfer signals R1, R2. ． ． In response to this, the fourth switch SW4 is connected to the read data buses RD and R.
D / and read data registers S1, S2. ． ． And connect.

The write data buses WD and WD / are connected via an input circuit 20 to an input terminal DI to which data is input. The read data buses RD and RD / are
It is connected via an output circuit 21 to an output terminal DO for outputting data. Word lines WL1-n are X decoder 2
Connected to 2. The X decoder 22 responds to the write X address WXAD to write data to the memory cell 1 when writing.
1 to specify the word lines WL1 to WLn, and in response to the read X address RXAD, word lines WL1 to WLn for specifying the memory cell 11 at the time of reading.
Select. A plurality of memory columns (four in the first embodiment) connected to the same write data register and read data register, a write Y decoder, and a read Y decoder are included. The other group is defined as a memory column group 12 here. Although not shown in FIG. 1, the serial access memory according to the first embodiment has first and second banks. The first and second banks each have a configuration including a plurality of memory column groups 12 as shown in FIG. 1, and can operate independently. The internal control signal 23 for controlling the first and second banks is generated by the memory-control signal generation circuit 24. The memory control signal generation circuit 24 includes a write clock signal WCLK, a write reset signal WR, which are external signals.
Write enable signal WE, read clock signal RCL
K, read reset signal RR, read enable signal R
E or the like is input. The arbiter 25 connected to the memory-control signal generating circuit 24 ranks these signals in order to avoid collision of the read transfer signal and the write transfer signal.

According to the first embodiment of the present invention, since one write register T1 or read register S1 is connected to four memory columns 10, the number of registers for the memory columns decreases. As shown in FIG. 1, pattern spaces 30 and 31 are obtained. Therefore, the pattern of the write register T1 or the read register S1 can be prepared with a margin without widening the bit line pitch of the memory column 10 (without increasing the vertical dimension in FIG. 1). .. From this,
The chip size can be reduced with the process of the conventional technology, and the advantages of cost saving and chip size reduction can be obtained.

FIG. 2 is a timing chart showing the operation timing of the serial memory of the first embodiment. The operation of the serial memory according to the first embodiment will be described below with reference to FIG. Each control signal is taken in in synchronization with the rising of the read clock signal RCLK or the write clock signal WCLK to determine the circuit operation.
First, the read operation of the serial memory of the first embodiment will be described for each time shown in FIG. Since the time Rt0 read reset signal RR is at the high level, the X address XAD (for simplification, the read X address RXAD and the write X address WXAD are collectively referred to as the X address XAD), the read The Y address for read RYAD is reset to low level. That is,
The read Y address RYAD is in the state of the address "0". Time Rt1 Word line WL1 rises, word line WL1
The memory cell information in the memory cell group connected to is transferred to the bit line pair BLi, BLi / (i = 0 to m-1). Although not shown in FIG. 2, the sense amplifier activation signal SAP is at a high level, and the sense amplifier activation signal SAN is
Goes low, the sense amplifier SAi becomes active. As a result, the bit line pair BLi, B
The information on Li / is amplified. Time Rt2 The read transfer signal RTR1 rises, and the read transfer signals RTR2-4 keep a low level. As a result, the read register Rk-1 and the bit line pair BL4k + 1, BL4k
+ 1 / is connected. Therefore, bit line pair B
Information on L4k + 1, BL4k + 1 / is read register R
k-1. Time Rt3 The word line WL1 becomes low level. Although not shown in FIG. 2, sense amplifier activation signals SAP, SAN
Are both at an intermediate level (because of the intermediate potential between the high level and the low level, the bit line pair BL4k + 1, BL
The information on 4k + 1 / is reset. At this time, the read transfer signal RTR1 is at the low level, and the read transfer signals RTR2-4 are kept at the low level. At time Rt4, the read enable signal RE becomes high and the serial read
The internal operation for the card starts.

Time Rt5 In response to the read Y address signal RYAD (address "0"), the output R1 of the Y decoder RY1 becomes high level. As a result, the data of the read register S1 is transferred to the read data bus pair RD, RD /. The data on the read data bus pair RD, RD / is transferred to the output circuit 21 and output from the output terminal DO. After that, Y for lead
The address RYAD is incremented to become the address (“1”) used at time Rt6. Time Rt6 In response to the read Y address signal RYAD (address "1"), the output R2 of the Y decoder RY2 becomes high level. As a result, the data of the read register S2 is transferred to the read data bus pair RD, RD /. The data on the read data bus pair RD, RD / is transferred to the output circuit 21 and output from the output terminal DO. After that, Y for lead
The address RYAD is incremented to become the address (“2”) used at time Rt7. Time Rt7 In response to the read Y address signal RYAD (address "2"), the output R3 of the Y decoder RY3 becomes high level. As a result, the data of the read register S3 is transferred to the read data bus pair RD, RD /. The data on the read data bus pair RD, RD / is transferred to the output circuit 21 and output from the output terminal DO. After that, Y for lead
The address RYAD is incremented to become the address (“3”). The above circuit operation is repeated until the address of the read Y address signal becomes "k", and a series of serial read operations are performed. In the next series of serial read operations, unlike the operation described at time Rt2, only the read transfer signal RTR2 becomes high level,
The other read transfer signals RTR1, 3 and 4 maintain the low level. As a result, the read register Rk-1 is connected to the bit line pair BL4k + 2, BL4k + 2 /. Therefore, the bit line pair BL4k + 2, BL4k + 2 /
The above information is transferred to the read register Rk-1. After this, the operations described at times Rt4 to 7 are sequentially repeated. Further, before the series of serial operations, the read transfer signal R
The operation is repeated in the order that only TR3 goes high and only the read transfer signal RTR4 goes high, and then only the read transfer signal RTR1 goes high.

Next, the write operation of the serial memory of the first embodiment will be described for each time shown in FIG. Since the time Wt0 write reset signal WR is at the high level, the write Y address WYAD is reset and is in the state of the address “0”. The input information of the first bit is fetched from the input terminal DI into the input circuit 20 and transferred to the write data bus pair WD, WD /. Since the output W1 of the write Y decoder WY1 is at high level,
The data on the write data bus pair WD, WD / is transferred to the write register T1. The second bit of input information from the time Wt1 input terminal DI is input circuit 2
It is taken into 0 and transferred to the write data bus pair WD, WD /. Since the output W2 of the write Y decoder WY2 is at a high level, the write data bus pair WD, WD
The above data is transferred to the write register T2. At time Wt2, the input information of the j-th bit from the input terminal DI is input circuit 2
It is taken into 0 and transferred to the write data bus pair WD, WD /. Since the output Wj of the write Y decoder WYj is at the high level, the write data bus pair WD, WD
The above data is transferred to the write register Tj. At the time Wt3, the input information of the (k + 1) th bit is taken into the input circuit 20 from the input terminal DI, and the write data bus pair WD, WD /
Transferred to. Light Y decoder WYk + 1 output Wk +
Since 1 is at the high level, the data on the write data bus pair WD, WD / is transferred to the write register Tk + 1. This completes the entire series of write operations to the write register.

Time Wt4 Only the write transfer signal WRT1 becomes high level, and the other write transfer signals WRT2-4 keep low level. As a result, each write register Ti (where i = 0 to k)
And the bit line pair BL4i + 1, BL4i + 1 /. Although not shown in FIG. 2, the sense amplifier activation signal SAN is low, and the sense amplifier activation signal S is low.
Sense amplifier SA4 because AP is at high level
i + 1 is activated. Since the word line WL1 becomes high level, it is connected to this word line WL1,
The bit line pair BL4i + 1, to the memory cell 11 connected to the bit line pair BL4i + 1, BL4i + 1 /
The data on BL4i + 1 / is written. Other bit line pairs BL4i + 2, BL4i + 2 //, BL4i +
3, BL4i + 3 /, BL4i + 4, BL4i + 4 /
The information of the memory cell connected to the word line WL1 is once read to the bit line pair, amplified by the sense amplifier, and then written to the original memory cell. This operation is generally called "rewriting". After that, the series of write operations to the write register described from time Wt0 to time Wt3 is performed again. After that, only the write transfer signal WRT2 becomes high level, and the other write transfer signals WRT1, 3, 4 remain low level. As a result, each write register Ti (where i = 0 to k)
And the bit line pair BL4i + 2, BL4i + 2 /. Then, the bit line pair BL4i + 2, BL is connected to the activated word line and the memory cell 11 connected to the bit line pair BL4i + 2, BL4i + 2 /.
The data on 4i + 2 / is written. The rewriting operation is performed on the other bit line pairs. The above operation is similarly performed for the write transfer signals WRT3, 4 and the serial write operation returns to Wt0 described first.

In the first embodiment, one memory column group 12 is composed of four memory columns. However, it suffices if it has a plurality of memory columns. It can be arbitrarily selected. Further, although the first embodiment has been described with respect to the configuration having both the read register and the write register, the merit of the present invention can be fully enjoyed depending on the application even if only the read register or the write register is used. Further, in the first embodiment, the Y decoder is a Y decoder for writing and a Y decoder for reading.
I explained it by dividing it into two, but it is a shared Y decoration that shared these.
You can also use da. Regarding the banks, the first embodiment has been described as having the first and second banks, but the number of banks may be one or more.

Now, a circuit for generating the write transfer signals WTR1 to WTR4 in the first embodiment will be described. FIG. 3 shows a write Y address WYAD and a write transfer signal W.
FIG. 4 is a circuit diagram showing a write address generation circuit for generating TR1 to TR4 (here, write transfer signals WTR1a to WTR4a for the first bank and write transfer signals WTR1b to WTR4b for the second bank). 6 is a timing chart showing the operation of the address generation circuit. The write address generation circuit is composed of a shift register 30, a first decoder 31 and a second decoder 32.
The shift register 30 has n + 1 flip-flops C0.
To Cn. The write clock signal WCLK is input to the clock input terminals c of the flip-flops C0 to Cn. The first terminals of the NMOS transistors are connected to the reset terminals of the flip-flops C0 to Cn. The second terminal of the NMOS transistor is grounded, and the gate is commonly supplied with a write reset signal WR. The input a of the first flip-flop C0 is grounded, and the output d is connected to the input of the second flip-flop C1. The output signal from the other output e of the first flip-flop C0 and its inverted signal are the write Y address W
Address signals WAY0, WAY0 / which are a part of YAD
become. The output d of the second flip-flop C1 is connected to the input of the third flip-flop C2. The output signal from the other output e of the second flip-flop C1 and its inverted signal become the address signals WAY1 and WAY1 / which are a part of the write Y address WYAD. Furthermore, the nth
The connection relationship up to the flip-flop is the same, but the write Y address WYAD is the address signals WAY1 to WAYn.
-2, WAY1 to n-2 /. Address signal WAYn-
1, WAYn-1 /, WAYn, WAYn / are used to generate the write transfer signals WTR1a to WTR4b.

The first decoder 31 is composed of a NAND circuit. The first NAND circuit has an address signal WA
Yn-1, WAYn and the write transfer signal WTR are input, and the output thereof is inverted by the inverter and becomes the signal 11.
The second NAND circuit has an address signal WAYn-1 /,
WAYn and the write transfer signal WTR are input, and the output thereof is inverted by the inverter and becomes the signal 10. Third N
The AND circuit has address signals WAYn-1, WAYn.
/ And the write transfer signal WTR are input, and the output thereof is inverted by the inverter and becomes the signal 01. The address signals WAYn-1 /, WAYn / and the write transfer signal WTR are input to the fourth NAND circuit, and the output thereof is inverted by the inverter and becomes the signal 00. The second decoder 32 is also NA
It is composed of an ND circuit. The first NAND circuit has a first
Decoder output signal 00 and address signal WAYn-
2 is input, the output is inverted by the inverter, and the first
Bank write transfer signal WTR1a. Second N
The output signal 01 of the first decoder and the address signal WAYn-2 are input to the AND circuit, the output of which is inverted by the inverter and the write transfer signal WTR of the first bank.
2a. The output signal 10 of the first decoder and the address signal WAYn-2 are input to the third NAND circuit, and the output thereof is inverted by the inverter and becomes the write transfer signal WTR3a of the first bank. The output signal 11 of the first decoder and the address signal WAYn-2 are input to the fourth NAND circuit, and the output thereof is inverted by the inverter and becomes the write transfer signal WTR4a of the first bank. The output signal 00 of the first decoder and the address signal WAYn-2 / are input to the fifth NAND circuit, and the output thereof is inverted by the inverter and becomes the write transfer signal WTR1b of the second bank. . The sixth NAND circuit has a first decoder output signal 01 and an address signal WAYn.
-2 / is input and its output is inverted by the inverter and becomes the write transfer signal WTR2b of the second bank. The output signal 10 of the first decoder and the address signal WAYn-2 / are input to the seventh NAND circuit, the output of which is inverted by the inverter and the write transfer signal WT of the second bank.
It becomes R3b. The eighth NAND circuit has a first decor
Output signal 11 and address signal WAYn-2 / are input and the output thereof is inverted by the inverter and becomes the write transfer signal WTR4b of the second bank.

FIG. 4 is a timing chart for explaining the operation of the write address generating circuit shown in FIG. At time t0 when the write clock signal WCLK rises, when the write enable signal WE and the write reset signal WR become high level, the generation of the address signal is started.
Next, at time t1 when the write clock signal rises, the address signal WAY0 becomes high level. Further, at time t2 when the write clock signal rises, the address signal WAY0 becomes high level again, and the address signal W0
AY1 goes high. Address signal WAY0-n
Since the write clock signal is sequentially divided, the description thereof will be omitted. At time t3, the write transfer signal WTR and the address signal WAYn-2
Goes high, and the address signals WAYn-1, WA
Yn remains low level. As a result, the write transfer signal WTR1a of the first bank becomes high level.
Further, at time t4, the write transfer signal WTR and the address signal WAYn-1 become high level, and the address signals WAYn-2 and WAYn become low level. As a result, the write transfer signal WTR of the second bank
1b goes high. Other write transfer signals W
Since TR2a to WTR4b can be understood by referring to the logic, the description thereof will be omitted.

Next, a circuit for generating the read transfer signals RTR1-4 will be described. FIG. 5 shows a read Y address RYAD and read transfer signals RTR1 to 4 (here, read transfer signals RTR1a to RT for the first bank).
Read transfer signal RTR1b for R4a and second bank
.About.RTR4b) is a circuit diagram showing a read address generating circuit, and FIG. 6 is a timing chart showing the operation of the read address generating circuit. The read address generation circuit includes a shift register 50, a first decoder 51, and a second decoder.
Of the decoder 52 and the initial transfer control circuit 53. The shift register 50 has n + 1 flip-flops C0 to Cn. Flip flop C
The read clock signal RCLK is input to the clock input terminals c of 0 to Cn. The first terminals of the NMOS transistors are connected to the reset terminals of the flip-flops C0 to Cn. The second terminal of this NMOS transistor is grounded, and a read reset signal R is commonly provided to the gate.
R is given. Input a of the first flip-flop C0
Is grounded and the output d is connected to the input of the second flip-flop C1. The output signal from the other output e of the first flip-flop C0 and its inverted signal are address signals RAY0, RY which are a part of the read Y address RYAD.
It becomes AY0 /. Output d of the second flip-flop C1
Is connected to the input of the third flip-flop C2. The output signal from the other output e of the second flip-flop C1 and its inverted signal become the address signals RAY1 and RAY1 / which are a part of the read Y address RYAD. Further, the connection relationship up to the nth flip-flop is the same, but the read Y address RYAD is the address signal RA.
Y1 to n-2 and RAY1 to n-2 /. The address signals RAYn-1, RAYn-1 /, RAYn, RAYn / are used to generate the read transfer signals RTR1a to RTR4b.

The first decoder 51 is composed of a NAND circuit. The first NAND circuit has an address signal RA
Yn-1, RAYn and the read transfer signal RTR are input, and the output thereof is inverted by the inverter to become the signal 11.
The second NAND circuit has address signals RAYn-1 /,
RAYn and the read transfer signal RTR are input, and the output thereof is inverted by the inverter to become the signal 10. Third N
The AND circuit has address signals RAYn-1, RAYn.
/ And the read transfer signal RTR are input, and the output is inverted by the inverter to become the signal 01. The address signals RAYn-1 /, RAYn / and the read transfer signal RTR are input to the fourth NAND circuit, and the output thereof is inverted by the inverter and becomes the signal 00. The second decoder 52 is also NA
It is composed of an ND circuit. The first NAND circuit has a first
Output signal 00 and address signal RAY of the decoder 51 of
n-2 is input. The output of the first NAND circuit is NORed with the output signal RRS / of the initial transfer control circuit and becomes the read transfer signal RTR1a of the first bank. The output signal 01 of the first decoder 51 and the address signal RAYn-2 are input to the second NAND circuit, the output of which is inverted by the inverter and the read transfer signal RTR2a of the first bank. Becomes The output signal 10 of the first decoder 51 and the address signal RAYn-2 are input to the third NAND circuit, the output of which is inverted by the inverter and the read transfer signal RTR3a of the first bank. Becomes The output signal 11 of the first decoder 51 and the address signal RAYn-2 are input to the fourth NAND circuit, the output of which is inverted by the inverter and the read transfer signal RTR4a of the first bank. Becomes The output signal 00 of the first decoder 51 and the address signal RAYn-2 / are input to the fifth NAND circuit, the output of which is inverted by the inverter and the read transfer signal of the second bank. It becomes RTR1b. The output signal 01 of the first decoder 51 and the address signal RAYn-2 / are input to the sixth NAND circuit, the output of which is inverted by the inverter and the read transfer signal of the second bank. It becomes RTR2b. The output signal 10 of the first decoder 51 and the address signal RAYn-2 / are input to the seventh NAND circuit, the output of which is inverted by the inverter and the write transfer signal RTR3b of the second bank. Become. The output signal 11 of the first decoder 51 and the address signal RAYn-2 / are input to the eighth NAND circuit, the output of which is inverted by the inverter and the write transfer signal RTR4b of the second bank. Become. The initial transfer control circuit is a circuit provided for adjusting the initial state of read transfer, receives a read reset signal, and outputs this read reset signal.
It is a circuit that outputs a signal RRS / which is in an active state for a slightly longer period than the read transfer signal RTR in response to the reset signal.

FIG. 6 is a timing chart for explaining the operation of the read address generating circuit shown in FIG. Lee
At time t0 when the clock signal RCLK rises, the read reset signal RR becomes high level. At this time,
The read enable signal RE remains low level,
The output signal RRS / of the initial transfer circuit is low level in response to the read reset signal RR. In addition,
Since the read transfer signal RTR also becomes high level, the read transfer signal RTR1a of the first bank also becomes high level. After that, when the read transfer signal RTR becomes low level, the first
The bank read transfer signal RTR1a also goes low, and thereafter the output signal RRS / of the initial transfer circuit goes high. At time t1 when the read reset signal RR rises and the read clock signal RCLK first rises, the generation of the address signal is started. Next, at time t2 when the write clock signal RCLK rises, the address signal RAY0 becomes high level. At time t3 when the write clock signal RCLK rises, the address signal RAY0 goes high again and the address signal RAY2 goes high. At this time, the read transfer signal RTR also becomes high level, and therefore the read transfer signal RTR1b of the second bank also becomes high level. Since the address signals RAY0 to RAYn are sequentially divided from the read clock signal RCLK, description thereof will be omitted. At time t4, the read transfer signal RTR and the address signal RAYn-2 become high level, and the address signals WAYn-1 and WAYn remain low level. As a result, the read transfer signal R of the first bank
TR2a becomes high level. Further, at time t5, the read transfer signal RTR and the address signal RAYn.
-1 goes high, and address signals RAYn-2, R
AYn goes low. As a result, the read transfer signal RTR2b of the second bank becomes high level. The other read transfer signals RTR3a to RTR4b can be understood by referring to the logic, and the description thereof will be omitted.

FIG. 7 is a partial circuit diagram of the serial access memory according to the second embodiment of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. The serial access memory of the second embodiment has exactly the same circuit configuration, but the circuit layout is different. In the serial access memory of the first embodiment, the write Y decoders WY1, WY2. ． ． And write registers T1, T2. ． ． Are connected to one end of the memory column 10 and read Y decoders RY1, RY2. ． ． And read registers S1, S2. ． ． Was connected to the other end of the memory column 10. In the serial access memory of the second embodiment, the write Y decoders WY1, WY2. ． ． , Write registers T1, T2. ． ． , Y decoders for reading RY1, RY2. ． ． And read registers S1 and S
2. ． ． Were connected to the same end side. The circuit structure of the serial access memory of the second embodiment is the same as that of the serial access memory of the first embodiment, so the operation is also the same. Therefore, description of the operation of the serial access memory of the second embodiment is omitted. Due to the above connection relationship, the write registers T1, T2. ． ． And read registers S1, S2. ． ． The areas for pattern design are smaller than those in the first embodiment because they are provided in close proximity to each other, but the chip area can be reduced accordingly, and there is an advantage that the manufacturing cost can be reduced.

FIG. 8 is a partial circuit diagram of the serial access memory according to the third embodiment of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. In the serial access memory of the third embodiment, the second
Of the write registers T1, T2. ． ． And read registers S1, S2. ． ． Are connected on the same end side of the memory column 10. A characteristic point of the serial access memory of the third embodiment is that it has a configuration in which every other memory column 10 forming the memory column group 12 is arranged. That is, the bit line pair BL1, BL1
/, BL3, BL3 /, BL5, BL5 /, BL7, B
One memory column group 12 is formed by L7 /. In the memory column group 12, the write register T1 and the read register S1 are connected on one side (left side in the drawing) of the memory column.
Further, the sense amplifiers SA1 and SA of the memory column
3. ． ． Are arranged outside the write register T1 and the read register S1. On the other hand, bit line pair BL2, B
L2 /, BL4, BL4 /, BL6, BL6 /, BL
Two memory column groups 1 by 8, BL8 /
2 is formed. And this memory column group 1
2, the write register T2 and the read register S2 are connected on the other side (right side in the drawing) of the memory column. Further, the sense amplifier SA2 of the memory column,
SA4. ． ． Write register T2 and read register S
It is placed outside of 2. In the third embodiment, the write transfer signal and the read transfer signal are divided into one end side and the other end side with respect to the memory column, and a and b are added to clarify. However, the sense amplifier activation signal S
Ana, SAPa, SANb, SAPb, Light Day
Tabas WDa, WDa /, WDb, WDb /, read data
Tabas is RDa, RDa /, RDb, RDb /, read transfer signals RTRa1 to RTRb4, write transfer signal WR.
Ta1 to b4 may be the same signal or finally the same line without distinction between a and b. What should be noted here is the distinction from the signals for the first and second banks described in FIGS. As previously mentioned, the first bank and the second bank can operate independently. However, in the third embodiment, since the circuit arrangement in the same bank is a problem,
As each signal, the same signal as in the first embodiment can be used. In the third embodiment, the selection signal SEL
a and SELb are newly added. This selection signal SE
La and SELb are signals for determining whether to access from the a side (right side of the drawing) or b side (left side of the drawing). On the other hand, the write registers T1 and T2 are selected by the logical product of the commonly input write Y address WYA and the selection signals SELa and SELb. Further, the selection of the read registers S1 and S2 is also performed by commonly inputting the read Y address RYA and the selection signal SE.
It is selected by the logical product of La and SELb. Third
Regarding the operation of the serial access memory of the embodiment of
Since it is similar to the serial access memory of the first embodiment,
The description is omitted. In the third embodiment, since the sense amplifier can be formed between two memory column pitches, the memory column pitch can be reduced. Also, the write register and the read register are connected to the memory column group 1
Since it can be formed in a pitch twice as large as 2, it can be formed with a margin twice as large as that in the second embodiment. Therefore, the chip area can be reduced and a low cost serial access memory can be provided.

9 and 10 are partial circuit diagrams of the serial access memory according to the fourth embodiment of the present invention. The same parts as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted. In the serial access memory of the fourth embodiment, as in the third embodiment, the memory column 10 forming the memory column group is alternated, and the write registers T1, T2. ． ． And read registers S1 and S
2. ． ． Are connected on the same end side of the memory column 10. A characteristic point of the serial access memory of the fourth embodiment is that, as shown in FIG. 9, a plurality of memory columns 10 forming a memory column group 12 are vertically arranged, and between these columns. The sense amplifiers SA1 to SA4, the read register S1 and the write register T1 are provided. The sense amplifiers SA1 to SA4, the read register S1 and the write register T1 provided between the memory column columns are selectively connected to the memory columns 10 on both sides. That is, the sense amplifiers SA1 to SA4, the read register S1 and the write register T1 shown in FIG. The sense amplifiers SA1 to SA4, the read register S1 and the write register T1 are also connected to a memory column (not shown) on the other side (left side in the drawing) via transfer transistors tr1 to tr8. Transfer transistor tr1
Open / close control is performed by the bit line pair selection signal BLB. The transfer transistors tr33 to 40 are controlled to be opened / closed by a bit line pair selection signal BLA.
In the fourth embodiment, the transistors Tr29 to Tr32 for equalizing the bit lines are provided in each bit line pair. Transistors tr29-32 equalize the bit line pair in response to the equalize signal EQ.

FIG. 10 shows a circuit diagram of one end portion of the memory column row of the serial access memory of the fourth embodiment. Therefore, FIG. 10 is connected to the right side of FIG. It goes without saying that there is a memory column (in some cases, there are two memory columns, and there may be a circuit as shown in FIG. 9 in the center) between FIG. 10 and FIG. Yes. Sense amplifiers SA1 to SA1 shown in FIG.
4 and the read register S1 and the write register T1 are also connected to the memory column (not shown) on the other side (left side in the drawing) via transfer transistors tr1 to tr8. The transfer transistors tr1 to tr8 are controlled to open / close by a bit line pair selection signal BLA. Note that, similarly to FIG. 9, the transistors tr29 to 32 equalize the bit line pair in response to the equalize signal EQ. Although not disclosed in FIGS. 9 and 10, in the fourth embodiment, there are a sense amplifier, a read register and a write register connected to the left side of FIG. 9 via a memory column. The circuit configuration is the circuit of FIG. 10 which is symmetrical. The signals supplied to the circuit are the same as those of the circuit shown in FIG. 10 except that the bit line pair selection signal BLB is supplied to the transfer transistors Tr1 to Tr8 and the selection signal SELb is supplied to the read register and the write register. Is.

Next, the operation of the serial access memory according to the fourth embodiment will be described. The operation is described in FIG.
The circuit shown in FIG. 10 is connected to the right side of the circuit shown in FIG. 10 via the first memory column row, and the circuit shown in FIG. 9 is connected to the left side of the circuit shown in FIG. The target is a serial access memory to which a circuit symmetrical to the circuit described in 10 is connected. First, the bit line pair selection signal BLA is set to high level and the bit line pair selection signal BLB is set to low level. As a result, FIG.
Transfer transistors tr33 to 40 shown in FIG.
The transfer transistors tr1 to tr8 shown in FIG. 10 are turned on. Therefore, the sense amplifiers SA1 to SA4 shown in FIG. 9 and the sense amplifiers SA1 to SA1 shown in FIG.
4 is connected to the first memory column column (on the right side in FIG. 9) between the circuit shown in FIG. 9 and the circuit shown in FIG. Subsequent operations are the same as those in the third embodiment, and the description thereof will be omitted. Next, the bit line pair selection signal BLA is set to low level and the bit line pair selection signal B is set.
Set LB to high level. As a result, the transfer transistors tr1 to tr8 shown in FIG. 9 and the transfer transistors tr1 to tr8 in the symmetrical circuit of the circuit shown in FIG. 10 are turned on. Therefore, the sense amplifiers SA1 to SA4 shown in FIG. 9 and the sense amplifiers SA1 to SA4 in the symmetrical circuit of the circuit shown in FIG.
It is connected to the second memory column column (on the left side in FIG. 9) between the circuits shown in FIG. 10 and the circuit shown in FIG. Subsequent operations are the same as those in the third embodiment, and the description thereof will be omitted. The fourth embodiment is effective when the length of the bit line pair in the memory cell array becomes long. When the bit line of the memory cell array becomes long (for example, the horizontal direction shown in FIG. 1 becomes long), the parasitic capacitance of the bit line becomes large and the write / read time of the memory becomes long. Therefore, in the fourth embodiment in which the bit line length is shortened,
Supports large-capacity serial access memory. Moreover, the chip area can be reduced as in the case of the third embodiment, and an inexpensive and large-capacity serial access memory can be provided.

11 and 12 are partial circuit diagrams of a serial access memory according to the fifth embodiment of the present invention. The same parts as those in the fourth embodiment are designated by the same reference numerals and the description thereof will be omitted. In the serial access memory of the fifth embodiment, a plurality of memory columns 10 forming a memory column group 12 are arranged vertically as in the fourth embodiment, and sense amplifiers SA1 to SA4 and A read register S1 and a write register T1 are provided. The serial access memory of the fifth embodiment has two read registers and no write register. Therefore, the writing of information to the memory cell is directly performed. In the serial access memory of the fifth embodiment, the memory column group 12 is composed of two memory columns. The configuration of the serial access memory according to the fifth embodiment will be described below, focusing on the difference from the fourth embodiment. The circuits of FIGS. 11 and 12 are arranged similarly to those of FIGS. 9 and 10 of the third embodiment. That is, the sense amplifier SA in FIG.
1, 2 and the read register S1 are connected to one side (left side in the drawing) of a memory column 10 (bit line pair BLa1, B1) via transfer transistors tr1 to tr4.
La1 /, BLa2, BLa2 /).
In addition, the sense amplifiers SA1 and SA2 and the read register S1
Is a memory column (bit line pair BLb1, BLb1 //, BLb2, BLb2) (not shown) on the other side (right side in the drawing) via the transfer transistors tr17 to 20.
/) Is also connected. Transfer transistor t
Opening and closing of r1 to 4 are controlled by the bit line pair selection signal BLB. Transfer transistors tr17 to 20
Is controlled by a bit line pair selection signal BLA. In the fourth embodiment, the write data bus pair WD,
WD / is a transfer transistor tr15, tr1
6, tr5, tr6, tr11 and tr12 are connected to the bit line. The read data bus pair RD, RD / is a transfer transistor tr13,
It is connected to the read register S1 via tr14. The read register S1 is a transfer transistor t
Connected to the bit line via r7-10. The transfer transistors tr13 to tr16 are commonly controlled to be opened / closed by the Y decoder output signal Y1. The transfer transistors tr5 and tr6 are write selection signals WSEL0.
In addition, the transfer transistors tr11 and 12 receive the write selection signal WSEL1
r9 and 10 are read selection signals RSEL0, and transfer transistors tr7 and 8 are read selection signals RSE.
Opening / closing control is performed by L1. In the circuit shown in FIG. 12, the description of the same parts as those in the circuit shown in FIG. 11 will be omitted. In the circuit of FIG. 12, there is no part corresponding to the transfer transistors tr17 to tr20 of FIG. The transfer transistors tr1 to tr4 are connected to the bit line pair BLb3, BLb3.
/, BLb4, BLb4 /. Similar to the fourth embodiment,
Although not disclosed in FIGS. 11 and 12, a sense amplifier and a reader connected to the left side of FIG. 9 via a memory column.
There is a register. The circuit configuration is the circuit of FIG. 12 which is symmetrical. The signal supplied to the circuit is the same as the circuit shown in FIG. 12 except that the bit line pair selection signal BLB is supplied to the transfer transistors Tr1 to Tr4.

Next, the operation of the serial access memory of the fifth embodiment will be described. Note that the operation description is given in FIG.
The circuit shown in FIG. 12 is connected to the right side of the circuit described in 1 through the first memory column row, and the left side of the circuit described in FIG. 11 is described above through the second memory column row. The target is a serial access memory to which a circuit which is symmetrical to the circuit shown in FIG. 12 is connected. First, the bit line pair selection signal BLA is set to high level and the bit line pair selection signal BLB is set to low level. This allows
The transfer transistors tr17 to 2 shown in FIG.
0 and the transfer transistor tr1 shown in FIG.
~ 4 is turned on. Therefore, the sense amplifiers SA1 and SA2 shown in FIG. 11 and the sense amplifiers SA1 and SA2 shown in FIG. 10 are located between the circuit shown in FIG. 11 and the circuit shown in FIG. 12 (on the right side in FIG. 11). Connected to the memory column row of. When the write operation is performed thereafter, the output signal Y1 of the Y decoder becomes high level, the write selection signal SEL0 becomes high level, and the write selection signal SEL1 becomes low level. As a result, the write data buses WD, WD / and the bit lines BL2b, Bl2b /
Are connected. Therefore, the write data buses WD, W
Data on D / is directly on the bit lines BL2b, Bl2b /
Is written to the memory cell connected to. Regarding the read operation, the bit line selection is the same as the successful write operation, and other operations are the same as those in the third embodiment, and therefore the description thereof is omitted. Next, the bit line pair selection signal BLA is set to low level and the bit line pair selection signal B is set.
Set LB to high level. As a result, the transfer transistors tr1 to tr8 shown in FIG. 9 and the transfer transistors tr1 to tr8 in the symmetrical circuit of the circuit shown in FIG. 10 are turned on. Therefore, the sense amplifiers SA1 to SA4 shown in FIG. 9 and the sense amplifiers SA1 to SA4 in the symmetrical circuit of the circuit shown in FIG.
It is connected to the second memory column column (on the left side in FIG. 9) between the circuits shown in FIG. 10 and the circuit shown in FIG. Subsequent operations are the same as the read operation and the write operation described above, and thus the description thereof is omitted.

13 and 14 are partial circuit diagrams of a serial access memory which is a modification of the fifth embodiment. The same parts as those in the fifth embodiment are designated by the same reference numerals and the description thereof will be omitted. In the serial access memory which is a modification of the fifth embodiment, the Y decoder output signal Y1 used for both read / write in the fifth embodiment is read.
It is divided into the Y decoder output signal RY1 for read and the output signal WY1 for write. Therefore, the read Y decoder output signal RY1 is applied to the transfer transistors tr13 and tr14, and the write decoder output signal WY1 is transferred to the transfer transistors tr15 and tr14.
Given to 16. Except for the above points, the circuit configuration and operation are the same as those in the fifth embodiment, and therefore their explanations are omitted.

15 to 18 are schematic diagrams showing the operation of the serial access memory of the first embodiment in more detail. As described in the description of the first embodiment, in the serial access memory of the first embodiment, the memory column group 12 is composed of four memory columns. here,
15 to 18, the memory columns in the first bank are represented by Ca4i + 1, Ca4i + 2, C4ai + 3, Ca4i + 4, and the memory columns in the second bank are Cb4i + 1, Cb4i + 2, C4b.
It is expressed as i + 3, Cb4i + 4, (i = 0 to n-1). When the access order for both write access and read access starts from Ca1 (it may start from Ca1 for simplicity, here we will start from Ca1), Ca1, Ca5, Ca9 ... C
a4n-3, Cb1, Cb5, Cb9 ... Cb4n-3, Ca2, Ca6, Ca10 ... Ca4n-2,
Cb2, Cb6, Cb10 ... Cb4n-2, Ca3, Ca7, Ca11 ... Ca4n-1, Cb3,
Cb7, Cb11 ... Cb4n-1, Ca4, Ca8, Ca12 .. .Ca4n, Cb4, Cb8, Cb
12 ... Cb4n, will be accessed in that order. The operation will be described in detail below step by step. As shown in FIG. 15, the serial access memory according to the first embodiment has a first memory bank 61 and a second memory bank 62. First
In the memory bank 61 of the write Y decoder 6
3a, write registers T1 to Tn, read Y decoder 64a, read registers S1 to Sn, and X decoder 22a.
And memory columns Ca1 to Ca4n. In the second memory bank 62, the write Y decoder 63b,
It has write registers Tn + 1 to T2n, a read Y decoder 64b, read registers Sn + 1 to S2n, an X decoder 22b and memory columns Cb1 to Cb4n.
Further, as a circuit common to the first and second banks, an input circuit 20, an output circuit 21, a write Y address generation circuit 65 for generating a write Y address, and a read Y address generation for generating a read Y address. The serial access memory of the first embodiment has a circuit 66, a write X address generation circuit 67 for generating a write Y address, and a read X address generation circuit 68 for generating a read X address.

Here, it is assumed that the memory address at which the serial write starts is the address in the memory column Ca1 designated by the word line WLai, and the memory address at which the serial read starts is the memory designated by the word line WLaj. Assume that the address is in column Ca4. Serial input data indicated by a series of continuous black circles is input to the write data bus via the input circuit 20 in synchronization with the write clock WCLK. Light Y decoder 63a
Outputs W1, W2. ． ． Wn sequentially becomes high level so that the write registers T1, T2. ． ． Light on Tn
Serial data on the data bus is sequentially written. During this time, the word line WLaj rises, and the information in the plurality of memory cells connected to the word line WLaj is amplified by the corresponding sense amplifiers and is fixed on the bit line pair to which the sense amplifiers are connected. Then, the memory columns Ca4, Ca8 ... Ca4n are read by the read registers S1, S2. ． ．
Each is selectively transferred to Sn. At the same time, the outputs R1, R2. ． ． When Rn goes high, the read registers S1, S2. ． ． Sn
The information transferred to S1, S2. ． ． An output circuit 21 via the read data buses RD and RD / in the order of Sn.
Further, it is serially output in synchronization with the read clock RCLK as indicated by a series of continuous white circles. Before the information transferred to the read register Sn is output, the second
The word line WLbj of the bank rises, and the information in the plurality of memory cells connected to the word line WLbj is amplified by the corresponding sense amplifiers, and is determined on the bit line pair to which the sense amplifiers are connected. Thereafter, the information on the memory columns Cb4, Cb8 ... Cb4n is read by the read register Sn + by the switch (the switch SW4 which is opened / closed by the read selection transfer signal described in the first embodiment).
1, Sn + 2. ． ． It is selectively transferred to S2n.
By this transfer, the read register Sn + explained in FIG.
1, Sn + 2. ． ． Read serial read from S2n
Register S1, S2. ． ． After the serial read from Sn, the read clock RCLK can be performed without interruption.

The operation following the above operation will be described with reference to FIG. Continuing, write clock WCL
In synchronism with K, serial input data indicated by a series of continuous black circles is input to the write data bus via the input circuit 20. At this time, the output W of the write Y decoder 63b
n + 1, Wn + 2. ． ． W2n sequentially becomes high level, whereby write registers Tn + 1, Tn + 2. ． ． It is written in the order of T2n. This write register Tn + 1, Tn +
2. ． ． While writing to T2n, the word line WLai of the first bank rises. After that, the write registers T1, T2. ． ． The information written in Tn is transferred to the memory columns Ca1, Ca5 ... Ca4n-3 selected by the switch (the switch SW2 which is opened / closed by the read selection transfer signal described in the first embodiment). , Their memory columns and word lines WLai
Is written to the memory cell connected to. While this write access is being performed, read registers Sn + 1, S
n + 2. ． ． The information selectively transferred to S2n is read from the output circuit 20 via the read data buses RD and RD /.
The serial data indicated by a series of continuous white circles is output in synchronization with the clock signal RCLK. Read register S
Before the information transferred to 2n is output, the word line WL which has risen in the first bank described in FIG.
The word line WLaj + 1, which is the X address of aj incremented by 1, rises. This word line WLaj +
The information in the plurality of memory cells connected to 1 is amplified by the corresponding sense amplifier, and is fixed on the bit line pair to which the sense amplifier is connected. afterwards,
Memory column, Ca1, Ca5 ... Ca4n by switch SW4
-3 is read registers S1, S2. ． ． Each is selectively transferred to Sn. By the transfer performed in advance, the read registers S1, S2. ． ． S
The serial read from n is the read register Sn + 1,
Sn + 2. ． ． After serial read from S2n, read
This can be done without interruption to the clock RCLK.

The operation following the above operation will be described with reference to FIG. The serial input data indicated by a series of continuous black circles is input to the write data buses WD and WD / via the input circuit 20 in synchronization with the write clock WCLK. The output signal W1 of the write Y decoder 63a,
W2. ． ． Wn sequentially becomes high level, whereby the input data is written to the write registers T1, T2. ． ． Sequentially written in Tn. The data is write registers T1 and T
2. ． ． While being written to Tn, output signals R1, R2. ． ． When Rn becomes high level, the read registers S1, S2. ． ． Sn
Information transferred to the read data bus R in that order.
Read clock R from output circuit 21 via D and RD /
It is output as serial data as indicated by a series of continuous white circles in synchronization with CLK. Read register Sn
The word line WLbj + 1 of the second bank rises before the information transferred to the second bank is output. Information in the plurality of memory cells connected to the word line WLbj + 1 is amplified by the corresponding sense amplifiers,
Determined on the bit line pair to which the sense amplifier connects. After that, the memory columns Cb1 and Cb are switched by the switch SW4.
Information on b5 ... Cb4n-3 is read registers Sn + 1, Sn +
2. ． ． It is selectively transferred to S2n. Due to the transfer performed in advance, the read registers Sn + 1, Sn + 2. ． ． The serial read from S2n is transferred to read registers S1, S2. ． ． After the serial read from Sn, the write clock signal RCLK can be continuously applied.

The operation following the above operation will be described with reference to FIG. Next, write clock signal W
Serial input data indicated by a series of continuous black circles is input to the write data buses RD and RD / via the input circuit 20 in synchronization with CLK. Output signals Wn + 1, Wn + 2. ． ． The write registers Tn + 1, Tn + 2. ． ． T2n
Are sequentially written to. This write register Tn + 1,
Tn + 2. ． ． While writing to T2n, the word selected by the X address incremented by 1 to the X address of the previous word line of the first bank 61.
Drain WLai + 1 rises. After that, the write registers T1, T2. ． ． The information written in Tn is stored in the memory column Ca2, which is selected by the switch SW2.
The data is transferred to Ca6 ... Ca4n-2 and written in the memory cells connected to the word line WLai + 1 in those memory columns. While the above write access is being performed, the read registers Sn + 1, Sn + 2. ． ． S2
The information that has been selectively transferred to n is read data bus R
The data is output from the output circuit 21 via D and RD / in synchronization with the read clock signal RCLK as serial data indicated by a series of continuous white circles. Read register S2n
X of the word line WLaj + 1 previously raised in the first bank 61 before the information transferred to the first bank 61 is output.
Word line WLaj with the address incremented by 1.
+2 rises. And this word line WLaj +
The information in the plurality of memory cells connected to 2 is amplified by the corresponding sense amplifier and is fixed on the bit line pair to which the sense amplifier is connected. After that, the information in the memory columns Ca2, Ca6 ... Ca4n-2 is read by the switch SW4, and the read registers S1, S2. ． ． Each is selectively transferred to Sn. By the transfer performed in advance, the read registers S1, S2. ． ． Serial serial from Sn
Read registers Sn + 1, Sn + 2. ． ． After the serial read from S2n, the read clock signal RCLK can be continuously applied.

The sequence of the write transfer operation and read transfer operation in the serial access memory of the present invention described above will be described with reference to FIGS. 19 and 20. FIG. 19 is a schematic diagram for explaining the write transfer operation in the serial access memory of the present invention. In the write transfer operation, first, the write registers T1, T2. ． ．
Serial data is sequentially written in Tn. After that, (a)
, The write registers T1, T2. ． ． Tn to the memory columns C1, C5. ． ． C4m
-Connect to 3 respectively. And the write register T1,
T2. ． ． The data transferred to Tn are stored in memory columns C1, C5. ． ． Write to the memory cell connected to a specific word line of C4m-3. During this period, the continuous serial data is the write registers Tn + 1, Tn + 2. ． ． It is sequentially written in T2n. Next, as shown in (b), the write registers Tn + 1, Tn + 2. ． ． T2n to memory columns C4m + 1, C4m + 5. ． ． Connect to C8m-3 respectively. The write registers Tn + 1, Tn + 2. ． ．
The data transferred to T2n are stored in the memory column C4.
m + 1, C4m + 5. ． ． Specific work of C8m-3
Write to the memory cell connected to the drain. During this time,
The continuous serial data is written in the write registers T1, T2. ． ． Sequentially written in Tn. After that, as shown in (c), the write registers T1, T
2. ． ． Tn is the memory column C2 of the first bank 61,
C6. ． ． Connect to C4m-2 respectively. Then, the write registers T1, T2. ． ． The data transferred to Tn are stored in memory columns C2, C6. ． ． The word line specified in (a) of C4m-2 is written to the memory cell connected to the word line incremented by one. During this time, the continuous serial data is stored in the second bank 6
2 write registers Tn + 1, Tn + 2. ． ． It is sequentially written in T2n. Further, as shown in (d), the write registers Tn + 1, Tn + 2. ． ． T2
n are memory columns C4m + 2, C4m + 6. ． ． C8m-
Connect to 2 respectively. And write register Tn +
1, Tn + 2. ． ． The data transferred to T2n are stored in memory columns C4m + 2, C4m + 6. ． ． C8m-2
The word line specified in (b) is written in the memory cell connected to the incremented word line. During this period, the continuous serial data is written in the write registers T1, T2. ． ． Sequentially written in Tn.

Next, as shown in (e), write registers T1, T2. ． ． Tn to the memory columns C3, C7. ． ． Connect to C4m-1 respectively. Then, the write registers T1, T2. ． ． The data transferred to Tn are stored in memory columns C3, C7. ． ． C4m
Write the word line specified in (c) of -1 to the memory cell connected to the word line incremented by one. During this period, the continuous serial data is the write registers Tn + 1, Tn + 2. ． ． T2
are sequentially written to n. Further, as shown in (f), the write registers Tn + 1 and Tn + of the second bank 62.
2. ． ． T2n is a memory column C4m + 3, C4m +
7. ． ． Connect to C8m-1 respectively. The write registers Tn + 1, Tn + 2. ． ． The data transferred to T2n are stored in memory columns C4m + 3 and C4m +, respectively.
7. ． ． The word line specified in (d) of C8m-1 is written in the memory cell connected to the word line incremented by one. During this period, the continuous serial data is written in the write registers T1 and T1 of the first bank 61.
2. ． ． Sequentially written in Tn. After this, as shown in (g), the write registers T1, T2. ． ． Tn to the memory columns C4, C8. ． ． Connect to C4m respectively. And the write registers T1 and T
2. ． ． The data transferred to Tn are stored in memory columns C4, C8. ． ． The word line specified in (e) of C4m is written in the memory cell connected to the word line incremented by one. During this time, the continuous serial data is written in the write register Tn + of the second bank 62.
1, Tn + 2. ． ． It is sequentially written in T2n. Further, as shown in (h), the write registers Tn + 1, Tn + 2. ． ． T2n to memory column C4m
+4, C4m + 8. ． ． Connect to C8m respectively. The write registers Tn + 1, Tn + 2. ． ． The data transferred to T2n are stored in memory columns C4m + 4 and C4, respectively.
m + 8. ． ． The word line specified in (f) of C8m is written in the memory cell connected to the word line incremented by one. During this period, the continuous serial data is written in the write registers T1 and T1 of the first bank 61.
2. ． ． Sequentially written in Tn. After that, the connection relationship between the write register and the memory column returns to FIG. 19A, and the word line is serially written for the addresses sequentially incremented after (h).

FIG. 20 is a schematic diagram for explaining the read transfer operation in the serial access memory of the present invention. In the read transfer operation, as shown in (a), the first bank 6
1 memory columns C1, C5. ． ． C4m-3 and read registers S1, S2. ． ． Sn and each are connected.
The memory columns C1, C5. ． ． The data of the memory cells connected to a specific word line of C4m-3 are read out, and read registers S1, S2. ． ．
Transfer to Sn. Next, as shown in (b), the memory columns C4m + 1, C4m + 5. ． ． C8
m-3 and read registers Sn, Sn + 1. ． ． S2n are connected respectively. And memory columns C4m + 1, C
4m + 5. ． ． The data of the memory cells connected to a specific word line of C8m-3 are read out, and read registers Sn, Sn + 1. ． ． Transfer to S2n.
In the meantime, in the first bank 61, the read register S
1, S2. ． ． The data transferred to Sn are sequentially output to the read data bus and output as continuous serial data. Thereafter, as shown in (c), the memory columns C2, C6. ． ． C4m-2 and read registers S1, S2. ． ． Sn and each are connected. The memory columns C2, C6. ． ． The data of the memory cells connected to the word line obtained by incrementing the word line specified by (a) of C4m-2 by one is read out, and the read registers S1, S2. ． ． Transfer to Sn. In the meantime, in the second bank 62, the read registers Sn + 1, Sn + 2. ． ． The data transferred to S2n are sequentially output to the read data bus and output as continuous serial data. Further, as shown in (d),
Memory columns C4m + 2, C4m + of the second bank 62
6. ． ． C8m-2 and read registers Sn + 1, Sn +
2. ． ． S2n are connected respectively. The memory columns C4m + 2, C4m + 6. ． ． The data of the memory cells connected to the word line obtained by incrementing the word line specified by (b) of C8m-2 by one is read out, and the read registers Sn + 1, Sn + 2. ． ．
Transfer to S2n. In the meantime, in the first bank 61, the read registers S1, S2. ． ． The data transferred to Sn are sequentially output to the read data bus and output as continuous serial data.

Thereafter, as shown in (e), the memory columns C3, C7. ． ． C4m-1 and Lee
Register S1, S2. ． ． Sn and each are connected. Then, the memory columns C3, C7. ． ． The data of the memory cells connected to the word line obtained by incrementing the word line specified by (c) of C4m-1 by 1 is read out, and the read registers S1, S2. ． ．
Transfer to Sn. During this time, in the second bank 62,
Read registers Sn + 1, Sn + 2. ． ． The data transferred to S2n are sequentially output to the read data bus and output as continuous serial data. Further, as shown in (f), the memory columns C4m + 3, C of the second bank 62 are
4m + 7. ． ． C8m-1 and read registers Sn + 1, S
n + 2. ． ． S2n are connected respectively. Then, memory columns C4m + 3, C4m + 7. ． ． The data of the memory cells connected to the word line obtained by incrementing the word line specified by (d) in C8m-1 is read out, and read registers Sn + 1 and Sn +, respectively.
2. ． ． Transfer to S2n. In the meantime, in the first bank 61, the read registers S1, S2. ． ． The data transferred to Sn are sequentially output to the read data bus and output as continuous serial data. Further, as shown in (g), the memory columns C4, C of the first bank 61 are
8. ． ． C4m and read registers S1, S2. ． ． Sn
And are connected respectively. And the memory columns C4, C
8. ． ． The data of the memory cells connected to the word line obtained by incrementing the word line specified by (e) of C4m by one is read out, and read register S1, S2. ． ． Transfer to Sn. In the meantime, in the second bank 62, the read registers Sn + 1 and Sn +
2. ． ． The data transferred to S2n are sequentially output to the read data bus and output as continuous serial data. Further, as shown in (h), memory columns C4m + 4, C4m + 8. ． ． C8m and read registers Sn + 1, Sn + 2. ． ． S2n are connected respectively. And memory columns C4m + 4, C4m +
8. ． ． The data of the memory cells connected to the word line obtained by incrementing the word line specified by (f) of C8m by one is read out, and read out from the read registers Sn + 1, Sn + 2. ． ． Transfer to S2n. During this time, the first
In the bank 61 of the read registers S1 and S
2. ． ． The data transferred to Sn are sequentially output to the read data bus and output as continuous serial data.
After this, the connection relationship between the read register and the memory column returns to FIG. 20 (a), and the word line is serially read for addresses sequentially incremented after (h).
Is done.

[0037]

As described in detail above, according to the serial access memory of the present invention, the number of registers for a memory column is reduced, and it is possible to make a register pattern with a margin. As a result, the chip size can be reduced with the conventional process, and the advantages of process development cost saving and chip size reduction can be obtained.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram of a serial access memory according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation timing of the serial memory of the first embodiment.

FIG. 3 is a circuit diagram showing a write address generation circuit.

FIG. 4 is a timing chart showing the operation of the write address generation circuit.

FIG. 5 is a circuit diagram showing a read address generation circuit.

FIG. 6 is a timing chart showing the operation of the read address generation circuit.

FIG. 7 is a partial circuit diagram of a serial access memory according to a second embodiment.

FIG. 8 is a partial circuit diagram of a serial access memory according to a third embodiment of the present invention.

FIG. 9 is a partial circuit diagram of a serial access memory according to a fourth embodiment of the present invention.

FIG. 10 is a partial circuit of a serial access memory according to a fourth embodiment of the present invention.

FIG. 11 is a partial circuit diagram of a serial access memory according to a fifth embodiment of the present invention.

FIG. 12 is a partial circuit diagram of a serial access memory according to a fifth embodiment of the present invention.

FIG. 13 is a partial circuit diagram of a serial access memory which is a modification of the fifth embodiment.

FIG. 14 is a partial circuit diagram of a serial access memory which is a modification of the fifth embodiment.

FIG. 15 is a schematic diagram showing the operation of the serial access memory of the first embodiment in more detail.

FIG. 16 is a schematic diagram showing the operation of the serial access memory of the first embodiment in more detail.

FIG. 17 is a schematic diagram showing the operation of the serial access memory of the first embodiment in more detail.

FIG. 18 is a schematic diagram showing the operation of the serial access memory of the first embodiment in more detail.

FIG. 19 is a schematic diagram illustrating a write transfer operation in the serial access memory according to the present invention.

FIG. 20 is a schematic diagram illustrating a read transfer operation in the serial access memory of the present invention.

[Explanation of symbols]

10 memory columns 11 memory cells 22 X decoder 24 Memory-Control signal generation circuit 25 Arbiter BL1-m, BL1-m / bit line WL1-n word line SA1-m sense amplifier T1, T2 write data register WD, WD / light data bus S1, S2 read data register RD, RD / read data bus

Claims (6)

[Claims] 1. A plurality of write data registers, which are connected to a write data bus to which input data is transferred and which temporarily store the data, and a plurality of memory cells. In a serial access memory having first and second memory banks each of which is formed of a memory column to which one of a predetermined number is selectively connected to one data register, data on the write data bus is stored. The write data register of the first memory bank is input, the write data register of the second memory bank is connected to the first memory column of a predetermined number, and the data of this write data register is connected. Writing to a predetermined memory cell of the memory column, and inputting the data on the write data bus to the write data register of the second memory bank. At the same time, the step of connecting the write data register of the first memory bank to the first memory column of the predetermined number and writing the data of this write data register to the predetermined memory cell of the connected memory column, , The data on the write data bus is input to the write data register of the first memory bank, and the write data register of the second memory bank is connected to the second memory column of the predetermined number. A step of writing the data of the write data register to a predetermined memory cell of the connected memory column, and inputting the data on the write data bus to the write data register of the second memory bank and the first memory The write data register of the bank is connected to the second memory column of the predetermined number, and the data of this write data register is connected. Writing data into a predetermined memory cell of a connected memory column, and a write transfer method of a serial access memory. 2. The write transfer method of a serial access memory according to claim 1, wherein after a predetermined number of successive writing steps have been performed, the first step is returned to and the subsequent steps are sequentially performed. 3. A read data bus to which data to be output is transferred, and a plurality of read data registers for temporarily storing this data, and a plurality of memory cells, In the serial access memory having the first and second memory banks, each of which is composed of a memory column to which one of a predetermined number of the read data registers is selectively connected. The first memory column of the predetermined number of memory banks is connected to the read data register, and the data stored in the connected memory column is output to the read data register, Outputting the data stored in the read data register of the second memory bank to the read data bus; and reading the first memory column of the predetermined number of the second memory bank. Data Regis To output the data stored in the connected memory column to the read data register and read the data stored in the read data register of the first memory bank. The step of outputting to the data bus and connecting the second memory column of the predetermined number of the first memory bank to the read data register, and storing the data stored in the connected memory column. A step of outputting the data stored in the read data register of the second memory bank to the read data bus while outputting the read data register to the read data register; and a predetermined number of second memory banks. The second memory column among them is connected to the read data register, the data stored in the connected memory column is output to the read data register, and the data in the first memory bank is read. -Data A step of outputting the data stored in the register to the read data bus; and
Transfer method. 4. The read transfer method of a serial access memory according to claim 3, wherein after the predetermined number of successive writing steps have been performed, the first step is returned to and the subsequent steps are sequentially performed. 5. A plurality of write data registers, which are connected to a write data bus to which input data is transferred, temporarily store the data, and a read to which the data to be output is transferred. It has a plurality of read data registers connected to a data bus and temporarily storing this data, and a plurality of memory cells. One for each of the read data register and the write register. A first column composed of a memory column to which one of a predetermined number is selectively connected;
And in the serial access memory having the second memory bank, the data on the write data bus is input to the write data register of the first memory bank, and the first of the predetermined number of the first memory bank is input. The memory column is connected to the read data register, the data stored in the connected memory column is output to the read data register, and the write data register of the second memory bank is predetermined. Connected to the first memory column of the memory cells, write the data of this write data register to a predetermined memory cell of the connected memory column, and save it in the read data register of the second memory bank. The step of outputting the read data to the read data bus, and inputting the data on the write data bus to the write data register of the second memory bank, The first memory column of the predetermined number of the memory banks is connected to the read data register, and the data stored in the connected memory column is output to the read data register. At the same time, the write data register of the first memory bank is connected to the first memory column of the predetermined number, and the data of this write data register is written to the predetermined memory cell of the connected memory column, Outputting the data stored in the read data register of the first memory bank to the read data bus, and inputting the data on the write data bus to the write data register of the first memory bank, The second memory column of the predetermined number in the first memory bank is connected to the read data register, and the data stored in the connected memory column is read. The write data register of the second memory bank is connected to the second memory column of the predetermined number while outputting to the register, and the data of the write data register is connected to the predetermined memory cell of the connected memory column. And writing the data stored in the read data register of the second memory bank to the read data bus, and writing the data on the write data bus to the write data register of the second memory bank. , The second memory column of the predetermined number in the second memory bank is connected to the read data register, and the data stored in the connected memory column is read. In addition to outputting to the data register, the write data register of the first memory bank is connected to the second memory column of the predetermined number, and the write data register of this write data register is connected. Writing data into a predetermined memory cell of the connected memory column and outputting the data stored in the read data register of the first memory bank to the read data bus. Serial access memory data
Data transfer method. 6. The serial access memory device according to claim 5, wherein after the two consecutive steps have been performed up to a predetermined number of times, the process returns to the first step and the subsequent steps are sequentially performed.
Data transfer method.