JP2003174102A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge the surface area of a capacity storage electrode in order to increase the capacity of the capacitor of a semiconductor device for memory that is minute and highly integrated. <P>SOLUTION: Two or more layers of silicon oxide films having different impurity concentrations and fluorine contents are stacked as the spare layer of a capacity storage electrode 11 that is formed to a semiconductor device. An opening that is the predetermined zone of the spare layer removed selectively is provided to get etching treatment. The shape of bellows is formed on the sidewall surface of the opening due to the difference in the etching rate of the spare layer. After a conductive film is deposited on the sidewall surface of the opening to form the capacity storage electrode 11, the spare layer is removed. Moreover, a capacity insulator film 12 and a capacity counter-electrode 13 are formed to the capacity storage electrode 11. The surface of the cylindrical capacity storage electrode 11 can be formed into bellows without performing high-temperature heat treatment, and the surface area is enlarged to increase the capacity of the capacitor. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which the surface area of a charge storage electrode is increased in order to improve the storage capacity of a charge storage capacitor in a semiconductor device for storage or having a storage portion. is there.

[0002]

2. Description of the Related Art Recently, in the field of information equipment, a semiconductor device DRAM (an occasional write / read memory requiring a memory holding operation) has been widely used. This DRAM is
Information is stored depending on the presence or absence of charge retention by the capacitor, and the charge accumulated in the capacitor is connected to the bit line through the switch of the transistor. It is amplified and read out as data.

However, since the electric charge accumulated in the capacitor decreases with the passage of time, it is necessary for the DRAM to perform a refresh operation of periodically reading the electric charge of the capacitor and rewriting the electric charge. Since there are problems such as data loss due to malfunction of the refresh operation itself and increase in power consumed by the refresh operation, it is necessary to reduce the number of refresh operations that are regularly performed.
It is effective for improving the reliability of AM. These can be realized by increasing the capacitance of the capacitor. However, due to the high-density integration that accompanies an increase in the storage capacity of the memory, the semiconductor element is miniaturized, the occupied area of the capacitor is reduced, and it is becoming difficult to increase the capacitance of the capacitor.

As one of the techniques for solving this problem, a technique for enlarging the surface area of the capacitor per unit area can be considered. For example, conventionally, a technique of increasing the surface area of the capacitance storage electrode by making the structure of the capacitance storage electrode forming the capacitor of the memory cell into a crown type or fin type structure has been used. Furthermore, in recent years, the HSG method (Hemispherical Grain method) is used to increase the surface area by coating the surface of a capacitance storage electrode made of a silicon-based material with fine particles made of polycrystalline silicon (particle diameter is about 0.05 μm).
Has been put to practical use.

However, when this technique is used, it is necessary to prevent the problem that the short channel effect becomes remarkable and the transistor characteristics become unstable due to the heat treatment for forming the unevenness on the surface of the capacitance storage electrode, and the increase in the junction resistance. There is a possibility that a problem may occur in forming a shallow junction of 0.2 μm or less.

Furthermore, in order to apply a high dielectric constant insulating film such as a tantalum oxide film or BST, it is necessary to use a metal material such as tungsten or titanium as the electrode material of the capacitance storage electrode. This technology is applicable only when the material is silicon, and cannot be applied to the capacitance storage electrode made of a metal material.

Therefore, the authors of the present invention, Japanese Patent Laid-Open No. 2000-1010.
It has been proposed to increase the surface area of the capacitance storage electrode by the method as disclosed in Japanese Patent Laid-Open No. 37.

FIG. 10 to FIG. 17 show sectional structural process diagrams in the above-described conventional embodiment of the invention.

First, as shown in FIG.
Silicon oxide film 15 containing a low concentration of boron and phosphorus on top
And a silicon oxide film 16 containing boron and phosphorus at a high concentration are alternately deposited by the CVD method. The impurity concentration difference between the silicon oxide film 15 and the silicon oxide film 16 is in the range of 10 to 30%, preferably about 15%. Thereafter, similarly, the steps of alternately depositing the silicon oxide film 15 and the silicon oxide film 16 are repeated to form a laminated film. Next, as shown in FIG. 11, patterning is performed with a resist pattern 8 for forming a capacitor portion, and a capacitor forming portion 9 is formed by dry etching or the like using the resist pattern 8 as a mask. FIG. 12 shows a state where the unnecessary resist pattern used in FIG. 11 is selectively removed.
FIG. 13 is a cross-sectional view after treating the side wall of the opening with an aqueous solution containing hydrofluoric acid (hereinafter referred to as hydrofluoric acid), an aqueous solution containing hydrogen peroxide and ammonia, or vapor phase hydrofluoric acid. The silicon oxide film 15 containing low concentration of boron and phosphorus and the silicon oxide film 16 containing high concentration of boron and phosphorus have different etching rates. Therefore, unevenness is formed on the side wall surface 10 of the capacitance forming portion 9, and the side wall portion of the capacitance storage electrode can be formed into a bellows shape 29. In FIG. 14, a conductive film 11 made of polycrystalline silicon for a capacitance storage electrode is deposited with a film thickness of 50 nm.
FIG. 15 shows a stage in which only the conductive film 11 on the surface of the silicon oxide film 16 is selectively removed by the chemical mechanical polishing method (CMP method). In FIG. 16, for example, the laminated film composed of the silicon oxide films 15 and 16 is sequentially and selectively removed with an aqueous solution of hydrofluoric acid, and the conductive film 11 is used as a capacitance storage electrode. In FIG. 17, a capacitance insulating film 12 is provided on the capacitance storage electrode 11, and a conductive film 13 for a capacitance counter electrode is further provided thereon.
Is just completed. As described above,
The capacitor of the charge storage capacity of the memory cell portion is completed.

[0010]

However, in the above-mentioned conventional method, the base directly contacting the capacitive electrode forming portion is compatible with hydrofluoric acid aqueous solution, aqueous solution containing hydrogen peroxide and ammonia, or vapor phase hydrofluoric acid. It could not be applied in the case of a soluble material, for example a metal layer of aluminum or tungsten. FIG. 18 is an example of a cross-sectional structure diagram when a conventional method is applied to a structure in which a memory cell is formed in an upper layer of a multilayer wiring. In such a structure, if an attempt is made to directly contact the capacitance storage electrode on the semiconductor substrate, the aspect ratio becomes too high and the conductive film may be imperfectly embedded in the contact portion. Need to contact. However, in the conventional method, as shown in FIG. 18, the metal wiring 14 immediately below the capacitance storage electrode is exposed to the chemical solution and is dissolved / disappeared, so that the metal wiring and the capacitance storage electrode cannot be electrically connected to each other. There is a problem that data write / read failure occurs.

Therefore, the present invention is directed to solving the above-mentioned problems of the prior art, and has an effective surface area for a memory semiconductor device represented by a fine DRAM of 0.13 μm rule or less. An object of the present invention is to provide a semiconductor device having an expanded capacitance storage electrode and a manufacturing method thereof.

[0012]

In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises a charge storage electrode, a counter electrode of the charge storage electrode, and a charge storage electrode on a semiconductor substrate. It is characterized in that it has a capacitor composed of a working electrode and a dielectric film provided between the counter electrode, and the surface of the charge storage electrode is formed into a bellows shape.

Specifically, a step of forming at least two layers of silicon oxide films having different fluorine contents on a semiconductor substrate to form a laminated film, and a predetermined region of the laminated film is selectively removed to form an opening. A step, a step of treating the opening portion of the laminated film in a water vapor atmosphere to form a side wall surface of the opening into a bellows shape, and a step of depositing a conductive film to be a charge storage electrode on the bellows side wall of the opening, A step of removing the laminated film after forming the charge storage electrode of the conductive film, a step of forming a dielectric film on the charge storage electrode, and a step of forming a counter electrode facing the charge storage electrode on the dielectric film. Consists of.

According to the manufacturing method of the present invention, fluorine contained in the silicon oxide film reacts with water vapor to generate hydrofluoric acid, and the silicon oxide film is etched in a self-aligned manner. No direct exposure to hydrofluoric acid. In addition, since the step of forming the side wall surface of the charge storage electrode into a bellows shape can be performed without performing high-temperature heat treatment, the surface area of each capacitor can be effectively increased, and the capacitor surface storage electrode having a large surface area can be used. The capacity can be increased. Furthermore, since a conductive film to be a charge storage electrode is deposited on the side wall of the opening provided in the laminated film, even if the material of the metal or its compound corresponding to the high dielectric constant film or the ferroelectric film is almost uniform. The thickness of the charge storage electrode can be varied and the surface of the charge storage electrode can be formed into a bellows shape.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 8 show sectional structure process diagrams in the embodiment of the present invention.

The manufacturing process will be described in detail below with reference to the drawings.

First, as shown in FIG. 1, a first insulating film 2 made of a silicon oxide film containing 5% by weight of fluorine is formed on a semiconductor substrate 1 by a CVD method, and the first insulating film 2 is formed.
A second insulating film 3 containing fluorine in a weight ratio of 2% was formed as a silicon oxide film having a fluorine content different from that of the insulating film 2. Thereafter, the third insulating film 4, the fourth insulating film 4
The insulating film 5, the fifth insulating film 6, and the sixth insulating film 7 were laminated. Next, as shown in FIG. 2, a resist pattern 8 for forming a capacitance portion is formed.
Then, the capacitance forming portion 9 is formed by dry etching or the like using the resist pattern 8 as a mask. FIG. 3 is a view in which the unnecessary resist pattern used in FIG. 2 is selectively removed. In FIG. 4, for example, the sample is treated in a steam atmosphere at 80 ° C. for 1 minute, washed with water, and dried.

FIG. 5 shows a case where a conductive film 11 made of polycrystalline silicon for a capacitance storage electrode is deposited to a film thickness of 50 nm. FIG. 6 shows a stage in which only the conductive film 11 on the surface of the insulating film 7 is selectively removed by the chemical mechanical polishing method (CMP method). FIG. 7 shows, for example, that the
The insulating film 7 to the first insulating film 2 are selectively removed sequentially,
This is where the conductive film 11 is used as a capacitance storage electrode. 8 is completed by depositing a capacitance insulating film 12 on the capacitance storage electrode 11 and further depositing a conductive film 13 for a capacitance counter electrode thereon.

The mechanism by which the side wall surface 10 has a bellows shape in the step shown in FIG. 4 will be described with reference to FIG. For example, although the silicon oxide film 2 contains fluorine,
This is mainly free fluorine that is not directly bonded to silicon or oxygen, or fluorine that is bonded to silicon. When the silicon oxide film 2 is exposed to a water vapor atmosphere, the above-mentioned fluorine reacts with water vapor to generate hydrofluoric acid (FIG. 9).
(A)). Since hydrofluoric acid is generated in the silicon oxide film 2, the hydrofluoric acid and the oxide film react next, and etching proceeds in a self-aligned manner. Since the concentration of the generated hydrofluoric acid is determined by the content ratio of fluorine in the silicon oxide film, the etching rate of the silicon oxide film is high in the portion where the fluorine content is high and the silicon oxide film is in the portion where the content of fluorine is low. The etching rate of the film becomes slow (FIG. 9B). In the step of stacking the silicon oxide film containing fluorine, if the fluorine concentration in the film changes stepwise, the shape after etching will be stepwise as shown in FIG. 9B. However, in reality, the heat treatment applied during the process causes diffusion of free fluorine, and the fluorine concentration continuously changes at the interface of the laminated films (FIG. 9C). Therefore, in actuality, the side wall surface 10 of the capacitance forming portion 9 formed on the insulating film formed by laminating silicon oxide films having different fluorine contents does not have a stepped shape but becomes a bellows shape, and is used for the next capacitance storage electrode. No step breakage occurs even when the conductive film is deposited.

According to the method of the present invention, hydrofluoric acid is generated and etched in a self-aligned manner by performing steam treatment, so that the bottom surface of the opening is not directly exposed to hydrofluoric acid. Even if a metal layer is used for the base, the base is not easily etched. In particular, the first insulating film 2
When a silicon oxide film having a fluorine content of 0% is used, no hydrofluoric acid is generated in the vicinity of the underlayer, and there is no risk of dissolution or disappearance of the underlying metal wiring.

According to the embodiment of the present invention, the conductive film for the capacitance storage electrode is made of polycrystalline silicon, and the sixth insulating film to the first insulating film are selectively removed sequentially with an aqueous solution of hydrofluoric acid. However, the conductive film is a metal film such as tungsten, or a silicide film or a metal oxide, and a laminated film made of a silicon oxide film containing fluorine is selected for the metal film, the silicide film, or the metal oxide. Which has a property, for example, isotropic dry etching may be performed using a CF-based gas to selectively remove it.

[0022]

As described above, according to the present invention,
To provide a semiconductor device capable of increasing the surface area of a capacitance storage electrode in order to obtain a capacitor of a memory cell, and specifically, by forming the surface shape of the capacitance storage electrode into a bellows structure by using self-aligned etching, The surface area of the electrode can be increased, and the capacity of the capacitor can be increased.

Further, since metal wiring can be used as a base material of the capacitance storage electrode, and for example, a memory cell can be easily formed on a multilayer wiring, it is possible to increase the degree of freedom in the layout of the memory cell. .

Further, according to the present invention, in order to increase the surface area of the capacitance storage electrode, heat treatment at high temperature as in the HSG method is not required, and the short channel effect which is a problem in the conventional HSG technology can be obtained. It is possible to avoid the problem associated with the formation of an extremely shallow shallow junction of 0.2 μm or less, which is necessary for preventing the occurrence and increase of the junction resistance.

Further, the capacitor storage electrode is also applied to a metal or a metal silicide material that is highly likely to be used as an electrode material corresponding to a high dielectric constant film or a ferroelectric film as a capacitive insulating film of future fine memory cells. The surface area can be increased, and it can be a useful method for manufacturing a VLSI having a 0.13 μm rule or less.

Further, according to the present invention, a refresh operation which is regularly performed for a VLSI element such as a DRAM having a rule of 0.13 μm or less from the viewpoints of reliability improvement of data reading, prevention of soft error and low power consumption. There is an effect that the number of times can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional structure process chart showing an embodiment of the present invention.

FIG. 2 is a sectional structure process chart showing an embodiment of the present invention.

FIG. 3 is a sectional structure process drawing showing an embodiment of the present invention.

FIG. 4 is a sectional structure process chart showing an embodiment of the present invention.

FIG. 5 is a sectional structural process diagram showing an embodiment of the present invention.

FIG. 6 is a sectional structure process diagram showing an embodiment of the present invention.

FIG. 7 is a sectional structure process diagram showing an embodiment of the present invention.

FIG. 8 is a sectional structural process diagram showing an embodiment of the present invention.

FIG. 9 is an explanatory diagram of a concavo-convex forming mechanism on a side wall surface according to the embodiment of the present invention.

FIG. 10 is a sectional structure process diagram showing a conventional embodiment.

FIG. 11 is a sectional structure process diagram showing a conventional embodiment.

FIG. 12 is a sectional structure process diagram showing a conventional form.

FIG. 13 is a sectional structure process diagram showing a conventional form.

FIG. 14 is a sectional structure process diagram showing a conventional embodiment.

FIG. 15 is a sectional structure process chart showing a conventional embodiment.

FIG. 16 is a sectional structure process diagram showing a conventional form.

FIG. 17 is a sectional structural process diagram showing a conventional form.

FIG. 18 is a cross-sectional structure diagram when a conventional technique is applied to a structure in which a memory cell is formed in an upper layer of a multilayer wiring.

[Explanation of symbols]

1 Semiconductor substrate 2 First insulating film 3 Second insulating film 4 Third insulating film 5 Fourth insulating film 6 Fifth insulating film 7 6th insulating film 8 resist pattern 9 Capacity forming part 10 Side wall surface of the capacity forming part 11 Capacitance storage electrode 12 capacitance insulating film 13 Capacitance counter electrode 14 Metal wiring 15 Silicon oxide film containing high concentration of boron and phosphorus 16 Silicon oxide film containing low concentration of boron and phosphorus

Continued front page    (72) Inventor Yuzo Shimizu             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Kenji Imaizumi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Katsuichi Osawa             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5F043 AA38 AA40 BB30 GG04                 5F083 AD29 AD45 AD63 JA32 JA35                       JA36 JA39 JA42 PR03 PR05                       PR06

Claims (3)

[Claims] 1. A step of forming a laminated film by laminating at least two layers of silicon oxide films having different fluorine contents on a semiconductor substrate, and a predetermined region of the laminated film is selectively removed to form an opening. A step of treating the opening of the laminated film containing fluorine in a steam atmosphere, a step of depositing a conductive film to be a charge storage electrode on a sidewall of the opening treated in the steam atmosphere, and the conductive film. Of removing the laminated film after forming the charge storage electrode, forming a dielectric film on the charge storage electrode, and further forming a counter electrode facing the charge storage electrode on the dielectric film. A method of manufacturing a semiconductor device, comprising the steps of: 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the laminated film by laminating the silicon oxide films, a silicon oxide film containing at least fluorine is first deposited. 3. The semiconductor according to claim 1, wherein the charge storage electrode is made of a metal or a compound thereof, and the dielectric film is made of a high dielectric constant film or a ferroelectric film. Device manufacturing method.