JP2003174085A - Dual damascene structure and forming method thereof, and semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dual damascene structure and a forming method thereof wherein no etching stop film is provided, a groove-wiring with a good shape is provided, and no wiring-delay occurs, and to provide a semiconductor device and a manufacturing method thereof. <P>SOLUTION: A first insulating film, an interlayer insulating film consisting of an organic Low-k material, and a second insulating film are formed in this order on a substrate. A via-hole is formed to the upper surface of the substrate by etching and removing these films in one process using halogenated carbon or halogenated hydrocarbon gas. Then, the second insulating film is etched and removed to the upper surface of the interlayer insulating film by using the same halogenated gas, and a wiring-groove is formed by carrying out trench etching of the interlayer insulating film using N<SB>2</SB>, H<SB>2</SB>, NH<SB>3</SB>, or O<SB>2</SB>gas, etc., and a Cu wiring layer is formed to fill this wiring groove. The surface of obtained laminated layers is subjected to surface flattening treatment through CMP to form a Cu wiring film. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual damascene structure, a method for forming the same, a semiconductor device (semiconductor element) and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, due to higher integration and higher speed of LSI in the semiconductor industry, wirings of a semiconductor substrate are becoming finer and multilayered, and the number of interconnections is also increasing. Therefore, the wiring pitch is narrowed, and the performance of the LSI is deteriorated due to the inter-wiring capacitance and the wiring delay. In order to prevent this, it is necessary to use a wiring material having a low resistivity and an interlayer insulating film having a low dielectric constant, and the wiring material has a low resistivity and electromigration (EM) instead of a conventional Al alloy or the like. The use of highly resistant Cu is becoming active. As a Cu film forming technique, there are a sputtering method, a plating method, a CVD method and the like, and a method of depositing and filling Cu in a wiring groove, a via hole, a contact hole and the like has been developed. A damascene process has also been developed in which a wiring groove, a hole, and the like are completely filled, and then a method of performing CMP processing to planarize the substrate surface is repeated.

Further, with the introduction of Cu wiring, research and development have been conducted on the wiring structure, interlayer insulating film, etc., and it is difficult to effectively reduce the wiring delay only by using Cu wiring. , In the semiconductor process,
A low relative dielectric constant oxide film (SiO ₂ film) is used as the interlayer insulating film.

As the damascene process, there are a single damascene method and a dual damascene method, but a dual damascene method for collectively forming a wiring layer and a via hole for connecting a lower layer wiring is promising in terms of a manufacturing method. According to the dual damascene method, after forming a wiring groove for embedding a wiring and a connection hole connecting the upper and lower wirings, a wiring material is embedded in both of them, and excess wiring material overflowing from the wiring groove is removed by CMP processing to form a wiring and This is a technique of simultaneously forming connection hole wiring (so-called plug) formed in the connection hole. An example of this dual damascene structure will be described with reference to FIGS. 1A to 1D which show a process of a conventional forming method in the order of steps.

First, a first insulating film (silicon oxide film) used as a via layer is formed on a substrate on which elements such as transistors are formed and Cu first wirings are formed.
It is formed with a film thickness of about 0 to 1000 nm. A first interlayer insulating film made of an organic Low-k material having a low dielectric constant is formed on the first silicon oxide film, and then a SiN film or a SiON film which functions as an etching stop film at the time of groove etching is formed to have a film thickness of about 30 to 200 nm. Form with a thick thickness. On this stop film, a second interlayer insulating film made of a Low-k material and a second insulating film (silicon oxide film, film thickness: about 100 to 500 nm) used as a wiring interlayer film are sequentially deposited. Then, a photoresist pattern is formed by a normal exposure method, and a via hole is formed by anisotropic etching. After that, the photoresist is peeled and removed, and again,
Form a photoresist pattern by the usual exposure method,
Forming grooves (wiring grooves) 105 by anisotropic etching
(FIG. 1 (A)). In FIG. 1A, 101 is a first interlayer insulating film, 102 is a stop film, 103 is a second interlayer insulating film, 1
Reference numeral 04 represents a second insulating film. When the groove is formed by etching, the layer to be etched must be surely stopped by the stop film 102 at a predetermined position (the upper surface of the stop film 102 in the figure). After forming the groove 105, a barrier metal such as TiN, TaN, or WN is deposited on the inner wall surface and the field portion of the groove by sputtering to form the barrier film 106 (FIG. 1B). Then, a Cu wiring layer 107 is formed by an electroplating method or the like so as to fill this groove. Finally, a surface flattening process is performed on the laminated surface by CMP to scrape off excess Cu wiring material in the field portion which is not embedded in the wiring groove 105 and overflows from the wiring groove, as shown in FIG. A Cu dual damascene structure is formed.

[0006]

In the above prior art, when a low dielectric constant film made of an organic Low-k material is introduced in order to solve the problem of wiring delay, it is used as a stop film when etching the Low-k film. SiN film or S
If a large selection ratio with respect to the iON film can be obtained, the etching shape can be made uniform within the wafer surface by performing overetching after that (FIG. 1A). However, when a SiN film or a SiON film is used as the stop film (intermediate layer), the non-dielectric constant is high (for SiN: ε =
Approximately 7-8, in the case of SiON: ε = approximately 5-6), the inter-wiring capacitance increases due to the fringe effect due to the edge of the adjacent wiring in the fine pitch pattern, and the wiring delay problem in the stacking direction There is a problem that the effect of elimination is drastically reduced. Even if HSQ or an organic-containing silicon oxide film having a low relative dielectric constant is applied as a stop film, there is a problem that it is likely to cause a large signal propagation delay.
Therefore, a dual damascene structure without a stop film as shown in FIG. 2 has been proposed. In FIG. 2, 20
Reference numeral 1 indicates an organic Low-k film, 202 indicates a silicon oxide film, and A indicates an etching stop point. However, in this case, since the etching must be stopped in the middle (point A in FIG. 2), the over-etching method cannot be used for uniform formation in the wafer surface. There is a problem that it is technically difficult.

Further, in a structure without a stop film, a shape without a micro trench is ideally desirable, but
Micro-trench is very likely to occur (FIG. 3), a high in-plane uniform shape cannot be obtained, and further, there is a problem in that the etching surface is roughened and etching residue is generated. In FIG. 3, reference numeral 301 denotes an organic Low-k film, 302
Is a silicon oxide film, 303 is a generated micro trench, 304 is an etching residue, and 305 is a state without a micro trench. An object of the present invention is to solve the above-mentioned problems of the prior art. A dual damascene structure having a grooved wiring having a good shape without an etching stop film and preventing wiring delay, a method for forming the dual damascene structure, and the dual structure are provided. A semiconductor device having a damascene structure and a method for manufacturing the same are provided.

[0008]

Means for Solving the Problems The present inventors have earnestly studied various materials, etching conditions and the like in order to obtain a dual damascene structure without an etching stop film, and as a result, from organic Low-k materials. By the combination of the interlayer insulating film and the silicon oxide film, etc.
The inventors have found that a dual damascene structure without an intermediate stop film can be formed by selecting etching conditions, and completed the present invention.

The Cu dual damascene structure of the present invention is
On the wiring layer provided on the substrate, an organic silicon compound film or a porous silicon oxide film as a first insulating film, and an organic Lo
An interlayer insulating film made of a wk material is sequentially provided, and a Cu wiring film is embedded in the wiring groove. A semiconductor device of the present invention has the Cu dual damascene structure described above.

According to the method of forming a Cu dual damascene structure of the present invention, the first insulating film is formed on the wiring layer provided on the substrate,
A step of forming an interlayer insulating film made of an organic Low-k material and a second insulating film in this order, a photoresist pattern is formed on the second insulating film, and a halogenated carbon gas or a halogenated hydrocarbon gas is used. Then, a step of collectively etching and removing the upper surface of the wiring layer provided on the substrate to form a via hole, peeling and removing the photoresist layer, and photoresist on the second insulating film forming a part of the wiring groove. A step of forming a pattern and etching away the second insulating film up to the upper surface of the interlayer insulating film by using a halogenated carbon gas or a halogenated hydrocarbon gas; after removing and removing the photoresist layer, N ₂ , H ₂ , NH ₃ , O ₂ , N
A step of forming a wiring groove by performing interlayer insulating film trench etching using a gas mainly containing ₂ O, NO, CO, or a CO ₂ gas or a mixed gas of at least two kinds of these gases; Cu to fill the groove
The method includes a step of forming a wiring layer and a step of performing a surface flattening process on the thus obtained laminated surface by CMP to form a Cu wiring film.

The first insulating film and the second insulating film are oxide films.
The organic Low-k material is a poly-alloy.
Are mainly ether or fluorinated polyimide,
The carbon halide gas is CF_Four, C_TwoF_Four,
C_TwoF₆, C_ThreeF₈, C_FourF ₈, C₅F₈Carbo bromide
Gas, or fluorocarbon iodide gas.
CHF is the hydrogenated hydrocarbon gas._Three, CH_TwoF_TwoOr C
H_ThreeCHF_TwoIs preferred. Where halogen
Is preferably F, Br or I. Further, the semiconductor device of the present invention
The manufacturing method is as described above for the Cu dual damascene.
A method of manufacturing a semiconductor device by forming a structure.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 4A to 4H show an example of a process for manufacturing a semiconductor device by forming a dual damascene structure according to an embodiment of the present invention in the order of steps.

First, as shown in FIG. 4A, a first insulating film (silicon oxide film) is formed on a substrate 401 on which elements such as transistors are formed and Cu first wirings are formed.
402 is formed with a thickness of about 300 to 1000 nm, and an interlayer insulating film 403 of an organic Low-k material with a thickness of about 500 nm is formed on the first silicon oxide film. After forming the interlayer insulating film 403, as shown in FIG. 4B, a second insulating film (silicon oxide film) 404 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film by the CVD method. . Next, as shown in FIG. 4C, a photoresist pattern 405 is formed by a normal exposure method. afterwards,
As shown in FIG. 4D, the substrate 404 is formed by using a halogenated carbon gas such as C ₃ F ₈ gas as an etchant.
To the upper surface of the substrate are collectively etched to form a via hole 406. After peeling and removing the photoresist layer 405, as shown in FIGS. 4E and 4F, a photoresist pattern 407 is formed again by a normal exposure method, and C ₃ F ₈ gas or the like is used as an etchant. Using such a halogenated carbon gas, the silicon oxide film 404 is removed by etching up to the upper surface of the interlayer insulating film 403.

Next, as shown in FIG.
N as an event_Two, H_Two, NH_Three, O _Two, N_TwoO, NO,
CO or CO_TwoGas mainly consisting of
Organic Low using at least two kinds of these mixed gases
-K film trench etching is performed to remove the first insulating film 402
The upper surface is removed by etching to form a wiring groove 408.
Peeling and removing the photoresist layer 407 by ashing
To do. As the mixed gas, for example, N_TwoAnd H_TwoWith
N for mixed gas_TwoGas = 50-80, H_TwoGas = 5
A mixture of 0 to 20 can be used.
It

By using the interlayer insulating film 403 made of the organic Low-k film and the first insulating film 402 in combination as described above, the etching selection ratio becomes 20 or more,
Even if a stop film is not used as an intermediate layer, the organic low
The -k film can be over-etched, and a desired wiring groove can be formed. Further, the resist ashing process for the etching residue is not necessary, and the second insulating film and the interlayer insulating film can be removed by etching at once.
By forming the wiring groove 408 in this way, a desired wiring groove can be formed without using a stop film as an intermediate film.

After forming the wiring groove 408, TiN, Ta
A barrier metal such as N or WN is deposited on the inner wall surface of the groove and the field portion by sputtering to form a barrier film 409.
Are formed (FIG. 4 (H)). Then, a Cu wiring layer is formed by an electrolytic plating method or the like so as to fill the wiring groove 408, and then a surface flattening process is performed on the laminated surface by CMP to fill the wiring groove 408 with a field overflowing from the wiring groove. Excessive Cu wiring material is shaved off, a Cu wiring film 410 is formed, and a Cu dual damascene structure as shown in FIG. 4H is formed.

In the above process, the first insulating film 40
The groove formed in 2 is a connection hole wiring that electrically connects the wiring, and the groove formed in the interlayer insulating film 403 made of the organic Low-k film and the second insulating film is the Cu wiring of the second metal wiring. Is. Since the etching rates of the silicon oxide film and the organic Low-k film are different, it is possible to form a dual damascene structure in which a wiring layer and a via hole for connecting a lower layer wiring are collectively formed as described above. is there.

In the above process, as the first insulating film, in addition to silicon oxide, SOD (spin on dielectri
cs), for example, FSG, MSQ, HMSQ, HSQ, M
HSQ, porous silica, etc. can be used, and the method for forming this film can be selected at any time according to the respective materials. Further, as the organic Low-k material, for example, polyaryl ether-based SiLK, FLARE and G
X-3 and the like, as well as polyimid fluoride and the like can be used, and the method of forming a film made of this material can be selected at any time according to the characteristics of each material.

[0019] As an etchant, in addition to the halogenated carbon gas, a halogenated hydrocarbon gas _{(C x} H y _{F z}
Gas), for example, CHF ₃ , CH ₂ F ₂ , CH ₃
Fluorohydrocarbon gas such as CHF ₂ may be used. Further, when the organic Low-k film is subjected to trench etching using the above etching gas, it is preferable to use N ₂ , H ₂ , NH ₃ , or O ₂ gas as described above as the etching gas. N ₂ and H ₂ as etching gas
With a mixed gas (N ₂ : H ₂ = 70: 30 in volume%) and NH ₃ gas under a pressure of 0.4 Pa and organic Low.
FLARE (registered trademark: Honeywell Electro
Figure 5 shows the relationship between the RF bias power and etching rate (nm / min) when etching a film (made by nic Materials).
Shown in. The case where Ar gas is used as a control is also shown in FIG. As is clear from this figure, the etching rate has a characteristic of increasing linearly without being saturated.
On the other hand, with a simple sputtering such as Ar, even if the bias power is increased, it is about 100 nm / min, and the etching rate hardly increases. Therefore, Organic Low
The etching mechanism of −k is N ₂ , H ₂ , N as described above.
It can be seen that a gas mainly containing a gas such as H ₃ , O ₂ , N ₂ O, NO, CO, or CO ₂ or an addition process is very useful.

Furthermore, the excited N ₂ + H ₂ (N in volume%
₂ : H ₂ = 70: 30) plasma and 0.4 Pa
Under low pressure, organic Low-k (FLARE), SiN, S
FIG. 6 shows the relationship between the RF bias power (W) and the etching rate and selectivity of each film when each film of io ₂ and MSQ (methylsilsesquioxane) was etched. As is clear from FIG. 6, in the process for etching the organic Low-k film, the silica-based Low-k film hardly reacts. This is the organic L in FIG. 4 (G) described below.
Underlying silica-based Low during etching of the ow-k film 403
This means that a high selection ratio (20 or more) can be obtained for the -k film 402. Therefore, even if overetching is performed, the film thickness t ₄₀₃ of the organic Low-k film and the silica-based Lo are reduced.
The thickness t ₄₀₂ of the wk film is almost unchanged. Furthermore, it means that the micro trench 303 shown in FIG. 3 does not occur. Further, as the photoresist, any commonly used resist can be used, and for example, SR resist, KrF resist, ArF resist, F ₂ resist and the like can be used.

[0021]

EXAMPLES The present invention will be described in detail below based on examples. (Embodiment 1) As shown in FIG. 4A, a silicon oxide film 402 having a thickness of 500 nm is formed on a substrate 401 on which elements such as transistors are formed and a first wiring of Cu is formed.
The FLARE film 403 is formed with a film thickness of about 500 nm on this film. This organic Low-k
After forming the film 403, as shown in FIG. 4B, a silicon oxide film 40 having a film thickness of about 50 to 100 nm is formed on this film.
4 was formed by the CVD method.

Next, as shown in FIG. 4C, a photoresist pattern 405 was formed by an ordinary coating / exposure method using an SR resist as a photoresist. After forming the resist pattern, C ₃ F ₈ / A as an etchant
SiO ₂ under a pressure of 0.1 to 1 Pa using r gas.
Under the condition that the film can be vertically etched, the via hole 406 is formed by collectively etching to the upper surface of the substrate 401, and then the photoresist layer 405 is removed and removed by ashing (FIG. 4D). Since it is not necessary to stop this etching on the way, no micro-trench was generated, no etching residue was left, and the etching surface was not roughened, and high uniformity of the etching surface was obtained.

After removing the photoresist described above, FIG.
As shown in (E) and (F), SR is used as a photoresist.
Using a resist, again using the usual coating / exposure method,
Form a photoresist pattern 407 and use it as an etchant
C_ThreeF₈Using gas, SiO _TwoThe film is etched vertically
Etching up to the top surface of the organic Low-k film
To remove the silicon oxide film 404 by etching.
It was Then, as shown in FIG. 4G, an etchant is formed.
, N_Two= 70, H_TwoGas having a mixing ratio of = 30
Organic low-k film trench etching using
Etching up to the upper surface of the silicon oxide film 402
A Cu oxide wiring groove 408 was formed. By ashing
The photoresist layer 407 was peeled and removed.

After forming the wiring groove 408, TiN, Ta
A barrier metal of N or WN was deposited on the inner wall surface of the wiring groove and the field portion by sputtering to form a barrier film 409. Then, a Cu wiring layer is formed by an electrolytic plating method so as to fill the wiring groove 408, and then,
The surface of the layer is flattened by CMP,
Excessive Cu wiring material in the field portion that overflows from the wiring groove without being embedded in the wiring groove 408 is scraped off to remove the Cu wiring film 41.
0 was formed to form a Cu dual damascene structure as shown in FIG.

As described above, by using the organic Low-k film 403 in combination with the silicon oxide film or the silicon-based Low-k film 402, the etching selection ratio is 20.
As described above, the silicon oxide film and the interlayer insulating film can be collectively etched and removed without using the stop film as the intermediate layer, the organic Low-k film can be over-etched, and a desired wiring groove can be formed. I was able to. In addition, an ashing process for removing the resist residue was unnecessary. In the above embodiment, in addition to silicon oxide, as SOD, FSG, MSQ, HMSQ, H
Even if SQ and porous silica are used, organic Low-k
As a material, in addition to the FLARE film, SiLK or GX-3,
Similar results are obtained using fluorinated polyimide.

Further, as an etchant _C x _H y _{F z gas,} as halocarbon gases other than C 3 _{F 8} gas,
_{CF 4, C 2 F 4,} C 2 F 6, C 4 F 8, C 5 F 8, bromide carbon gas, or iodide carbon fluoride gas, and as the halogenated hydrocarbon gas, _CHF 3, CH ₂
Similar results are obtained with F ₂ or CH ₃ CHF ₂ . Furthermore, similar results can be obtained by using the above-mentioned gas other than the mixed gas having the mixing ratio of N ₂ = 70 and H ₂ = 30.

[0027]

According to the present invention, the use of a combination of an interlayer insulating film made of an organic Low-k film and an insulating film results in a high etching selection ratio, and even without using an etching stop film as an intermediate layer, The organic Low-k film can be over-etched, a desired wiring groove can be formed, a resist ashing process is not required, and the insulating film and the interlayer insulating film can be collectively etched and removed. Therefore, it is possible to easily form a dual damascene structure having a grooved wiring with a good shape without an etching stop film and causing no wiring delay, and also to easily manufacture a semiconductor device having this dual damascene structure. It can be manufactured.

[Brief description of drawings]

FIG. 1A is a schematic cross-sectional view showing the configuration of a semiconductor device semi-processed product in which a wiring groove is formed in a conventional process of forming a dual damascene structure having a stop film. (B) A schematic cross-sectional view showing the configuration of a semi-processed product having a barrier film formed in the conventional process of forming a dual damascene structure having a stop film. (C) A schematic cross-sectional view showing the structure of a semi-processed product in which a Cu wiring material is embedded in a conventional process of forming a dual damascene structure having a stop film. (D) A schematic cross-sectional view showing a Cu dual damascene structure after CMP treatment in the conventional process of forming a dual damascene structure with a stop film.

FIG. 2 is a schematic cross-sectional view showing a configuration of a semi-processed product in which a wiring groove is formed in a conventional process of forming a dual damascene structure without a stop film.

FIG. 3 is a schematic cross-sectional view showing the structure of a semi-processed product for explaining a micro-trench that occurs when forming a wiring groove in the conventional process of forming a dual damascene structure without a stop film.

FIG. 4A is a schematic cross-sectional view showing the configuration of a semi-finished semiconductor device product in which a first insulating film and an interlayer insulating film are formed in the dual damascene structure forming process of the present invention. (B) A schematic cross-sectional view showing the configuration of a semi-processed product on which a second insulating film (SiO ₂ film) is formed in the dual damascene structure forming process of the present invention. (C) In the dual damascene structure forming process of the present invention, a schematic cross-sectional view showing the structure of a semi-processed product for explaining the resist coating / exposure process. (D) In the dual damascene structure forming process of the present invention, a schematic cross-sectional view showing the structure of a semi-processed product for explaining the step of forming via holes by collective etching. (E) In the dual damascene structure forming process of the present invention, a schematic cross-sectional view showing the structure of a semi-processed product for explaining the resist coating / exposure process. (F) In the dual damascene structure forming process of the present invention, a schematic cross-sectional view showing the structure of a semi-processed product for explaining the step of etching away the second insulating film (SiO ₂ film). (G) In the dual damascene structure forming process of the present invention, a schematic cross-sectional view showing the structure of a semi-processed product for explaining the step of etching away the organic Low-k film. (H) In the dual damascene structure forming process of the present invention, the organic Low-k film is etched over to form Cu.
FIG. 3 is a schematic cross-sectional view showing the structure of a semi-processed product for explaining the process of embedding wiring.

FIG. 5: RF when etching an organic Low-k film
The graph which shows the relationship between bias electric power and etching rate (nm / min).

FIG. 6 is a graph showing the relationship between the RF bias power (W) and the etching rate and selectivity of each film when an organic Low-k, a film, and other films are etched using plasma.

[Explanation of symbols]

101 first interlayer insulating film 102 stop film 103 second interlayer insulating film 104 second
Insulating film 105 Groove (wiring groove) 106 Barrier film 107 Cu wiring layer 201 Organic Low-k film 202 Silicon oxide film A Etching stop point 301 Organic Low-k film 302 Silicon oxide film 303 Micro trench part 304 Etching residue 305 Micro trench Unexposed portion 401 Substrate 402 First insulating film (silicon oxide film) 403 Interlayer insulating film 404 Second insulating film (silicon oxide film) 405 Photoresist pattern 406 Via hole 407 Photoresist layer 408 Wiring groove 409 Barrier film 410 Cu wiring film t ₄₀₂ Thickness of first insulating film t ₄₀₃ Thickness of interlayer insulating film

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F004 AA02 DA03 DA24 DA25 DA26                       DB03 DB23 EB02                 5F033 HH32 HH33 HH34 JJ32 JJ33                       JJ34 KK11 MM02 MM12 MM13                       NN06 NN07 PP17 PP27 QQ09                       QQ15 QQ25 QQ37 QQ48 RR01                       RR04 RR21 RR22 RR26 RR29                       SS11 XX27

Claims (8)

[Claims] 1. An organic silicon compound film or a porous silicon oxide film as a first insulating film, and an interlayer insulating film made of an organic Low-k material are sequentially provided on a wiring layer provided on a substrate, and wiring is further provided. A Cu dual damascene structure characterized in that a Cu wiring film is embedded in the groove. 2. A semiconductor device having the Cu dual damascene structure according to claim 1. 3. A first insulating film, an interlayer insulating film made of an organic Low-k material, and a second insulating film on the wiring layer provided on the substrate.
A step of forming an insulating film in this order, a photoresist pattern is formed on the second insulating film, and a halogenated carbon gas or a halogenated hydrocarbon gas is used to collectively reach the upper surface of the wiring layer provided on the substrate. A step of forming a via hole by etching removal, peeling and removing the photoresist layer,
A photoresist pattern is formed on the second insulating film forming a part of the wiring groove, and a halogen carbon gas or a halogenated hydrocarbon gas is used to form a photoresist pattern up to the upper surface of the interlayer insulating film.
The step of etching away the insulating film, after peeling and removing this photoresist layer, N ₂ , H ₂ , NH ₃ , O ₂ , N
₂ O, NO, CO, a gas mainly composed of CO ₂ gas, or a mixed gas of at least two of these,
A step of performing interlayer insulating film trench etching to form a wiring groove, a step of forming a Cu wiring layer so as to fill the wiring groove, and a surface flattening treatment by CMP to the thus obtained laminated surface. A method of forming a Cu dual damascene structure, including the step of forming a Cu wiring film. 4. The Cu according to claim 3, wherein the first insulating film and the second insulating film are silicon oxide films.
Method of forming a dual damascene structure. 5. The method for forming a Cu dual damascene structure according to claim 3, wherein the organic Low-k material is mainly composed of polyaryl ether or fluorinated polyimide. 6. The halogenated carbon gas is CF ₄ , C
₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ , C ₅ F ₈ , carbon bromide gas, or fluoroiodinated carbon gas, and the halogenated hydrocarbon gas is CHF ₃ , CH ₂
Method for forming a Cu dual damascene structure according to any one of claims 3-5, characterized in that the F ₂ or _CH 3 CHF _2. 7. A first insulating layer on a wiring layer provided on a substrate.
A film, an interlayer insulating film made of an organic Low-k material, and a second
The step of forming the insulating film in this order, the step of forming a film on the second insulating film.
A photoresist pattern is formed, and a halogenated carbon gas or
Was provided on the substrate using a halogenated hydrocarbon gas
Via holes are removed by batch etching to the top surface of the wiring layer.
A step of forming, removing and removing the photoresist layer,
Photoresist on the second insulating film forming part of the wiring groove
Form a pattern and use carbon halide gas or halogen
A second layer up to the upper surface of the interlayer insulating film by using a hydrocarbon gas.
Step of etching away the insulating film, this photoresist
After peeling and removing the layer, N _Two, H_Two, NH_Three, O_Two, N
_Two, H_Two, NH_Three, O_Two, N_TwoO, NO, CO, young
Is CO_TwoGas mainly of, or less of these
Both of them use a mixed gas of two types to form an interlayer insulating film trench etch.
Process to form wiring trenches, and then
A step of forming a Cu wiring layer so as to bury the wire groove,
Surface flattening by CMP on the laminated surface obtained by
It is characterized by including a step of performing a treatment and forming a Cu wiring film.
Semiconductor device manufacturing of Cu dual damascene structure
Method. 8. The first insulating film and the second insulating film are silicon oxide films, the organic Low-k material is mainly a polyaryl ether or fluorinated polyimide, and the halogenated carbon is used. The gas is CF ₄ , C ₂ F
₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ , C ₅ F ₈ , carbon bromide gas, or fluoroiodinated carbon gas, and the halogenated hydrocarbon gas is CHF ₃ , CH ₂ The method for manufacturing a semiconductor device having a Cu dual damascene structure according to claim 7, wherein the method is F ₂ or CH ₃ CHF ₂ .