JP2003169492A - Dc brushless motor control circuit and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce sizes of an FET and a heat sink plate by improving a gate drive circuit of a driver and suppressing the loss of the FET in a DC brushless motor used for a polygon mirror motor or the like for a scanner. <P>SOLUTION: The DC brushless motor control circuit comprises a semiconductor switch, a gate drive circuit for driving the switch, and a control circuit for driving the gate drive circuit in such a manner that an arbitrary delay time incorporated in the gate drive circuit is combined with the acceleration of the gate drive circuit. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC brushless motor control circuit and an electrophotographic image forming apparatus using the DC brushless motor as a polygon mirror motor for a scanner.

[0002]

2. Description of the Related Art An image forming apparatus to which a conventional electrophotographic technique is applied uses a DC brushless motor as a polygon mirror motor for a scanner for writing an electric latent image on a photosensitive drum, and uses a semiconductor switch such as FET or IGBT. It has been used as a driver for DC brushless motors. In general, FETs and IGBTs for electric power use have a large gate input capacitance, and a gate drive circuit capable of withstanding driving a capacitive load is required. The gate drive circuit is driven by the control circuit. The control circuit generates a signal for rotating the DC brushless motor. Next, a case where an FET is used will be specifically described with reference to the drawings.

FIG. 5 is a block diagram of a conventional DC brushless motor control circuit. The control circuit 42 is a control circuit for a three-phase DC brushless motor and is generally a dedicated IC for the DC brushless motor, and is UL, VL, WL, UH, VH, W.
Change the output of H. Further, the control circuit 42 has a direct PWM function, and PWMs UH, VH, and WH signals.
The Nch-FET is controlled to perform PWM operation. Reference numeral 43 is a gate drive circuit for the Pch-FET 49, and the transistor
5, an output part which is composed of a resistor 56 and is connected to the gate of the Pch-FET 49 is a collector follower circuit. Four
Reference numeral 4 denotes a gate drive circuit for the Pch-FET 51, which is composed of a transistor 57 and a resistor 58, and the output section connected to the gate of the Pch-FET 51 is a collector follower circuit. Reference numeral 45 is a gate drive circuit for the Pch-FET 53, which is composed of a transistor 59 and a resistor 60, and the output section connected to the gate of the Pch-FET 3 is a collector follower circuit. Reference numeral 46 denotes a gate drive circuit for the Nch-FET 50, which has a collector follower circuit configuration including a resistor 61, a transistor 62, and a resistor 63. 47 is Nch-F
Resistor 64, transistor 6 in the gate drive circuit of ET52
5, a collector follower circuit configuration including a resistor 66. A gate drive circuit 48 of the Nch-FET 54 has a collector follower circuit configuration including a resistor 67, a transistor 68, and a resistor 69. Resistance 70,
The resistors 71 and 72 are Nch-FET 54 and N, respectively.
The gate resistance of the ch-FET 52 and the Nch-FET 54 is a small resistance of about several tens Ω, and when the noise induced in the gate of the Nch-FET does not pose a problem, each gate drive circuit and the gate of the Nch-FET are directly connected. You may. 73 is a DC brushless motor which is excited by the FET and rotates.

Reference numerals 43, 44, and 45 are gate drive circuits for Pch-FETs, which have the same function and operation, and will be described with reference to 43. When UL of the control circuit 42 becomes H, the transistor 55 is turned on and the gate input capacitance of the P-FET 49 is driven to L by the transistor 55, so P
-The gate of FET 49 goes low. UL of control circuit 42
When L becomes L, the transistor 55 is cut off and P-FE
The gate of T49 rises due to resistor 56. 46, 4
Reference numerals 7 and 48 denote Nch-FET gate drive circuits, which have the same functions and operations and will be described with reference to 46. When UH of the control circuit 42 becomes H, the transistor 6
2 turns on, and the gate of P-FET49 becomes L. When UH of the control circuit 42 becomes L, the transistor 62 is cut off and the gate of the P-FET 49 becomes H by the resistor 56. Next, description will be made with reference to FIG. One Pch-FE
When T turns off, the other Pch-FET turns on. When one Nch-FET turns on, the other Pch-FET turns off. Pch
-Two Pch-FEs because one Nch-FET is on when the FET is turned on and when it is turned off.
The current flowing by T flows into one Nch-FET. At this time, the current flowing in the Pch-FET is a current required by the motor, so that the Nch-FET is required to have a current rating much higher than the motor current. Similarly, when one Nch-FET turns off, another Nch-FET turns off.
-The FET turns on. Also one Nch-FET
When it turns on, the other Nch-FET turns off. Since one Nch-FET is on at the time of turning on and off the Nch-FET, 2
One Nch-FET has one Nch-FET
Flow into. At this time, the current flowing in the Nch-FET is a current required by the motor, and therefore the Nch-FET is required to have a current rating much higher than the motor current.
For the above reasons, all Nch-FETs and all Nc
The h-FET has a period of simultaneous ON, and the current at the time of simultaneous ON increases the loss of the FET and causes an instantaneous junction temperature. Therefore, it is necessary to use a FET with a current rating that greatly exceeds the current required by the motor and use a large radiator plate.

[0005]

The loss of the semiconductor switch includes a steady loss during the ON period and a transient loss that occurs when the excitation is switched or the current is controlled by PWM control.
FET is used as a semiconductor switch in DC brushless motors.
Since the on-state resistance is low, the effect of transient loss is greater than the steady-state loss during the on-state because of its low on-resistance. In the conventional circuit, the gate circuit simply generates the gate voltage of the FET and the transient loss. In order to suppress the transient loss, the speed of the gate circuit should be increased in order to shorten the time to generate the transient loss. Therefore, the simultaneous ON prevention of the FET is not considered and the current value of the motor is greatly exceeded.
It was decided to select ET or IGBT. In the conventional gate drive circuit, as shown in FIG.
There is a period in which two ch-FETs or Nch-FETs are turned on at the same time, and a current larger than usual flows. Further, since the control circuit controls the on time of the FET by PWM control to control the current value, the transient loss generated when the FET is turned on / off during the current control by PWM is also a heat loss. Due to the simultaneous turn-on of the FET and the transient loss during PWM, the conventional DC brushless motor control circuit is originally D
The FET used is significantly larger than the rated FET required to drive the C brushless motor, and a large heat sink is used for heat dissipation. In the present invention, the gate drive circuit of the conventional DC brushless motor is improved to suppress FET loss and
The ET and the heat sink are downsized and the reliability is improved.

[0006]

1 shows an embodiment of the present invention.
The control circuit 34 is a control circuit of a three-phase DC brushless motor and changes the outputs of UL, VL, WL, UH, VH, and WH. Further, the control circuit 34 has a direct PWM function and performs PWM control of UH, VH, and WH signals to perform Nch-
Operate the FET in PWM. 39 is Nch-FET1
14 and 1 in the gate drive circuit of
3, the output portion which is composed of the resistor 23 and the resistor 22 and is connected to the gate of the Nch-FET 1 is a transistor 13 and the resistor 22 to form a collector follower circuit. 40 is Nch-
The gate drive circuit of the FET3 is composed of a transistor 16, a transistor 15, a resistor 26, and a resistor 25, and is an Nch-F.
The output part connected to the gate of ET3 is a transistor 15
And the resistor 25 makes a collector follower circuit. Four
Reference numeral 1 denotes a gate drive circuit for the Nch-FET 5, which is composed of a transistor 18, a transistor 17, a resistor 29, and a resistor 28, and an output portion connected to the gate of the Nch-FET 5 is a transistor 17 and a resistor 28 to form a collector follower circuit. Reference numeral 36 is a gate drive circuit for the Nch-FET 2 and a resistor 3
The emitter-follower push-pull configuration is composed of a transistor 1, a transistor 7, and a transistor 8. Reference numeral 37 denotes a gate drive circuit for the Nch-FET 4, which has a push-pull structure of an emitter follower including a resistor 32, a transistor 9 and a transistor 10. 38 is Nch-
Resistor 33, transistor 1 in the gate drive circuit of FET6
1, an emitter follower composed of a transistor 12 and a push-pull structure. Resistor 19, resistor 20,
The resistors 21 are Nch-FET2 and Nch-FET, respectively.
4. The gate resistance of the Nch-FET 6, which is a small resistance of about several tens Ω, and when the noise induced in the gate of the FET does not pose a problem, each gate drive circuit and the Nch-FE
The gate of T may be directly connected.

FIG. 2 shows operation waveforms when the output of the Nch-FET is turned on and when it is turned off in the present invention. Nch-
In order for the output of the FET to change from OFF to ON, UL needs to change from H to L, and the control circuit 34 changes UL to L. UL is input to the gate drive circuit 39, and the gate drive circuit 39 is input to the gate of the Nch-FET 1. Since the gate of the Nch-FET has an input capacitance and the resistor 22 in the gate drive circuit 39 causes a transient phenomenon to fall, the gate input capacitance Cip and the resistance value R22 of the resistor 22 are present.
The voltage drop is delayed by the time determined by the product of The delay time of the gate voltage drop of this Nch-FET is Nch-
This is the delay time of turning on the FET. Nch-F
When ET changes from on to off, UL becomes H and is input to the gate drive circuit 39, and the output of the gate drive circuit 39 is N.
Input to the gate of ch-FET1. Even when the Nch-FET is off, the input capacitance Cip of the gate of the Nch-FET acts as a time delay element, but since it is driven by the transistor 13 in the gate drive circuit, the rise is steep and the delay time is small. Since the delay time of the rise of the gate voltage of the Nch-FET is short, the delay of the time when the Nch-FET turns off also becomes small.

FIG. 3 shows operation waveforms when the output of the Nch-FET is turned on and when it is turned off in the present invention. Nch-
In order for the output of the FET to change from OFF to ON, UH needs to change from L to H, and the control circuit 34 changes UH to H. UH is input to the gate drive circuit 36, and the gate drive circuit 36 outputs H and inputs it to the gate of the Nch-FET 2. The gate of the Nch-FET has an input capacitance Ci.
Since there is n and the Nch-FET is turned on, a transient phenomenon occurs for a time determined by the product of the resistance 19 and the resistance 19 and C falls.
The turn-on of the Nch-FET is delayed by the time determined by the product of in and the resistance value R19 of the resistor 19. However, the value of the resistor 19 is several tens Ω, and the delay time is small. Also Nch
-When FET turns off, UH changes from H to L and Nch
The gate of the FET goes from L to H. Since the gate drive circuit 36 has a push-pull structure of the emitter follower, the rising of the gate voltage of the Nch-FET operates at the same high speed as when the turn-on changes.

FIG. 4 shows the operation waveforms of the respective FETs of the present invention, but the transient simultaneous ON period generated when switching the excitation phase of the DC brushless motor is reduced. Also Nc
When the h-FET is performing PWM operation, Nch-
Although the transient loss occurs when the FET 1 is turned on and off, the gate drive circuit 36 has a push-pull configuration of the emitter follower, so the gate is repeatedly driven on and off repeatedly, and the transient loss of the Nch-FET during PWM operation is small. In this embodiment, a delay time is provided when the Nch-FET is turned on, and the gate drive circuit of the Nch-FET operating in direct PWM mode has a push-pull configuration to speed up the operation and suppress the loss during switching the excitation phase and the loss during PWM. By F
ET loss can be significantly reduced. Most of the loss that occurs when switching the FET of a DC brushless motor is due to overcurrent when the FETs are simultaneously turned on and Nch-FET.
Is a transient loss at the time of PWM control performed for current control, and therefore prevention of simultaneous FET turn-on and speeding up of the gate circuit of the Nch-FET significantly reduce the loss.

FIG. 7 shows a schematic diagram of an electrophotographic image forming apparatus. Laser light is emitted from the semiconductor laser 101 driven by the semiconductor laser drive circuit 100, and reflected by the reflecting surface of the polygon mirror 103 via the lens 102. Since the polygon mirror 103 is rotated by the polygon mirror 104, the laser light reflected by the mirror 105 scans the photosensitive drum 106. Photosensitive drum 1
The surface of 06 is charged by the charger 107, and then characters and image signals are written by the laser beam and visualized by the toner in the developing device 108. The toner on the surface of the photosensitive drum is transferred to the sheet 111 by the transfer unit 109 and fixed on the sheet by a fixing device (not shown). Unnecessary toner on the photosensitive drum 106 is cleaned by the cleaner 110. The DC brushless motor control circuit of the present invention is used to drive the polygon mirror motor 104. With the DC brushless motor control circuit of the present invention, high-speed rotation and high reliability of the polygon mirror motor enable high-speed printing and high quality of the image forming apparatus, and downsizing of the entire apparatus.

[0011]

In the conventional DC brushless motor driver, two Nch-FEs are transiently changed by the signal of the control circuit.
There was an ON period of T or two Nch-FETs. Moreover, since a transient loss occurs during PWM operation, a large FET having a rating higher than the motor current is used. As for the heat sink, a large heat sink has been used in consideration of the instantaneous rise in junction temperature.

According to the present invention, it is possible to delay the turn-on timing of the FET at the time of switching the excitation phase of the DC motor to suppress the overlap of the current with the FET that is turned off, and to reduce the transient loss by increasing the speed of the gate drive circuit of the PWM control section. By combining them, it is possible to form a highly reliable DC brushless motor control circuit with a small FET and a small radiator plate, and it is possible to achieve low cost and high reliability.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a turn-on / turn-off operation of the Nch-FET according to the embodiment of the present invention.

FIG. 3 is a waveform diagram showing a turn-on / turn-off operation of the Pch-FET according to the embodiment of the present invention.

FIG. 4 is a waveform diagram showing simultaneous FET turn-on according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional DC brushless motor control circuit.

FIG. 6 FET of a conventional DC brushless motor control circuit
It is a wave form diagram which shows simultaneous ON.

FIG. 7 is a schematic diagram of an electrophotographic image forming apparatus that is an embodiment of the present invention.

[Explanation of symbols]

1, 3, 5, 49, 51, 53 ... Pch-FET, 2,
4, 6, 50, 52, 54 ... Nch-FET, 7, 8,
9, 10, 11, 12, 13, 14, 15, 16, 1
7, 18, 55, 57, 59, 62, 65, 68 ... Transistor, 19, 20, 21, 22, 23, 24, 2
5,26,28,29,31,32,33,56,5
8, 60, 61, 63, 64, 66, 67, 69, 7
0, 71, 72 ... Resistance, 34, 42 ... Control circuit, 35,
73 ... DC brushless motor, 36, 37, 38, 3
9,40,41,43,44,45,46,47,48
… Gate drive circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masaharu Kimura             Hitachiko, 1060 Takeda, Hitachinaka City, Ibaraki Prefecture             Machine Co., Ltd. (72) Inventor Hiroshi Inaga             Hitachiko, 1060 Takeda, Hitachinaka City, Ibaraki Prefecture             Machine Co., Ltd. F-term (reference) 2C362 AA03 BA04 BA08                 5H007 AA03 AA06 BB06 CA02 CB05                       DB03 FA06 FA13                 5H560 AA03 BB04 EB01 EC04 JJ02                       JJ06 JJ19 RR02 SS01 UA05                       UA06 XA12 XB02                 5H740 AA04 BA12 JA01 JB01 MM08                       MM13

Claims (3)

[Claims] 1. A control circuit for a DC brushless motor, comprising a semiconductor switch, a gate drive circuit for driving the semiconductor switch, and a control circuit for driving the gate drive circuit, wherein the gate drive circuit has an arbitrary delay. A DC brushless motor control circuit characterized by having time. 2. An FET semiconductor switch and a PWM-controlled DC brushless motor control circuit are provided, and when the excitation phase of the DC motor is switched, the FET turn-on timing is delayed to prevent the current from overlapping with the FET. 2. The DC brushless motor control circuit according to claim 1, wherein the effect of reducing transient loss by increasing the speed of the gate drive circuit of the PWM control unit is combined. 3. An image forming apparatus using the DC brushless motor control circuit according to claim 2 as a polygon mirror control circuit for a scanner.