JP2003169228A - Synchronizing signal conversion circuit, image display device, and method for them - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronizing signal conversion circuit capable of correctly generating an output vertical synchronizing signal. <P>SOLUTION: The synchronizing signal conversion circuit 42 that measures a time interval of each input pulse of an input synchronizing signal V1 comprising the input pulses sequentially generated in a prescribed timing and generates an output pulse in a timing on the basis of the measured time interval to thereby generate an output synchronizing signal V10 comprising output pulses, detects discontinuity of generation timings generated from the input pulses and adjusts a generating timing of the output pulse on the basis of the detection result to correctly generate the output synchronizing signal V10. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal conversion circuit, an image display device and their methods, and is suitable for application to, for example, a television receiver.

[0002]

2. Description of the Related Art Conventionally, a television receiver has a PAL (phase alternation by line) as a color television system.
Method or SECAM (sequential couleur a memire)
Has been adopted.

Generally, the field frequency of a PAL or SECAM color video signal is 50 [Hz], and in a television receiver, the PAL or SE signal is used.
When playing a CAM color video signal on a large screen,
There is an inconvenience that flicker occurs and the image becomes difficult to see.

In order to avoid such inconvenience, a television receiver has been developed which doubles the field frequency of the video signal and outputs it. The configuration of such a conventional television receiver is shown in FIG. Shown in.

The television receiver 1 receives broadcast waves respectively distributed from a plurality of broadcasting stations by an antenna 2 and, in response to a tuning operation performed by a user on an operation unit 3, the television receiver 1 receives the broadcasting waves. Program data of a designated broadcasting station is selected from the program data, and the program data of the selected broadcasting station is demodulated and output to an external monitor for display.

That is, in the television receiver 1, the command signal S generated by the user operating the operation unit 3.
1 is sent to a CPU (central processing unit) 4. The CPU 4 analyzes the command signal S1 and controls each circuit of the television receiver 1 according to the analysis result.

As a result of analyzing the command signal S1, the CPU 4 generates a channel selection signal S2 in accordance with the tuning operation when it is determined that the user has performed the tuning operation on the operation unit 3. It is sent to the tuner 5.

The tuner 5 extracts the broadcast wave of the channel corresponding to the channel selection signal S2 from the broadcast waves received by the antenna 2 to obtain the video signal S3, and sends this to the chroma decoder 6.

The chroma decoder 6 extracts a Y signal S4A, a Cb signal S4B and a Cr signal S4C from the video signal S3 and sends them to an analog / digital (A / D) conversion circuit 7. Also, the chroma decoder 6 uses the video signal S
The horizontal synchronizing signal H1 and the vertical synchronizing signal V1 are extracted from the above 3 and are sent to the memory controller 8 and the output synchronizing generating circuit 9 and the horizontal synchronizing signal H1 is PLL.
(Phase locked loop) The signal is sent to the circuit 10. The PLL circuit 10 receives the dot clock D from the horizontal synchronizing signal H1.
C is generated and sent to the memory controller 8 and the output synchronization generating circuit 9, and the memory controller 8 and the output synchronization generating circuit 9 operate based on the dot clock DC.

The A / D conversion circuit 7 uses the Y signals S4A and Cb.
By converting the signal S4B and the Cr signal S4C from analog to digital, Y data S5A and Cb data S5B can be obtained.
And Cr data S5C are obtained and sent to the memory 11.

By the way, the memory controller 8 generates a write control signal S6A based on the horizontal synchronizing signal H1 and the vertical synchronizing signal V1 and sends it to the memory 11, thereby Y data S5A, Cb data S5B and Cr data S5C. Is written in the memory 11.

Next, the output sync generation circuit 9 generates a horizontal sync signal H2 and a vertical sync signal V2 having a field frequency doubled based on the horizontal sync signal H1 and the vertical sync signal V1 and sends them to the memory controller 8. To do. The memory controller 8 generates a read control signal S6B based on the horizontal synchronizing signal H2 and the vertical synchronizing signal V2 whose field frequencies are doubled, and sends this to the memory 11 to output Y data S7A, Cb data S7B, and The Cr data S7C is read from the memory 11 at a speed twice as high as the field frequency at the time of writing and sent to the digital-analog (D / A) conversion circuit 12.

The D / A conversion circuit 12 receives these Y data S
7A, Cb data S7B and Cr data S7C are digital-analog converted to obtain Y signals S8A, Cb.
A signal S8B and a Cr signal S8C are obtained, and these are output to an external monitor for display.

By the way, the standard signal of the PAL system is an interlaced signal of 625 scanning lines, and as shown in FIG. 5A, both the first field and the second field are scanning lines of 312.5H. , 50 [Hz], the vertical synchronizing signal V1 is generated.

Therefore, the output synchronization generation circuit 9 generates a vertical synchronization signal V2 of 100 [Hz] as shown in FIG. 5B in order to make the field frequency at the time of reading twice the field frequency at the time of writing. It is done like this.

In the output synchronization generation circuit 9, as a method of generating the vertical synchronization signal V2 having such a doubled field frequency, as shown in FIG. 6, the time of the input vertical synchronization signal V1 is measured. And 1 of the measured time
A method of generating an intermediate synchronizing signal pulse at a timing of / 2 is adopted (Japanese Patent Laid-Open No. 63-282029), whereby even if the field frequency changes due to special reproduction of a video tape recorder. , It avoids that the displayed image is defective.

The structure of the output synchronization generating circuit 9 is shown in FIG. 7, and the operation timing of the output synchronization generating circuit 9 is shown in FIG. When the vertical synchronization signal V1 (FIG. 8A), which is an interlaced signal of 1 field 312.5H, is supplied from the chroma decoder 6 to the output synchronization generation circuit 9, the output synchronization generation circuit 9 resets the vertical synchronization signal V1 (FIG. 8A). And the OR circuit 22.

At the same time, the output sync generation circuit 9 inputs the horizontal sync signal H1 supplied from the chroma decoder 6 to the constant-magnification circuit 23. The constant-magnification circuit 23 doubles the field frequency of the horizontal synchronizing signal H1 and outputs the horizontal synchronizing signal H2 whose field frequency is doubled to the input vertical synchronizing section counter 24, the output vertical synchronizing section counter 25, and the memory controller at the subsequent stage. Send to 8.

The reset timing generating circuit 20 is configured to reset the count operation of the input vertical synchronizing section counter 24 for each vertical synchronizing signal V1 based on the supplied vertical synchronizing signal V1.

The input vertical synchronizing section counter 24 counts one section of the vertical synchronizing signal V1 according to the supplied horizontal synchronizing signal H2, and the count value S20 thereof is latched by the latch circuit 2.
Send to 1. The latch circuit 21 holds the supplied count value S20 during the section next to the section in which the count value S20 is counted, so that the count value S20 is held.
A count value S21 (FIG. 8B) that outputs 20 during the section next to the counted section is generated, and this is set to 1 in the latter stage.
It is sent to the / 2 coefficient circuit 26.

That is, as shown in FIG. 8 (B),
The count value S21 is a count value (3 which is obtained by counting one section of the vertical synchronization signal V1 by the original horizontal synchronization signal H1.
This is twice the value of 12.5 lines (625 lines), as shown in FIG.
The count value S20 of the section a in (A) is the next section b.
Will be output.

The ½ coefficient circuit 26 multiplies the count value S21 output from the latch circuit 21 by ½, and the resulting count value S22 (FIG. 8C).
To the comparator 27.

On the other hand, the output vertical synchronization section counter 25
The input vertical synchronization section counter 24 has the same configuration as the input vertical synchronization section counter 24.
The section is counted, and the count value S23 (see FIG.
(D)) is sent to the comparator 27. This Figure 8
As shown in (D), the count value S23 increases in real time every time the horizontal synchronizing signal H2 is input to the output vertical synchronizing section counter 25.

The comparator 27 includes a 1/2 coefficient circuit 26.
The count value S22 (FIG. 8C) output from the output vertical synchronization interval counter 25 is compared with the count value S23 (FIG. 8D) output from the output vertical synchronization section counter 25, and these count values S
If it is determined that 22 and S23 match, a comparison output signal S24 (FIG. 8E) that generates a pulse of logic level "L" is generated and sent to the pulse width expansion circuit 28.

Since the comparison output signal S24 generates only a pulse having the same pulse width as the pulse generated by the horizontal synchronizing signal H2, the pulse width expansion circuit 2
8 expands the pulse width of the pulse generated by the comparison output signal S24 to the pulse width of the pulse generated by the vertical synchronization signal V1, and outputs the comparison output signal S25 (FIG. 8) obtained as a result.
(F)) to the OR circuit 22.

The OR circuit 22 takes the logical sum of the vertical synchronizing signal V1 and the comparison output signal S2 output from the pulse width expanding circuit 28 to obtain the vertical synchronizing signal V2 (FIG. 8 (G )) Is generated and sent to the memory controller 8 in the subsequent stage.

[0027]

In the output synchronization generating circuit 9 having such a configuration, when the tuner 5 is switched by the user's tuning operation, the cycle of the pulse generation timing of the input vertical synchronization signal V1 is impaired. ,
As a result, there is a disadvantage that the image is disturbed and the image quality is deteriorated.

Here, FIG. 9A shows the vertical synchronizing signal V1 when the tuner is switched, and FIG. 9B shows
A vertical synchronization signal V2 having a field frequency doubled, which is generated by the output synchronization generation circuit 9 based on the vertical synchronization signal V1 is shown. In the output vertical synchronizing signal V2, the vertical synchronizing signal pulses Vo1 to Vo6 generated at the same timing as the input vertical synchronizing signal V1 and the time of the vertical synchronizing signal V1 are measured. Vertical sync signal pulses Vm1 to Vm generated at the timing of / 2.
It is composed of 5 and.

As shown in FIG. 9A, the tuner switching is performed at timing T1, and the tuner switching is completed at timing T2. Thereafter, a stable vertical synchronizing signal V1 is input to the output synchronization generating circuit 9. The case will be described.

In this case, the vertical synchronizing signal V1 has its cycle impaired by the tuner switching, and the vertical synchronizing signal section C in which the tuner switching is performed is the vertical synchronizing signal sections A and B in the case where the normal operation is performed. It is shorter than At the timing T2, the tuner switching is completed,
Then, when the vertical synchronizing signal pulse Vi4 is output, the vertical synchronizing signal V2 is the vertical synchronizing signal pulse Vi.
Therefore, the vertical synchronizing signal pulse Vo4 is generated at the same timing as that of No.4.

By the way, the intermediate vertical synchronizing signal pulse Vm3 shown in FIG. 9B is a pulse generated at a timing of 1/2 of the vertical synchronizing section B of the input vertical synchronizing signal V1. When the vertical synchronizing signal pulse Vi4 is input after the Vm3 is generated, the vertical synchronizing signal pulse Vo4 is generated, and the intermediate vertical synchronizing signal pulse Vm3 and the vertical synchronizing signal pulse Vo4 are generated in succession. Therefore, the cycle of the vertical synchronizing signal V2 is impaired, and as a result, the image displayed on the monitor is disturbed.

Further, the intermediate vertical synchronizing signal pulse Vm4 of FIG. 9 (B) is converted to the vertical synchronizing signal V1 by the tuner switching.
Of these, the pulse is generated by measuring the section C in which the vertical synchronization section is disturbed, so that the intermediate vertical synchronization signal pulse Vm4 is generated at an incorrect timing.

In this case, the television receiver 1 processes the intermediate vertical synchronizing signal pulse Vm3 as the vertical synchronizing signal V2 and further processes the vertical synchronizing signal pulse Vo4 as a normal image signal. V
This causes the inconvenience of displaying o4 on the monitor as an image to be displayed.

The present invention has been made in consideration of the above points, and is intended to propose a synchronizing signal generating circuit, an image display device, and their methods capable of avoiding deterioration of the image quality of a display image.

[0035]

In order to solve such a problem, in the present invention, a time interval at which each input pulse of an input synchronizing signal composed of input pulses sequentially generated at a predetermined timing is measured, and is measured. Generating means for generating an output synchronizing signal composed of the output pulse by generating the output pulse at a timing based on the time interval, detecting means for detecting the discontinuity of the generating timing of the input pulse, and The adjusting means adjusts the generation timing of the output pulse based on the detection result. As a result, the output synchronization signal can be correctly generated.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 4 are designated by the same reference numerals, reference numeral 40 generally indicates the structure of a television receiver, and the antenna 2 receives broadcast waves respectively distributed from a plurality of broadcasting stations. Then, the user selects the program data of the designated broadcasting station from the received program data of the plural broadcasting stations according to the tuning operation performed by the operation unit 3, and the program data of the selected broadcasting station is selected. Demodulate and output to an external monitor for display.

That is, the television receiver 40 sends a command signal S1 generated by the user operating the operation unit 3 to a CPU (central processing unit) 41. The CPU 41 analyzes the command signal S1 and controls each circuit of the television receiver 40 according to the analysis result.

When the CPU 41 analyzes the command signal S1 and determines that the user has performed a tuning operation on the operation unit 3, the CPU 41 generates a channel selection signal S2 according to the tuning operation, and outputs it. A tuner switching start signal S41A indicating that the switching of the tuner 5 has started and a tuner switching end signal S41B indicating that the switching of the tuner 5 has finished are generated while being sent to the tuner 5, and these are output to the output synchronization generating circuit 42. Send to.

The tuner 5 extracts the broadcast wave of the channel corresponding to the channel selection signal S2 from the broadcast waves received by the antenna 2 to obtain the video signal S3 and sends it to the chroma decoder 6.

The chroma decoder 6 extracts the Y signal S4A, the Cb signal S4B and the Cr signal S4C from the video signal S3 and sends them to the analog / digital (A / D) conversion circuit 7. Also, the chroma decoder 6 uses the video signal S
The horizontal synchronizing signal H1 and the vertical synchronizing signal V1 are extracted from the above 3 and are sent to the memory controller 8 and the output synchronizing generating circuit 42, and the horizontal synchronizing signal H1 is PLL.
(Phase locked loop) The signal is sent to the circuit 10. The PLL circuit 10 receives the dot clock D from the horizontal synchronizing signal H1.
C is generated and sent to the memory controller 8 and the output synchronization generating circuit 42, and the memory controller 8 and the output synchronization generating circuit 42 operate based on the dot clock DC.

The A / D conversion circuit 7 uses the Y signals S4A and Cb.
By converting the signal S4B and the Cr signal S4C from analog to digital, Y data S5A and Cb data S5B can be obtained.
And Cr data S5C are obtained and sent to the memory 11.

By the way, the memory controller 8 generates the write control signal S6A based on the horizontal synchronizing signal H1 and the vertical synchronizing signal V1 and sends it to the memory 11, whereby the Y data S5A, Cb data S5B and Cr data S5C are generated. Is written in the memory 11.

Next, the output sync generation circuit 42 generates a horizontal sync signal H2 and a vertical sync signal V10 having a field frequency doubled based on the horizontal sync signal H1 and the vertical sync signal V1 and sends them to the memory controller 8. To do. The memory controller 8 generates a read control signal S6B based on the horizontal synchronizing signal H2 and the vertical synchronizing signal V10 whose field frequency is doubled, and sends the read control signal S6B to the memory 11, whereby Y data S7A, Cb data S7B and C
The r data S7C is read from the memory 11 at a speed twice as high as the field frequency at the time of writing and sent to the digital / analog (D / A) conversion circuit 12.

The D / A conversion circuit 12 uses the Y data S
7A, Cb data S7B and Cr data S7C are digital-analog converted to obtain Y signals S8A, Cb.
A signal S8B and a Cr signal S8C are obtained, and these are output to an external monitor for display.

Here, the configuration of the output synchronization generating circuit 42 is shown in FIG.
2 in which the same parts as those in FIG. 2 are assigned the same reference numerals, and the operation timing of the output synchronization generating circuit 42 is shown in FIG.
Shown in. When the vertical synchronization signal V1 (FIG. 3A), which is an interlaced signal of 1 field 312.5H, is supplied from the chroma decoder 6, this output synchronization generation circuit 42 supplies it to the reset timing generation circuit 20 and the latch circuit 21. , OR circuit 22, hold circuit 50 and switch SW1.

As shown in FIG. 3A, tuner switching is performed at timing T1, and tuner switching is completed at timing T2, and thereafter, a stable vertical synchronizing signal V1 is input to the output synchronization generating circuit 42. ing.

At the same time, the output sync generation circuit 42 inputs the horizontal sync signal H1 supplied from the chroma decoder 6 to the constant-magnification circuit 23. The constant-magnification circuit 23 uses the horizontal synchronizing signal H1.
The field synchronizing frequency is doubled, and the horizontal synchronizing signal H2 whose field frequency is doubled is sent to the input vertical synchronizing section counter 24, the output vertical synchronizing section counter 25, and the memory controller 8 in the subsequent stage.

The reset timing generating circuit 20 is configured to reset the count operation of the input vertical synchronizing section counter 24 for each vertical synchronizing signal V1 based on the supplied vertical synchronizing signal V1.

The input vertical synchronizing section counter 24 counts one section of the vertical synchronizing signal V1 by the supplied horizontal synchronizing signal H2, and the count value S20 is counted by the latch circuit 2.
Send to 1. The latch circuit 21 holds the supplied count value S20 during the section next to the section in which the count value S20 is counted, so that the count value S20 is held.
A count value S21 (FIG. 3 (B)) that outputs 20 during the section subsequent to the counted section is generated and sent to the hold circuit 50 and the switch SW1.

That is, as shown in FIG. 3 (B),
The count value S21 is a count value (3 which is obtained by counting one section of the vertical synchronization signal V1 by the original horizontal synchronization signal H1.
It is twice the value (625 lines) of 12.5 lines, as shown in FIG.
The count value S20 of the section A in (A) is the next section B.
Will be output.

The hold circuit 50 holds the supplied count value S21 for the next section,
The count value S50 that is output during the period next to the period output from the latch circuit 21 (see FIG. 3).
(C)) is generated and sent to the switch SW1.

The switch SW1 is adapted to switch its connection state based on a tuner switching start signal S41A and a tuner switching end signal S41B supplied from the CPU 41. That is, the connection state of the switch SW1 is switched to the latch circuit 21 side during the normal operation, and the count value S21 output from the latch circuit 21 is selected and sent to the 1/2 coefficient circuit 26.

In this state, the switch SW1 causes the tuner switching start signal S41, as shown in FIG. 3 (D).
When A is input, the connection state is held by the hold circuit 5
The count value S50 output from the hold circuit 50 is selected by switching to the 0 side and sent to the 1/2 coefficient circuit 26. Then, the switch SW1 turns on the vertical synchronizing signal pulse V.
The connection state is maintained until i5 is input, and when the vertical synchronization signal pulse Vi5 is input, the connection state is switched to the latch circuit 21 side and the count value S21 output from the latch circuit 21 is selected. And sends it to the 1/2 coefficient circuit 26.

The 1/2 coefficient circuit 26 is 1 / of the count value S21 or S50 output from the switch SW1.
The count value S51 obtained by multiplying by 2 (see FIG. 3) is obtained.
(E)) is sent to the comparator 27.

By the way, in the conventional output synchronization generating circuit 9, the count value S2 supplied from the latch circuit 21.
Since 1 is input to the comparator 27 via the 1/2 coefficient circuit 26, the count value S22 obtained by counting the vertical synchronization signal section C in which the cycle is disturbed by tuner switching is used as the comparator 2
Therefore, the intermediate vertical synchronizing signal pulse Vm4 was generated at the wrong timing of C / 2 (FIG. 9).

On the other hand, in the output synchronization generation circuit 42 of the present embodiment, the count value S5 output from the hold circuit 50 from the start timing of tuner switching to the generation timing of the vertical synchronization signal pulse Vi5.
By inputting 0 to the comparator 27 through the switch SW1 and the 1/2 coefficient circuit 26 in sequence, the vertical synchronizing signal section B immediately before the vertical synchronizing signal section C whose cycle is disturbed by tuner switching is counted and obtained. Since the count value S50 is input to the comparator 27, the intermediate vertical synchronizing signal pulse Vm4 is generated at the proper timing of B / 2.

On the other hand, the output vertical synchronization section counter 25
The input vertical synchronization section counter 24 has the same configuration as the input vertical synchronization section counter 24.
The section is counted, and the count value S23 is sent to the comparator 27.

The comparator 27 has a 1/2 coefficient circuit 26.
The count value S51 (FIG. 3 (E)) output from the output vertical synchronization section counter 25 is compared with the count value S51 and the count value S51 output from the output vertical synchronization section counter 25.
When it is determined that the two coincide with each other, the comparison output signal S52 for generating the pulse of the logic level "L" is generated and sent to the pulse width expansion circuit 28.

Since the comparison output signal S52 generates only a pulse having the same pulse width as the pulse width of the pulse generated by the horizontal synchronizing signal H2, the pulse width expansion circuit 2
Reference numeral 8 enlarges the pulse width of the pulse generated by the comparison output signal S52 to the pulse width of the pulse generated by the vertical synchronization signal V1, and sends the comparison output signal S53 obtained as a result to the OR circuit 22.

The OR circuit 22 generates a vertical synchronizing signal V3 having a field frequency doubled by taking the logical sum of the vertical synchronizing signal V1 and the comparison output signal S53 output from the pulse width expanding circuit 28. To the switch SW2.

The switch SW2 switches its connection state based on a tuner switching start signal S41A and a tuner switching end signal S41B supplied from the CPU 41. That is, the connection state of the switch SW1 is switched to the OR circuit 22 side during the normal operation, the vertical synchronization signal V3 output from the OR circuit 22 is selected, and the vertical synchronization signal V10 (FIG. 3) is selected.
(G)) is sent to the memory controller 8 in the subsequent stage.

In this state, the switch SW2 causes the tuner switching start signal S41 as shown in FIG.
When A is input, the connection state is changed to the vertical synchronization signal V1.
The vertical synchronizing signal V1 is selected by switching to the side and sent to the memory controller 8 as the vertical synchronizing signal V10 (FIG. 3 (G)). Then, the switch SW2 maintains the connection state until the tuner switching end signal S41A is input, and when the tuner switching end signal S41A is input, the connection state is switched to the OR circuit 22 side and the OR circuit 22 The output vertical synchronizing signal V3 is selected and sent to the memory controller 8 as the vertical synchronizing signal V10 (FIG. 3 (G)).

In this way, from the start timing of tuner switching to the end timing of tuner switching, the connection state of the switch SW2 is switched to the vertical synchronizing signal V1 side, and the vertical synchronizing signal V1 is kept unchanged as the vertical synchronizing signal V1.
By sending it to the memory controller 8 as 0 (FIG. 3 (G)), the intermediate vertical synchronizing signal Vm3 (FIG. 9 (B)) for doubling the field frequency is not generated, and the conventional output synchronization generating circuit 9, the intermediate vertical synchronizing signal pulse Vm3 and the vertical synchronizing signal pulse Vo do not occur in succession.

In the above configuration, the output synchronization generating circuit 4
2, the count value S50 output from the hold circuit 50 is switched to the switch S from the start timing of the tuner switching to the generation timing of the vertical synchronizing signal pulse Vi5.
A count value S50 obtained by counting the vertical sync signal section B immediately before the vertical sync signal section C whose cycle is disturbed by tuner switching by inputting it to the comparator 27 through the W1 and 1/2 coefficient circuits 26 sequentially. Can be input to the comparator 27, so that the intermediate vertical synchronizing signal pulse Vm4 can be generated at a proper timing.

Further, in the output synchronization generating circuit 42, the connection state of the switch SW2 is switched to the vertical synchronization signal V1 side from the tuner switching start timing to the tuner switching end timing, and the vertical synchronization signal V1 is kept as it is. It is possible to prevent the generation of the intermediate vertical synchronizing signal for doubling the field frequency by sending the intermediate vertical synchronizing signal pulse to the memory controller 8 as V10. Can be prevented from occurring in quick succession.

According to the above configuration, the time of one section of the input vertical synchronizing signal V1 is measured, and the intermediate vertical synchronizing signal pulse Vm is generated at the timing of 1/2 of the measured time. In the output synchronization generation circuit 40 that generates the vertical synchronization signal V10 having a field frequency doubled, even if the input vertical synchronization signal V1 is disturbed by the tuner switching, depending on the start and end timings of the tuner switching. Intermediate vertical sync signal pulse V
By adjusting the generation of m, the field frequency becomes 2
It is possible to correctly generate the double vertical synchronization signal V10,
Thus, the deterioration of the image quality of the displayed image can be avoided.

In the above-described embodiment, the reset timing generation circuit 20, the latch circuit 21, the input vertical synchronization section counter 24, the output vertical synchronization section counter 25, the 1/2 coefficient circuit 26, the comparator 27, as the generation means. Although the case where the pulse width expansion circuit 28 and the OR circuit 22 are applied has been described, the present invention is not limited to this, and the time interval at which each input pulse of the input synchronization signal composed of the input pulses sequentially generated at a predetermined timing is generated. It is possible to apply various other generation means for measuring and generating an output pulse at a timing based on the measured time interval to generate an output synchronization signal composed of the output pulse.

In the above embodiment, the case where the CPU 41 is applied as the detecting means has been described.
The present invention is not limited to this, and various other detecting means for detecting the discontinuity of the generation timing at which the input pulse is generated may be applied.

Further, in the above-described embodiment, the hold circuit 50, the switches SW1 and SW are used as the adjusting means.
Although the case where 2 is applied has been described, the present invention is not limited to this, and various other adjusting means for adjusting the generation timing of the output pulse based on the detection result of the detecting means may be applied.

Further, in the above-described embodiment, the case where the output synchronization generating circuit 42 is applied as the synchronization signal converting circuit has been described, but the present invention is not limited to this, and various other synchronizing signal converting circuits are applied. You may do it.

Further, in the above-described embodiment, the case where the television receiver 40 is applied as the image display device has been described, but the present invention is not limited to this, and various other image display devices may be applied. Is also good.

[0073]

As described above, according to the present invention, the time interval at which each input pulse of the input synchronizing signal composed of the input pulse sequentially generated at a predetermined timing is measured, and based on the measured time interval. In a synchronization signal conversion circuit that generates an output synchronization signal composed of output pulses by generating output pulses at the timing, the discontinuity of the generation timing at which the input pulse is generated is detected, and the output pulse of the output pulse is detected based on the detection result. The output synchronization signal can be correctly generated by adjusting the generation timing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention.

FIG. 2 is a block diagram showing a configuration of an output synchronization generation circuit.

FIG. 3 is a timing chart showing the operation timing of the output synchronization generation circuit.

FIG. 4 is a block diagram showing a configuration of a conventional television receiver.

FIG. 5 is a timing chart used to explain vertical synchronization signals of standard PAL and double speed PAL.

FIG. 6 is a timing chart for explaining a method of generating an output vertical synchronizing signal.

FIG. 7 is a block diagram showing a configuration of a conventional output synchronization generating circuit.

FIG. 8 is a timing chart showing the operation timing of a conventional output synchronization generation circuit.

FIG. 9 is a timing chart for explaining the operation of the conventional output synchronization generating circuit at the time of tuner switching.

[Explanation of symbols]

1, 40 ... Television receiver, 3 ... Operation unit, 4,
41 ... CPU, 5 ... Tuner, 9, 42 ... Output synchronization generation circuit, 21 ... Latch circuit, 22 ... OR circuit,
24 ... Input vertical sync section counter, 25 ... Output vertical sync section counter, 27 ... Comparator, 50 ... Hold circuit.

Claims (8)

[Claims] 1. By measuring a time interval at which each of the input pulses of an input synchronizing signal composed of input pulses sequentially generated at a predetermined timing is generated, and an output pulse is generated at a timing based on the measured time interval. Generating means for generating an output synchronizing signal composed of the output pulse, detecting means for detecting discontinuity in the generation timing of the input pulse, and generation timing of the output pulse based on the detection result of the detecting means And a adjusting means for adjusting the sync signal converting circuit. 2. The generating means successively generates the output pulse at a predetermined timing between the generation timing of the input pulse and the generation timing of each of the input pulses to multiply the field frequency of the input synchronization signal by a predetermined frequency. The synchronization signal conversion circuit according to claim 1, wherein the output synchronization signal is generated. 3. By measuring a time interval at which each of the input pulses of an input synchronizing signal consisting of input pulses sequentially generated at a predetermined timing is measured, and an output pulse is generated at a timing based on the measured time interval. Generating means for generating an output synchronizing signal composed of the output pulse, detecting means for detecting discontinuity in the generation timing of the input pulse, and generation timing of the output pulse based on the detection result of the detecting means An image display device, comprising: an adjusting means for adjusting the image signal and a display means for displaying an image signal supplied from the outside based on the output synchronizing signal. 4. The generating means successively generates the output pulse at a predetermined timing between the generation timing of the input pulse and the generation timing of each input pulse, thereby multiplying the field frequency of the input synchronization signal by a predetermined frequency. The image display device according to claim 3, wherein the output synchronizing signal is generated. 5. By measuring a time interval at which each of the input pulses of an input synchronizing signal consisting of input pulses sequentially generated at a predetermined timing is measured, and an output pulse is generated at a timing based on the measured time interval. A first step of generating an output synchronization signal composed of the output pulse, a second step of detecting a discontinuity of generation timing of the input pulse, and generation of the output pulse based on the detection result. And a third step of adjusting the timing. 6. In the first step, the field frequency of the input synchronizing signal is changed by sequentially generating the output pulse at a predetermined timing between the generation timing of the input pulse and the generation timing of each input pulse. The synchronizing signal conversion method according to claim 5, wherein the output synchronizing signal multiplied by a predetermined number is generated. 7. By measuring the time interval at which each of the input pulses of the input synchronization signal consisting of the input pulse sequentially generated at a predetermined timing is measured, and the output pulse is generated at a timing based on the measured time interval. A first step of generating an output synchronizing signal composed of the output pulse, a second step of detecting a discontinuity in the generation timing of the input pulse, and the output based on the detection result of the detecting means. An image display method comprising: a third step of adjusting a pulse generation timing; and a fourth step of displaying an image signal supplied from the outside based on the output synchronizing signal. 8. In the first step, the field frequency of the input synchronizing signal is changed by sequentially generating the output pulse at a predetermined timing between the generation timing of the input pulse and the generation timing of each input pulse. The image display method according to claim 7, wherein the output synchronizing signal multiplied by a predetermined number is generated.