JP2003167845A - Data storing device and data transferring system using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To write the data to an external circuit by using a microcontroller not comprising a data writing function, as it is. <P>SOLUTION: An enable circuit 121 generates an enable signal EB on the basis of the 16th bit A15 of an address bus 140 and a signal value of a read-out control signal line 150. A decoder 122 generates an address from the 9th bit A8 - the 15th bit A14 of the address bus 140. A group of registers 123 write the signal values of the 1st bit A0 the 8th bit A7 of the address bus 140 to the resistor corresponding to the address when the enable signal EB is 'effective'. According to this invention, the read-out signal, the writing address and the writing data can be transmitted to the external circuit 120 from the microcontroller 110. Accordingly, the data can be written to the external circuit 120 without using a writing control signal line. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device for transmitting data using a bus and a data transmission system using the same.

[0002]

2. Description of the Related Art Conventionally, a technique using a bus has been known as a technique for performing data transmission within the same circuit board or data transmission within the same system.

For example, when data is transmitted between an arithmetic processing circuit (microcontroller or the like) and an external memory (random access memory or the like), the arithmetic processing circuit and the external memory are connected to a data bus and an address bus. To be done. Further, the arithmetic processing circuit and the external memory are connected by a read control signal line and a write control signal line.

When the arithmetic processing circuit reads data from the external memory, the arithmetic processing circuit outputs the read address on the address bus. When the read address is input from the address bus, the external memory outputs the storage data corresponding to this address on the data bus. After that, the arithmetic processing circuit activates the read control signal and reads the data on the data bus. The read control signal allows the external memory to know that the data has been read.

On the other hand, when writing data from the arithmetic processing circuit to the external memory, the arithmetic processing circuit outputs the write address on the address bus and the write data on the data bus, and then outputs the write control signal. To activate. When the external memory detects that the write control signal is activated, the external memory writes the data received from the data bus to the storage area corresponding to the address received from the address bus.

As an arithmetic processing circuit, there is known an arithmetic processing circuit that is not configured to write data to an external memory, that is, one that is configured to only read data from the external memory. This is because data is not written when the external memory is a ROM (Read Only Memory).

As a matter of course, the arithmetic processing circuit that does not write data does not have the function of generating and outputting the write control signal. That is, the interface of such an arithmetic processing circuit can be connected to the address bus, the data bus and the read control signal line, but cannot be connected to the write control signal line.

[0008]

In a system equipped with an arithmetic processing circuit such as a microcontroller, it is sometimes desired to expand the function by replacing or adding an external circuit. Further, due to such function expansion, there is a case where it is desired to change a system that does not write data from the arithmetic processing circuit to the external memory to a system that can perform such data writing.

However, as described above, the arithmetic processing circuit that does not write data to the external circuit does not have a function of generating and outputting a write control signal.
It could not be used in a system that writes data. Therefore, conventionally, in order to change the system so that the data can be written in the external memory, it is necessary to replace the expensive arithmetic processing circuit itself.

For this reason, an arithmetic processing circuit that does not write data to an external circuit is used as it is,
There has been a strong demand for a technology that enables data writing to an external memory or the like.

[0011]

A data storage device according to a first invention inputs n-bit information including an operation mode bit, an address bit and a data bit from an address bus, and a read control signal. Input means for inputting from a control signal line, enable generating means for generating an enable signal using an operation mode bit and a read control signal, a decoding circuit for generating an address from an address bit, and an enable signal being'valid ' At this time, a storage means for storing the data bit corresponding to the address is provided.

According to this data storage device, the read control signal, the address and the write data can be received from the address bus. Therefore, data can be written to the data storage device without using the write control signal line.

A data transmission system according to the second invention is
Operating mode bits, address bits and data
Output n-bit information including bits on the address bus,
Further, an arithmetic processing unit for outputting a read control signal to the control signal line, an input means for inputting n-bit information from the address bus and a read control signal from the control signal line, an operation mode bit and the read control signal Enable generating means for generating an enable signal using, a decoding means for generating an address from an address bit, and a data data corresponding to the address when the enable signal is'valid '.
A data storage device having storage means for storing bits.

According to this data transmission system, by using the address bus, from the arithmetic processing unit to the data storage unit,
A read control signal, a write address and write data can be sent. Therefore, data can be written to the data storage device without using the write control signal line.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. It should be noted that, in the drawings, the size, shape, and arrangement relationship of each constituent component are only schematically illustrated to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. .

First Embodiment The first embodiment of the data storage device and the data transmission system according to the present invention will be described below.

FIG. 1 is a block diagram schematically showing the configuration of a data transmission system 100 according to this embodiment.

As shown in FIG. 1, this system 100
Is a microcontroller 11 as an arithmetic processing circuit.
0, an external circuit 120 as a data storage device (external memory, etc.), a data bus 130, an address bus 140, and a read control signal line 150.

The microcontroller 110 includes a processor core 111, a ROM (Read Only Memory) 112, and an RA.
An M (Random Access Memory) 113, an internal bus 114, and an external memory interface 115 are provided.

The processor core 111 includes an external circuit 120.
Data is not written to the external circuit 120, but processing such as reading data from the external circuit 120 is performed.

The ROM 112 stores programs for the processor core 111 to execute processing.

The RAM 113 temporarily stores the data being processed by the processor 111.

The internal bus 114 is used for the processor core 11.
1, used for transmission of programs and data among the ROM 112, the RAM 113, and the external memory interface 115.

The external memory interface 115 has an internal bus 114, a data bus 130, and an address bus 140.
And a read control signal line 150. In this embodiment, the data bus 130 is 8
The signals of each bit are represented by D0 to D7. Further, the address bus 140 has 16 bits, and signals of respective bits are represented by A0 to A15.

The external circuit 120 is an enable circuit 12.
1, a decoder 122, a register group 123, and an interface 124.

The enable circuit 121 inputs the most significant bit A15 (operation mode bit) of 16-bit information from the address bus 140 via the interface 124, and reads the read control signal_RD from the read control signal line 150.
Enter. When the read control signal _RD is "0" and the address signal A15 is "1", the enable circuit 1
21 determines that the write mode is set, and sets the enable signal EB to "valid". On the other hand, when the signals _RD and A15 have other values, the enable circuit 121 determines that the read mode is set, and invalidates the enable signal EB. Here, the enable signal EB is output to the register group 123.
It is a signal that permits writing of data to, and is substantially used as a write signal.

The decoder 122 inputs signals A8 to A14 (address bits) of the 9th to 15th bits from the address bus 140. Then, the decoder 122
These signals A8 to A14 are decoded into addresses for specifying any of the registers in the register group 123.

The register group 123 includes, for example, 128 8-bit registers (not shown). The register group 123 inputs signals A0 to A7 (data bits) of the first to eighth bits of 16-bit information from the address bus 140. And the register group 123 is
When the enable signal EB is “valid”, the decoder 122
The values of the signals A0 to A7 are written in the register specified by. On the other hand, when the enable signal EB is “invalid”, the storage data of the register specified by the decoder 122 is output to the data bus 130. Each register has 8 bits because the data bus 130 has 8 bits. However, when the external circuit 120 is mounted on a system having a 16-bit data bus, only one of the upper 8 bits or the lower 8 bits is used, and the other 8 bits are fixed to an undefined value (high impedance). Good.
Also, the same 8-bit signal may be output for the upper 8 bits and the lower 8 bits.

The interface 124 has a data bus 13
0, address bus 140 and read control signal line 150. As can be seen from the above description, the data bus 1
30 is a register group 1 via the interface 124
23 is connected. In the address bus 140, bits A0 to A7 are registered in the register group 1 via the interface 124.
23, the bits A8 to A14 are connected to the decoder 122, and the bit A15 is connected to the enable circuit 121. The read control signal line 150 is also connected to the enable circuit 121 via the interface 124.

Data bus 130 and address bus 14
As 0, a normal bus is used. These buses 1
30 and 140 may be connected to other circuits and devices.

Next, the data transmission system 1 shown in FIG.
The operation of 00 will be described with reference to the timing chart of FIG. The sequence of FIG. 2 is basically a read sequence.

In this data transmission system 100,
Writing of data to the external circuit 120 is performed as follows. As described below, in this embodiment, the write operation is executed by using the operation sequence of the read mode of the microcontroller 110 as it is.

First, the timing T1 of the system clock
Then, the microcontroller 110 changes the address bus 14
The 16-bit information A0 to A15 is output to 0. In this embodiment, the value of the most significant bit A15 of the address bus 140 is set to "1" when executing the write mode. Also, in the 9th to 15th bits A8 to A14,
An address for specifying one register of the register group 123 is stored. Further, the first to eighth bits A0 to A7 of the address bus 140 store 8-bit data to be written in the register.

The external circuit 120 reads the 16-bit information A0 to A15 from the address bus 140. As described above, the most significant bit A15 of the 16-bit information A0 to A15 is input to the enable circuit 121 and
The bits to the fifteenth bits A8 to A14 are decoded by the decoder 122 into data for specifying the registers, and the first to eighth bits A0 to A7 are input to the register group 123.

Since the write mode is being executed here, 16-bit information A0 to A15 is placed on the address bus 140.
Is output, the external circuit 120 does not output data on the data bus 130. However, as mentioned above, since the microcontroller 110 is executing the read mode operation sequence, the
After a predetermined delay time from the output of the 6-bit information A0 to A15 (near the timing T3 in the example of FIG. 2), the data bus 1
It is determined that the data is output on 30. And
The macro controller 110 uses the system clock T4.
→ During T5, the data on the data bus 130 is read and the read signal _RD is made active (that is, “0”).

The enable circuit 121 in the external circuit 120
Enables the enable signal EB to be “valid” (that is, “1”) when the read signal _RD is active and the value of the bit A15 is “1”. Here, since the value of the bit A15 is “1”, the enable signal is provided during the period when the read signal _RD is active (that is, the period of T4 → T5).
EB becomes'valid '.

The register specified by the decoder 122 is
At the rising timing of the enable signal EB (time T4 in FIG. 2), the first bit to the eighth bit A0 to A7 of the 16-bit information A0 to A15 are stored.

After that, the timing T of the system clock
At 6, the microcontroller 110 outputs the next 16-bit information A0-A15 on the address bus 140.
Then, the write operation similar to the operation at the timings T1 to T5 is repeated.

As described above, in the system 100 according to this embodiment, the write operation sequence of the microcontroller 110 is the same as the read operation sequence of the conventional microcontroller. That is, by using the above 16-bit information as the transmission information of the address bus 140, the read operation sequence
Data can be written to the external circuit 120. Therefore, even if the microcontroller 110 does not have the function of writing to the external circuit, by installing the external circuit 120 according to this embodiment in the system 100, data writing can be performed.

Next, the operation of reading data from the external circuit 120 will be described. As will be described below, also when reading data from the external circuit 120, the microcontroller 110 performs exactly the same sequence as the write operation of this embodiment, that is, the same sequence as the read operation sequence shown in FIG. To use.

First, the timing T1 of the system clock
Then, the microcontroller 110 changes the address bus 14
The 16-bit information A0 to A15 is output to 0. In this embodiment, when the read mode is executed, the value of the most significant bit A15 of the 16-bit information is set to "0".
Further, as in the case of the write operation, the 9th bit to the 1st bit
Addresses for specifying one register of the register group 123 are stored in the 5 bits A8 to A14. Here, in the case of the read operation, it is not necessary to store the data in the first bit to the eighth bit A0 to A7 of the 16-bit information.

The external circuit 120 reads 16-bit information A0 to A15 from the address bus 140. As described above, the most significant bit A15 of the 16-bit information A0-A15 is input to the enable circuit 121 and the ninth bit-
The fifteenth bits A8 to A14 are decoded by the decoder 122 into data for specifying the register. Where the first
Bits to eighth bits A0 to A7 are input to the register group 123, but are not used in the read operation.

At this point, the read control signal _RD is inactive (that is, "1"), so the enable signal EB is also "invalid" (that is, "0"). Enable signal EB
Is invalid, the register specified by the decoder 122 outputs the stored value. This stored value is output onto the data bus 130 via the interface 124.

As in the case of the above-described write operation, the microcontroller 110 outputs the 16-bit information A0 to A15 after a predetermined delay time (timing T in the example of FIG. 2).
3), it is determined that data has been output onto the data bus 130. Then, the macro controller 110 maintains the data bus 130 during the period T4 → T5 of the system clock.
The above data is read, and the read signal _RD is made active (that is, "0"). The read data is stored in the RAM 113, for example.

Here, since the most significant bit A15 of the 16-bit information is "0", the enable signal EB does not become "valid" even if the read signal _RD becomes active.
Therefore, the register specified by the decoder 122 is
The first to eighth bits A0 to A7 of 16-bit information are not stored.

After that, the system clock timing T
At 6, the microcontroller 110 switches the address bus 1
The following 16-bit information A0 to A15 is output on the 40.
Then, the read operation similar to the operation at the timings T1 to T5 is repeated.

As described above, in the system 100 according to this embodiment, the read operation sequence of the microcontroller 110 is also the same as the read operation sequence of the conventional microcontroller.

As described above, in the system 100 according to the present embodiment, both the write operation and the read operation can be executed in exactly the same operation sequence as the conventional read operation sequence. Therefore, according to this embodiment, both the write operation and the read operation can be performed by using the microcontroller having no write function with respect to the external circuit.

In the write operation, the microcontroller 110 does not use the data bus 130. Therefore, even when the data bus 130 is used for communication between other circuits, if the address bus 140 is not used, The controller 110 can write data. For example, DMA (Direct Memo) between other circuits
While performing (ry access) transfer, the microcontroller 110 can write data to the external circuit 120.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. 2 and 3.

FIG. 3 is a block diagram schematically showing the configuration of the data transmission system 300 according to this embodiment.

In FIG. 3, the components designated by the same reference numerals as in FIG. 1 indicate the same components as in FIG. 1, respectively.

As shown in FIG. 3, the external circuit 310 is
The interface 124, the register circuit 311, the verification circuit 312, and the multiplexer 313 are provided. Here, the register circuit 311 has the same enable circuit 121 and decoder 1 as the external circuit 120 of the first embodiment.
22 and a register group 123.

The verification circuit 312 inputs the storage data from the register specified by the decoder 122.
Then, the verification data of this stored data is generated and output. The verification data is, for example, data used in a verification method such as checksum and parity.

The multiplexer 313 inputs the storage data of the register specified by the decoder 122 from one input port, and the verification data from the other input port. Further, the multiplexer 313
Is the most significant bit A of 16-bit information as a selection signal.
Enter 15. Then, the multiplexer 313 outputs the verification data when the signal value of the bit A15 is “1”,
When the signal value of bit A15 is "0", the data stored in the register is output.

Next, the data transmission system 3 shown in FIG.
The operation of 00 will be described. The operation sequence of the microcontroller 110 in this embodiment is exactly the same as in the case of the first embodiment (see FIG. 2).

First, the operation of writing data to the external circuit 310 will be described.

First, the system clock timing T
1, the microcontroller 110 sets the address bus 1
16-bit information A0 to A15 is output to 40. Similar to the write operation in the first embodiment, the value of the most significant bit A15 of 16-bit information is set to "1", and the ninth bit to the fifteenth bit A8 to A14 have an address for specifying a register. In addition, 8-bit write data is stored in the first to eighth bits A0 to A7.

The external circuit 310 reads 16-bit information from the address bus 140. Of the 16-bit information, the most significant bit A15 is input to the enable circuit 121 and the multiplexer 313, and the 9th to 15th bits are input.
Bits A8 to A14 are input to the decoder 122, and
The first to eighth bits A0 to A7 are the register group 123.
Entered in.

As in the first embodiment, the macro controller 110 operates in the period T4 → T5 of the system clock,
The read signal _RD is made active (that is, "0"). Then, the enable circuit 121 sets the enable signal EB to “valid” while the read signal _RD is active (that is, the period of T4 → T5).

The register specified by the decoder 122 is
The first to eighth bits A0 to A7 of the 16-bit information are stored at the rising timing of the enable signal EB. At this time, this stored data is output as it is,
It is input to the verification circuit 312. The verification circuit 312 outputs the verification data as described above.

Since the signal value of the bit A15 is "1", the multiplexer 313 selects and outputs this verification data. This verification data is output on the data bus 130 via the interface 124.

As described above, the microcontroller 1
10 executes a sequence of read operations even in the write operation. Therefore, the data bus 130
The above verification data is input to the microcontroller 110.

As described above, in the system 300 according to this embodiment, when data is written in the external circuit, the verification result of this write data can be output to the data bus 130.

Next, the operation of reading data from the external circuit 310 will be described. Even in this operation, the microcontroller 110 performs the same sequence as the conventional read operation sequence as shown in FIG.

First, the system clock timing T1
Then, the microcontroller 110 changes the address bus 14
The 16-bit 16-bit information A0 to A15 is output to 0. At this time, the value of the most significant bit A15 of the 16-bit information is set to "0". Further, similar to the first embodiment, the ninth bit to the fifteenth bit A8 to A14 store an address for specifying one register of the register group 123, and the first bit of 16-bit information. ~ Eighth
No data is stored in bits A0 to A7.

The external circuit 310 reads this 16-bit information from the address bus 140. Of the 16-bit information, the most significant bit A15 is input to the enable circuit 121 and the multiplexer 313, and the ninth to fifteenth bits A8 to A14 are decoded by the decoder 122 into data for specifying the register. The specified register outputs the stored data to the multiplexer 313.

Here, since the most significant bit A15 is "0", the multiplexer 313 selects the storage data.

Thereafter, as in the case of the first embodiment, the data stored in the register specified by the decoder 122 is stored in the multiplexer 313 and the interface 12.
4 to the data bus 130. Then, this stored data is read into the macro controller 110 from the data bus 130.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a block diagram schematically showing the configuration of the data transmission system 400 according to this embodiment.

In FIG. 4, the components designated by the same reference numerals as in FIG. 1 indicate the same components as in FIG. 1, respectively.

As shown in FIG. 4, the data transmission system 400 according to this embodiment includes a microcontroller 110, an external dedicated controller 410 and a control device 4.
Equipped with 20.

The external dedicated controller 410 includes a register circuit 411, a control circuit 412 and an interface 41.
3,414.

The register circuit 411 includes an enable circuit 121, a decoder 122, and a register group 123 similar to the external circuit 120 of the first embodiment. In this embodiment, each register (not shown) in the register group 123 has a command received from the microcontroller 110 or the microcontroller 11
The status information sent to 0 is stored. In this embodiment, these commands and status information are
8 bits.

The control circuit 412 executes the command read from the register circuit 411. With the execution of this command, the control circuit 412 transmits the control signal CTR to the control device 420 and receives the status signal ST from the control device 420. The control circuit 412 uses the received status signal ST as status information to register group 1
Write to register in 23. Further, the control circuit 412
Sends an interrupt request signal IR to the microcontroller 110.
While sending Q, it receives an interrupt response signal IAK from this microcontroller 110.

The interface 413 is the data bus 13
0, the address bus 140 and the read control signal line 150, and additionally, the control signal line 430 for the interrupt request signal IRQ and the control signal line 4 for the interrupt response signal IAK.
Connected to 40. That is, these signal lines 130,
Signals are transmitted and received between the interfaces 115 and 413 using 140, 150, 430 and 440.

The interface 414 has a control signal line 45.
At 0,460, it is connected to the control device 420. The control signal line 450 is used for receiving the status signal ST, and the control signal line 460 is used for transmitting the control signal CTR.

The control device 420 includes control signal lines 450, 4
60 to send status signal ST and control signal CT
An interface 421 for receiving R is provided. The control device 420 is controlled by the external dedicated controller 410 by transmitting and receiving these signals ST and CTR.

The operation when the microcontroller 110 writes data to the register circuit 411 is the same as that of the first embodiment. However, in this embodiment,
At the time of writing, the command is stored in the first to eighth bits A0 to A7 of the 16-bit information. That is, in the write operation of this embodiment, the register circuit 411
Command is written to. This command is read by the control circuit 412 and executed. As a result, the control signal CTR is transmitted from the control circuit 412 to the control device 420. The control of the control device 420 is executed by the control signal CTR.

The control device 420 transmits the status signal ST generated according to the control content to the control circuit 412. The control circuit 412 changes the received status signal ST to
Write to a predetermined register in the register circuit 411.
The status signal ST stored in the register is a read operation similar to that of the system 100 according to the first embodiment.
It is read by the microcontroller 110.

Further, the control circuit 412 uses the status signal
When the ST value is a predetermined value, the microcontroller 110
An interrupt request signal IRQ is transmitted to When the microcontroller 110 recognizes the reception of the signal IRQ,
The interrupt response signal IAK is transmitted to the control circuit 412, and a command for interrupt control is issued by the register circuit 41 by the same operation as the write operation of the first embodiment.
Write to 1. This command is read and executed by the control circuit 412. As a result, the control circuit 41
2 can perform interrupt control.

According to the data transmission system 400 of this embodiment, it is possible to write a command to the external dedicated controller 410 using only the address bus 140. Therefore, it is possible to control the control device 420 by using a microcontroller that does not have a write function for an external circuit and has an interrupt function.

Further, since the microcontroller 110 does not use the data bus 130 in the write operation, control is performed if the address bus 140 is not used even when the data bus 130 is used for communication between other circuits. The device 420 can be controlled. For example, the microcontroller 110 can write a command in the register circuit 411 even while performing DMA (Direct Memory Access) transfer between other circuits. However,
In this case, since the data bus 130 is used for the DMA transfer, the status information cannot be transmitted from the register circuit 411 to the microcontroller 110.

In addition, since the interrupt request signal IRQ and the interrupt response signal IAK are used, the control device 420 can be quickly controlled.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described with reference to FIG.

This embodiment is an example in which the arithmetic processing unit according to the present invention is applied to a program development board, and the data storage unit according to the present invention is applied to a ROM emulator.

FIG. 5 shows a system 5 according to this embodiment.
It is a block diagram which shows the structure of 00 roughly.

As shown in FIG. 5, this system 500
Includes a program development board 510, a ROM emulator 520, a program debugger 530, and connection cables 540 and 550.

The program development board 510 includes a processor 511, a RAM 512, and a ROM socket 513.
And an internal bus 514.

The processor 511 writes data to the program debugger 530 and the program debugger 5
Processing such as reading data from 30 is performed.

The RAM 512 stores the program debugger 53.
The data to be written to 0 and the data read from the program debugger 530 are temporarily stored.

The ROM socket 513 is used for the connection cable 5
40 is used to connect 40 to internal bus 514.

The internal bus 514 is a processor 511, R
It is used for transmitting programs and data among the AM 512, the ROM socket 513, and the interface 515.

The interface 515 is an internal bus 514.
Is an input / output circuit that connects the connection cable 550 with the connection cable 550.

The ROM emulator 520 stores the program executed by the processor 511. The ROM emulator 520 sends this program to the processor 511 and the like via the interface 521, the connection cable 540, the ROM socket 513, and the internal bus 514. Further, the ROM emulator 520 has an internal bus 51
4, debug data and the like are received from the processor 511 and the like via the ROM socket 513, the connection cable 540 and the interface 521. In this embodiment, the ROM emulator 520 and the processor 511 are used.
The present invention is applied to data transmission / reception with and. For this reason,
The ROM emulator 520 includes the enable circuit 121 and the decoder 12 of the external circuit 120 according to the first embodiment.
2 and circuits corresponding to the register group 123.

The program debugger 530 is a development tool for debugging a program such as an application program. As the program debugger 530, for example, a personal computer or the like is used. Here, even when other development tools are used instead of the program debugger 530, the system according to this embodiment can be applied. Program debugger 530
Is connected to the connection cable 550 at the interface 531.

The connection cable 540 is the ROM socket 5
13 and the ROM emulator 520 are connected. As described above, the present invention is applied to data transmission / reception between the ROM socket 513 and the ROM emulator 520.
Therefore, the connection cable 540 includes the data bus, the address bus, and the read control signal line according to the present invention.

The connection cable 550 connects the interface 515 of the program development board 510 and the interface 531 of the program debugger 530 as described above. The program debugger 530 is generally configured to be able to write and read data, and therefore, it is not necessary to apply the present invention to data transmission / reception to / from the program debugger 530 via the connection cable 550. . However, it is possible to apply the present invention.

The specific operation of this embodiment, that is, the program development board 510 and the ROM emulator 52
The specific operation when transmitting / receiving data to / from 0 is the same as that in the first embodiment, and thus the description thereof is omitted.

When developing a program using the program development board 510, conventionally, the ROM socket 513 has been used.
, EEPROM (Electrically Erasable Programmabl
e Read Only Memory) was set. EEPRO
The program written in M is sent to the program debugger 530 under the control of the processor 511, and is executed by the program debugger 530. And if you find a bug or other inconvenience by debugging,
Each time it is discovered, the developer sets the EEPROM to the ROM socket 5
It was removed from No. 13, and the program in the EEPROM was rewritten. Such rewriting of the EEPROM has been one of the causes of lowering the efficiency of program development.

On the other hand, in the system according to this embodiment, the ROM emulator 520 is connected to the ROM socket 513. The ROM emulator 520 is
The program can be changed without the troublesome rewriting work as in the case of the EEPROM. However, the normal program development board 510 is
It is not configured to be able to send a write control signal from the etc. to the ROM socket 513. Therefore, the normal program development board 510 is
No data can be written to 20. However, in order to improve the efficiency of the debugging work, it is desirable to be able to write the data related to debugging from the program development board 510 to the ROM emulator 520.

In this embodiment, the ROM socket 51
The present invention is applied to data transmission / reception between the ROM 3 and the ROM emulator 520. Therefore, it is possible to transmit and write data to the ROM emulator 520 by using the conventional program development board 510 as it is. As a result, the degree of freedom in debugging work is improved, and the debugging work is made more efficient.

[0104]

As described in detail above, according to the present invention, it is possible to write data to an external memory or the like by directly using an arithmetic processing unit that does not write data to an external circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission system according to a first embodiment.

FIG. 2 is a timing chart showing an operation of the data transmission system according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a data transmission system according to a second embodiment.

FIG. 4 is a block diagram showing a configuration of a data transmission system according to a third embodiment.

FIG. 5 is a block diagram showing a configuration of a data transmission system according to a fourth embodiment.

[Explanation of symbols]

100 data transmission system 110 microcontroller 111 processor core 112 ROM 113 RAM 114 internal bus 115 External memory interface 120 external circuit 121 enable circuit 122 decoder 123 registers 124 interface 130 data bus 140 address bus 150 read control signal line

Claims (9)

[Claims] 1. Input means for inputting n-bit information including an operation mode bit, an address bit and a data bit from an address bus and inputting a read control signal from a control signal line, and an operation mode bit. Enable generation means for generating an enable signal using the read control signal, means for generating an address from the address bit, and the data data corresponding to the address when the enable signal is'valid '. A data storage device comprising: a storage unit that stores a bit. 2. The storage means outputs a data bit previously stored in a storage area corresponding to the address to a data bus when the enable signal is “invalid”. The data storage device according to 1. 3. Verification means for generating verification data of data bits stored in said storage means when said enable signal is'valid ', and said verification data for said verification data when said enable signal is'valid'. 2. The data according to claim 1, further comprising: a selection unit that outputs the data bit to a data bus and outputs the data bit previously stored in the storage unit to the data bus when the enable signal is “invalid”. Storage device. 4. The data storage device according to claim 1, further comprising control means for reading the storage data from the storage means and executing a command corresponding to the storage data. 5. An arithmetic processing unit which outputs n-bit information including an operation mode bit, an address bit and a data bit on an address bus and outputs a read control signal to a control signal line, and the address. Input means for inputting the n-bit information from the bus and inputting the read control signal from the control signal line; enable generating means for generating an enable signal using the operation mode bit and the read control signal; A data storage device having a decoding means for generating an address from an address bit and a storage means for storing the data bit in correspondence with the address when the enable signal is'valid '. And data transmission system. 6. The storage means outputs a data bit previously stored in a storage area corresponding to the address to a data bus when the enable signal is “invalid”. The data transmission system described in. 7. Verification means for generating verification data of the bit stored in said storage means when said enable signal is'valid ', and said verification data for said data when said enable signal is'valid'. 6. The data transmission according to claim 5, further comprising: a selection unit that outputs the data bit stored in the storage unit to the data bus when the enable signal is “invalid”. system. 8. The data transmission system according to claim 5, further comprising control means for reading the storage data from the storage means and executing a command corresponding to the storage data. 9. The data transmission system according to claim 5, wherein the arithmetic processing unit is a program development board, and the data storage unit is a ROM emulator.