JP2003167783A - Memory protect control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems in a conventional memory protect control device that it requires the set to a write through mode because a memory protect function cannot be often realized in the use of a cache in a write back mode, which causes a reduction in memory access speed and the specification limitation for a system to a set designer. <P>SOLUTION: This device comprises a memory control part having a protect function capable of monitoring and protecting the memory access not only between a microcomputer part and a memory but also between a CPU part and the cache within the microcomputer. According to such a structure, the memory protect function can be realized even in the use of the cache. Further, since the write back mode can be used, compared with a conventional system only usable in the write-through mode, the access speed can be improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control unit in a semiconductor integrated circuit, and more particularly to a memory protect control device.

[0002]

2. Description of the Related Art Conventionally, as a device of this type, an address bus between a microcomputer unit and a memory, a chip select, a read, There is a device that monitors a control signal such as a write and realizes memory protection against unauthorized memory access.

FIG. 3 is a block diagram showing the configuration of a conventional memory protect control device. A microcomputer unit 30 including a CPU unit 301, an interrupt control unit 302, and a cache 303
4, a memory control unit 305 having a protect function capable of monitoring and preventing access to a certain memory space, outputting a notification signal 307 to the microcomputer unit 304 and generating an interrupt, and a memory 306. System.

Next, the operation will be described. CPU unit 30
When an illegal memory access satisfying the protection condition occurs from 1, the memory control unit 305 stops the access and simultaneously outputs a notification signal 307 for notifying the illegal memory access to the microcomputer unit 304 to generate an interrupt.

[0005]

However, in the conventional device, when the memory protect function is realized by using the cache, if the write access protect is set in a certain memory space and the data cache is used in the write back mode. To do. After that, when a write access is made to the protected area, only the data in the cache is rewritten at both the cache hit and the miss hit. At the same time, since the control signal for notifying the illegal memory access is not output to the microcomputer unit and the interrupt does not occur, there are cases where the memory protect function cannot be realized. As a result, when the data cache is used, it is necessary to set the write-through mode in order to realize the memory protect function, which causes a problem that the memory access speed is lowered, and the set designer is restricted by the system specifications.

The present invention solves the above-mentioned conventional problem. When data in a protected memory space is entered in a cache and an access to the cache occurs, the cache is accessed. It is possible to implement a memory protect function even if the cache is used in the write-back mode because it is possible to generate a control signal notifying the illegal memory access to the microcomputer unit and generate an interrupt without performing the operation. The purpose is to provide.

[0007]

In order to achieve this object, the present invention provides a CPU unit, an interrupt control unit, a microcomputer unit including a cache, a memory, and a CPU between the microcomputer unit and the memory and in the microcomputer unit. And a memory control unit having a protect function capable of monitoring and protecting memory access between the unit and the cache. Further, the memory control unit outputs a control signal for notifying the microcomputer unit at the time of illegal memory access, and performs control to terminate the execution program that caused the illegal memory access.

With this configuration, even if the CPU section accesses the entry data of the protected cache, the access to the corresponding entry data is prevented, and an illegal memory access is made to the microcomputer section by the notification signal of the memory control section. Is issued, an interrupt is generated, the execution program can be terminated, and a system down can be prevented. Further, as a result, the memory protect function can be realized even when the cache is used in the write-back mode, so that the memory access speed can be improved as compared with the conventional system which can be used only in the write-through mode.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described with reference to the drawings. In FIG. 1, a CPU unit 101, an interrupt control unit 102, a microcomputer unit 104 including a cache 103 and an access to a certain memory space can be monitored and prevented, and a notification signal 107 to the microcomputer unit can be output to generate an interrupt. A memory control unit 105 having a different protection function and a memory 106 are further provided.

The operation of the memory protect control device of this embodiment having the above-described structure will be described below. When the CPU section 101 makes an illegal memory access that satisfies the protection setting conditions of the access prohibited area and the access cycle, the memory control section 105 stops the access. As a target memory whose access is stopped, not only the external memory 106 seen from the microcomputer unit 104 but also the cache 103 inside the microcomputer unit 104 can be stopped. If the data in the protected memory space is entered in the cache 103 and the protected data in the cache 103 is accessed, the cache 10
It is possible to stop access to the protected data on the No.3. A method of stopping the memory access is realized by not outputting the address, read, and write control signals from the CPU unit 101.

A second embodiment of the present invention will be described. The configuration is the same as that of the memory protect control device of FIG. The operation will be described with reference to FIGS. 1 and 2. When an illegal memory access occurs, the memory control unit 105 of FIG. 1 outputs a notification signal 107, for example, a non-maskable interrupt (NMI) signal, to notify the illegal memory access to the microcomputer unit at the same time as the above memory access stop. Generate NMI. The memory 106 stores a program that has caused an illegal memory access and a program that terminates the execution of the program, such as an NMI process. In NMI processing,
As shown in the flowchart of FIG. 5, the NMI factor determination (202) is performed, and if it is the NMI generated by the illegal memory access, the execution program that has caused the illegal memory access is ended (203). Other than that, the NMI processing for other factors (204) is executed and the NMI processing is ended (205).

[0012]

As described above, according to the present invention,
In order to prevent system down due to illegal memory access, and to improve the memory access speed by enabling write-back mode in a system that was previously only available in write-through mode, the cache using write-back mode can be used. In the memory protection control, even if the CPU section accesses the entry data of the protected cache, the corresponding entry data is prevented from being accessed and the notification signal of the memory control section notifies the microcomputer section of the illegal memory access. Then, it becomes possible to generate an interrupt and terminate the execution program.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory protect control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the memory protect control device according to the second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional memory protection control device.

[Explanation of symbols]

101 CPU section 102 interrupt control unit 103 cache 104 Microcomputer section 105 memory control unit 106 memory 107 Notification signal 201 NMI processing start 202 Interrupt factor judgment processing 203 Illegal memory access generation program termination processing 204 NMI processing other than illegal memory access 205 NMI processing end 301 CPU section 302 Interrupt control unit 303 cache 304 Microcomputer part 305 Memory controller 306 memory 307 Notification signal

Claims (2)

[Claims] 1. A protect function capable of monitoring and protecting memory access between a CPU section, an interrupt control section, a microcomputer including a cache, a memory, and between the microcomputer section and the memory and between the CPU section and the cache in the microcomputer section. A memory protection control device, comprising: a memory control unit having: 2. The memory control unit has a control signal for notifying an illegal memory access to the microcomputer unit,
2. The memory protection control device according to claim 1, wherein control is performed to terminate an execution program that has caused an illegal memory access.