JP2003167782A - Controller for duplicate controller constituting disk storage system, and disk storage system with the duplicate controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow the acquiring of the right of accessing a disk area concerned simultaneously with the ensuring of a memory area on a disk cache. <P>SOLUTION: A microprocessor 121<SB>-1</SB>in the controller 12<SB>-1</SB>sets the information of the memory area on a cache 124<SB>-1</SB>natural to a designated logic disk area on the receipt of a wright-designated IO request. A control circuit 125<SB>-1</SB>sets this memory area information in a control circuit 125<SB>-2</SB>in a controller 12<SB>-2</SB>through an exclusive bus 13. The control circuit 125<SB>-1</SB>acquires, when the memory area showing the set memory area information can be ensured, the access right to the corresponding disk area by use of exclusively using this memory area, writes designated data in the memory area concerned, and transmits the data concerned to the control circuit 125<SB>-2</SB>through the exclusive bus 13, whereby the data is written in the memory area shown by the memory area information set in the control circuit 125<SB>-2</SB>. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant controller for controlling access to a logical disk, and more particularly, to the same logical disk between the redundant controllers (host computers connected to the same). The present invention relates to a controller for a disk storage system having a redundant controller, which is suitable for exclusive control of access to a disk area and matching control of disk cache data, and a disk storage system having the controller duplicated.

[0002]

2. Description of the Related Art In recent years, a disk storage system has been developed which can handle one or a plurality of disk devices as one logical disk when viewed from a host computer. This system comprises one or more logical disks. As this type of disk storage system, for example, a disk storage system (storage subsystem) in which a controller for controlling access to a logical disk is duplicated, as described in Japanese Patent Laid-Open No. 9-146842, is known. .

In a disk storage system to which a dual controller configuration is applied, different host computers can be connected to each controller, and therefore, IO (input / output) for disk access from a plurality of host computers.
A request (read / write request) can be processed at high speed. In this type of disk storage system, each controller includes a cache memory (hereinafter referred to as a disk cache) for temporarily storing data transferred between a host computer and a logical disk.

Here, it is assumed that the redundant controller in the disk storage system is composed of a first controller and a second controller. Further, it is assumed that the first and second controllers respectively include first and second disk caches and are connected to the first and second host computers, respectively. In such a disk storage system, the first controller, when executing the write request from the first host computer, completes writing the data specified by the write request into the first disk cache and then sends the request source. Of the request execution completion is notified to the first host computer. The data written in the first disk cache is written, that is, written back to the disk area of the logical disk designated by the write request by the first controller at an appropriate timing.

Now, before this write-back is performed,
From the second host computer to the second controller,
It is assumed that the write request from the first host computer is the same as that of the access destination, that is, the write request to the same disk area (same logical disk area) of the same logical disk is given. If the second controller directly executes the write request from the second host computer and writes the data specified by the write request to the second disk cache, the first controller
Also, on the second disk cache, the data corresponding to the same disk area of the same logical disk will be different. Therefore, in this state, when the first host computer issues a read request for instructing the first controller to read data from the disk area, the first controller causes the second host computer to read the data. Data different from the latest data specified by the write request is read from the first disk cache and transferred to the requesting first host computer.

Therefore, in the above disk storage system, in response to a write request from the host computer,
When the corresponding controller writes the data specified in the request to the disk cache, in order to solve the problem that the data does not match between the disk cache and the disk cache of another controller, Matching control (disk cache data matching control) that matches the data between the disk caches, and so-called exclusive control that delays execution of a write request to the same disk area of the same logical disk in another controller during that time (Exclusive control of the logical disk area accessed from the host computer) is required.

The disk cache data matching control and the exclusive control of the logical disk area accessed by the host computer in the conventional disk storage system will be described below.

First, in the conventional disk storage system,
In order to exchange information necessary for the matching control and the exclusive control between the controllers, the first and second controllers are provided with first and second communication control units and first and second disk cache controls, respectively. A circuit is provided, and a first dedicated bus that connects the communication control units and a second dedicated bus that connects the disk cache control circuits are provided.

In such a disk storage system, when an IO request (read / write request) is given from the first host computer to the first controller, for example, the first controller interprets the IO request and (2) The controller performs exclusive control of the disk area (logical disk area) of the logical disk specified by the IO request by communication control via the communication control unit with the controller, and acquires the access right of the disk area. . After this exclusive control, the first controller secures the memory area on the first disk cache necessary for performing the data transfer specified by the IO request. On the other hand, the second controller secures a memory area for storing a copy of the data transferred by the execution of the IO request by the first controller. After that, the first controller
Data is transferred via the first disk cache in accordance with the IO request.

The data stored in the first disk cache is transferred to the second controller via the second dedicated bus by the data transfer function of the first disk cache control circuit, and then transferred to the second disk cache. It is stored in the reserved memory area by the second disk cache control circuit. By the data transfer between the disk caches, the disk cache data is matched between the controllers.

In the conventional disk storage system described above, IO requests for the same disk area (logical disk area) of the same logical disk are given from the first and second host computers to the corresponding first and second controllers. In this case, only one of the controllers acquires the access right to the logical disk area by the communication control by the both controllers and executes the IO request. Here, it is assumed that the first controller acquires the access right and executes the IO request. The second controller must wait for the execution of the IO request from the second host computer until the IO processing of the first controller is completed.

The first controller, which has obtained the access right to the disk area designated by the IO request from the first host computer, executes the IO request to execute the first request.
The data stored in the memory area secured on the disk cache is transferred to the second controller. This data is stored in the memory area secured on the second disk cache by the previous communication between the controllers. As a result, the disk cache data can be matched between the controllers.

The first controller stores all the data designated by the IO request from the first host computer as the first data.
When the storage is completed in the memory area on the disk cache of the first host computer, the first host computer is notified of the completion of the IO request execution, and the first controller is communicated with the second controller via the first dedicated bus. The controller 2 is also notified of the completion of IO request execution. Then, the second controller in the waiting state continues to execute the IO request from the second host computer by using the matched data in the memory area of the second disk cache.

[0014]

As described above, in the conventional disk storage system to which the duplicated controller configuration is applied, when the host computer corresponding to each controller issues an IO request for the same logical disk area, In the controller, the memory area required for data transfer between the corresponding host computer and the logical disk area is secured on the disk cache in the controller itself. This memory area on the disk cache is not only reserved for accessing the same logical disk area from the corresponding host computer, but also as a memory area for matching the disk cache data between the controllers. The synchronization (integrity) of is guaranteed. This is exclusive control for access to the same logical disk area by communication control between each controller (IO exclusive control).
This is because the memory area is secured after the process is performed.

In the conventional disk storage system to which the redundant controller configuration is applied, the exclusive control for the access to the same logical disk area is performed by the communication control between the controllers, and thereafter each controller allocates the memory area on the disk cache. Each controller (corresponding host computer) for making the disk cache data consistent by ensuring
It can be a memory area in which synchronization between them is guaranteed.

However, for that purpose, IO exclusive control by communication control between controllers is required, and there is a problem that the IO request from the host computer cannot be processed at high speed.

Now, after the IO exclusive control by the communication control is performed, the memory area secured on the disk cache of each controller for accessing the same logical disk area (the same disk area of the same logical disk) is simultaneously excluded. It can be said that it is a memory area. On the contrary, if access can be excluded when the memory area is secured in the disk cache, it is considered possible to simultaneously exclude access to the same logical disk area. Therefore, if the memory area on the disk cache of each controller can be secured and exclusive at the same time, it is considered that the IO exclusive control by the communication control can be unnecessary.

Therefore, the present invention has been made in consideration of the above circumstances, and an object thereof is to perform exclusive control for access to the same disk area of the same logical disk and secure memory on the disk cache separately. When a memory area on the disk cache is secured, the right to access the corresponding disk area by using the memory area exclusively at the same time can be obtained, which enables smooth exclusive control and high-speed IO request. The present invention is to provide a controller for a disk storage system that applies a dual controller configuration capable of processing the above, and a disk storage system in which the controller is dual.

[0019]

According to one aspect of the present invention, it is used in a disk storage system to which a dual controller configuration is applied, which comprises at least one logical disk composed of at least one disk device. Provided is a controller for a redundant controller configuration disk storage system that controls data transfer between the host computer and a corresponding logical disk in response to an input / output request from the host computer. This controller receives an input / output request from the host computer and controls the execution of the request, and a microprocessor,
A disk cache memory for temporarily storing data input / output according to an input / output request from a host computer, in which a memory area specific to a logical address area specified by the input / output request is secured, and the disk cache memory A disk cache control circuit for controlling data writing to the memory area secured above and data reading from the memory area is provided. The disk cache control circuit enables the microprocessor to set the memory area information indicating the memory area specific to the logical address area specified by the input / output request from the host computer. According to this setting, the memory area information is set in the disk cache control circuit of another controller in the disk storage system via the dedicated bus. Here, in the disk cache control circuit, the following functions, that is, when the input / output request from the host computer is a write request, the memory area indicated by the memory area information set by the microprocessor is secured, At the same time that the data specified by the input / output request is written in the secured memory area, the data is transferred to the disk cache control circuit of another controller via the dedicated bus to transfer the data to the other It is preferable that the controller has a function of writing to the corresponding memory area secured on the disk cache of the other controller by the disk cache control circuit of the controller.

In the controller having such a configuration, in response to an input / output (IO) request from the host computer, a logical address area (disk area of a logical disk) designated by the input / output request is stored in a disk cache memory unique to the logical address area. Memory area information indicating the memory area of the controller is set in the disk cache control circuit in the controller itself, and at the same time, the memory area information is set in the disk cache control circuit of another controller via the dedicated bus. If the memory area indicated by the above can be secured in the disk cache memory in the own controller, the other controller can simultaneously secure the memory area indicated by the memory area information in the disk cache memory in the other controller. As a result, exclusive control of the logical disk area accessed by the host computer is automatically performed without requiring a special procedure such as communication control. In other words, each controller does not need exclusive control to access the same disk area of the same logical disk by configuring the memory area at the same position on the disk cache memory in the controller at the same time. In addition, high-speed disc cache data matching and input / output request processing can be performed.

Here, the microprocessor has the following functions, that is, a memory set by the disk cache control circuit in the other controller in response to an input / output request from the host computer to the other controller via the dedicated bus. In the state where the memory area indicated by the area information is secured, at least a part of the memory area specific to the logical disk area designated by the received input / output request is accepted. If the input / output request from the host computer to the other controller is a write request in the case where the input / output request is a write request, whether the received input / output request is a write request or a read request. Regardless of the above, until the secured memory area is released, If the function to wait for the memory area specific to the logical disk area specified by the received I / O request (exclusive function) and the I / O request from the host computer to the above other controller is a read request, Only when the received I / O request is a write request, wait until the reserved memory area is released until a memory area specific to the logical disk area designated by the received I / O request is reserved. It is advisable to provide a function (in other words, a shared function) that can secure the memory area only when the received input / output request is a read request.

As described above, the securing of the memory area on the disk cache memory is controlled by the type of input / output request (read / write type) from the host computer so that the area cannot be read / written by others. In addition to the exclusive function, a shared function that allows only reading of the area is provided, that is, a function of classifying and securing the memory area on the disk cache memory as exclusive / shared according to the type of input / output requests from the host computer. By performing exclusive control of the logical disk area accessed by the host computer, the input / output processing required by each controller can be executed at a higher speed.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a computer system including a disk storage system according to an embodiment of the present invention.

In FIG. 1, a disk storage system 10
Is at least 1, for example, n (n is an integer of 2 or more)
11-n of the logical disks 11-1, 11-2, ... 11-n and, for example, two controllers 12-1, 12-2 connected to the respective logical disks 11-1, 11-2 ,. Composed.
The logical disks 11-i (i = 1 to n) appear as a single disk device to the host computers 20-1 and 20-2 described later, and are composed of a plurality of disk devices (for example, hard disk drives). It is an array. The logical disk 11-i may be composed of one disk device.

The controllers 12-1 and 12-2 are connected to host computers 20-1 and 20-2, respectively, which utilize the disk storage system 10. Controller 12
-1, 12-2 responds to IO (input / output) requests (read / write requests) from the host computers 20-1, 20-2 and the host computers 20-1, 20-2 and the logical disks 11-i. Control data transfer to and from. That is, the disk storage system 10 employs a redundant controller configuration including the controllers 12-1 and 12-2. The controllers 12-1 and 12-2 are respectively the microprocessor 1
21-1, 121-2 and host input / output units 122-1, 122
-2, disk input / output units 123-1 and 123-2, disk cache (disk cache memory) 124-1,
124-2 and disk cache control circuits 125-1 and 1
25-2 and PCI bus (Peripheral Component Interco
nnect Bus) represented by internal buses 126-1 and 126-2
It has and. The internal buses 126-1 and 126-2 include microprocessors 121-1 and 121-2, host input / output units 122-1 and 122-2, and disk input / output unit 12 respectively.
3-1 and 123-2 and the disk cache control circuit 125
-1, 125-2 are connected.

Microprocessors 121-1 and 121-2
Is the center of the controllers 12-1 and 12-2,
The execution of IO requests from the host computers 20-1 and 20-2 is controlled according to a control program stored in a non-volatile memory such as a ROM (not shown). In particular, when the microprocessors 121-1 and 121-2 receive an IO request from the host computers 20-1 and 20-2, the I
The disk area of the logical disk 11-i designated by the O request (here, for convenience of description, the host computer 20-
If a memory area corresponding to a logical disk area visible from 1, 20-2, that is, a logical disk area) is not secured in the disk caches 124-1 and 124-2, that memory area Is controlled on the disk caches 124-1 and 124-2 via the disk cache control circuits 125-1 and 125-2, and the access right to the corresponding disk area is acquired when this memory area is secured. To do.

The host input / output units 122-1 and 122-2 form an input / output interface between a host computer using the disk storage system 10 and the controllers 12-1 and 12-2. Here, the host input / output units 122-1 and 1
22-2 are host computers 20-1 and 20-2, respectively.
It is used as an input / output interface with.

The disk input / output units 123-1 and 123-2 are
It forms a connection interface between the logical disks 11-1 to 11-n (each of the disk devices constituting the disk) and the controllers 12-1 and 12-2.

Disk caches 124-1 and 124-2
Is a memory used to temporarily store data transferred between the host computer 20-1 and the logical disk 11-i. In this embodiment, the IO request (input / output request) given from the host computers 20-1, 20-2 to the controllers 12-1, 12-2 includes a logical address (start logical address) and data size information. There is.
The data size is set with the basic block size BS as the minimum unit. That is, the data size is an integral multiple of the block size BS. Now, assuming that the data size is m times the block size BS (m is an integer of 1 or more), logical addresses are consecutive m in the logical address space.
The logical address of the first block of the logical blocks is shown. The areas of the disk caches 124-1 and 124-2 are
As shown in FIG. 2, the block B that matches the block size BS is managed as a unit. Therefore, in the memory area corresponding to the disk area of the logical disk 11-i designated by the IO request, if the size of the disk area is m times the block size BS, the disk caches 124-1 and 124- 2 consecutive m blocks are allocated. Here, the logical block specified by the logical address and the blocks on the disk caches 124-1 and 124-2 correspond in advance.

Disk cache control circuit 125-1, 1
Reference numeral 25-2 denotes disk caches 124-1 and 124-2 set by the microprocessors 121-1 and 121-2.
Controls access to the upper memory area. The disk cache control circuits 125-1 and 125-2 are interconnected by a dedicated bus 13.

Disk cache control circuit 125-1, 1
25-2 is, as shown in FIG. 3, an address register 31, a size register 32 and a status register 3 on the transmission side.
3 and a plurality of receiving side address registers 34, size registers 35, and status registers 36. In the address registers 31 and 34, start addresses (addresses of leading blocks) of memory areas secured on the disk caches 124-1 and 124-2 are set.
In the size registers 32 and 35, the disk cache 1
The size of the memory area secured on 24-1, 124-2,
That is, the number of blocks is set. Status register 3
3 and 36, the disk cache 12 indicated by the address registers 31 and 34 and the size registers 32 and 35.
The statuses of the memory areas on 4-1 and 124-2 are set. This status type includes a write-in-use status indicating that the corresponding memory area is used (exclusive use, secured) by a write request, and a read-in-use status indicating that it is used (secured) by a read request. Status, write use wait status indicating that it is in use wait status for write request, read use wait status that indicates that it is in use wait status for read request, write use completion status that indicates use completion for write request, read Contains the read usage completion status, which indicates the usage is complete for the request. The set of each address register 31, the size register 32, and the status register 33 in the disk cache control circuit 125-1 corresponds to the set of each address register 34, size register 35, and status register 36 in the disk cache control circuit 125-2. It corresponds.

Disk cache control circuit 125-1, 1
In each address register 31 and size register 32 in 25-2, I from the host computer 20-1, 20-2
Addresses and sizes indicating corresponding memory areas (as memory area information) in response to the O request are set by the microprocessors 121-1 and 121-2, respectively. On the other hand, in the address register 34 and the size register 35 in the disk cache control circuits 125-1 and 125-2,
The contents of the corresponding address register 31 and size register 32 in the disk cache control circuits 125-2 and 125-1 are set via the dedicated bus 13 when the contents are set by the microprocessors 121-2 and 121-1. It

Next, the operation of this embodiment will be described with reference to FIGS. Note that FIG. 4 shows the host computer 2.
An IO request (host IO request) 41 for designating a write operation from 0-1, 20-2 to the disk storage system 10-
FIG. 5 is a diagram for explaining the operation when 1, 41-2 are given, and FIG. Bus 13
FIG. 6 is a diagram for explaining how the address register 34 and the size register 35 in the disk cache control circuit 125-2 are set via the memory. FIG. 6 shows the microprocessor 1 when receiving an IO write request designating a write operation.
It is a flow chart for explaining a processing procedure of 21-1 and 121-2.

Now, from the host computers 20-1, 20-2 to the controller 12-1, in the disk storage system 10,
12-2, disk area 4 of logical disk 11-i
Host IO requests 41-1 and 4-4 that specify a write operation to 0
It is assumed that 1-2 is given.

Upon receiving the host IO request 41-1 from the host computer 20-1, the microprocessor 121-1 in the controller 12-1 receives the host IO request 41-1.
Logical disk 11-i to be accessed specified by -1
The address and size designating the memory area on the disk cache 124-1 corresponding to the disk area (access area) 40 of the disk cache 124-1 are indicated by arrows 51 and 52 in FIG. 5 via the internal bus 126-1. The transmission side address register 31 and the size register 32 in the control circuit 125-1 are set (step S1). Here, the address designating the memory area is uniquely determined by calculation from the logical address included in the host IO request.

The disk cache control circuit 125-1 is
When the address and data are set in the transmission side address register 31 and the size register 32 by the microprocessor 121-1, the set address and data are transferred to the dedicated bus 13 as shown by arrows 53 and 54 in FIG. Through the disk cache control circuit 125-2
To the receiving side address register 34 and the size register 35 corresponding to the transmitting side address register 31 and the size register 32 (step S1).
1). That is, when the address and the size are set in the transmitting side address register 31 and the size register 32, the same address and size are set in the corresponding receiving side address register 34 and the size register 35 in synchronization therewith.

The same operation is performed by the controller 12-2. That is, the disk area (logical disk area) 40 of the logical disk 11-i designated by the host IO request 41-2.
The address and size designating the memory area on the disk cache 124-2 corresponding to the above are set in the transmission side address register 31 and the size register 32 in the disk cache control circuit 125-2. At the same time, the address and size set in the transmission side address register 31 and the size register 32 are set in the corresponding reception side address register 34 and size register 35 in the disk cache control circuit 125-1 via the dedicated bus 13. It

Microprocessors 121-1 and 121-2
Is a transmission side address register 31 and a size register 32 in the disk cache control circuits 125-1 and 125-2.
When the address and size are set in
A status indicating "waiting for write use" is set in the status register 33, which is paired with 32 and 32 (step S
2). That is, the microprocessors 121-1 and 121-2
Is the host I from the host computers 20-1 and 20-2.
Regarding the data transfer designated by the O requests 41-1 and 41-2, the transmission side status is set to "wait for write use". Then, the disk cache control circuits 125-1 and 125-2
The status set in the transmission side status register 33 is transferred to the other disk cache control circuits 125-2 and 125-1 via the dedicated bus 13, and the reception side status corresponding to the transmission side status register 33 is transferred. The register 36 is set (step S12).
That is, when the transmission side status is set to "write use wait", the reception side status is automatically set to "write use wait" in synchronization with this.

Microprocessor 121-j (j = 1,
In 2), when the transmission side status is set to "wait for write use", the process proceeds to step S3. Microprocessor 121
In step S3, -j searches for a pair of the receiving side address register 34 and the size register 35 which specify the same memory area as the address and size (memory area information consisting of) set in step S1 (step S3). S3). Here, in order to avoid a complicated expression, it is expressed as "the same memory area as indicated by the address and size set in step S1" for convenience, but this "same memory area" means (Disk cache 1
In addition to the completely same memory area (positions on 24-1 and 124-2), a partial area (partial block area) includes a common memory area.

If the search cannot be performed, the microprocessor 121-j executes the data transfer using the same memory area as the address and size set in step S1 on the other controller side. Judge not to. In other words, the microprocessor 121-j designates the host IO which designates the write to the disk area of the same logical disk 11-i (at least partly) as the disk area of the logical disk 11-i designated by the host IO request 41-j.
Judge that the request is not being executed by another controller. In this case, the microprocessor 121-j activates the disk cache control circuit 125-j to execute the host IO request 41-j and causes the data transfer designated by the host IO request 41-j to be performed (step S5). ). As a result, the disk cache control circuit 125-j changes the status set in the corresponding transmission side status register 33 in the circuit 125-j to "write wait".
To "light in use". This means that the memory area designated by the transmission side address register 31 and the size register 32 forming a pair with the status register 33 switched to the "write in use" status is secured. At the same time, as will be described later in detail, the status set in the reception side status register 36 in the disk cache control circuit of the other controller corresponding to the transmission side status register 33 switched to the "write in use" status is also " It is switched from "write waiting" to "write in use" (step S13). This means that the memory area designated by the receiving side address register 34 and the size register 35, which form a pair with the status register 36 switched to the "write in use" status, is secured.

On the other hand, if the target receiving side address register 34 and size register 35 pair can be retrieved in step S3, the microprocessor 121-j receives the pair of receiving address register 34 and size register 35. It is determined whether or not the "write in use" status is set in the side status register 36 (step S6). If the status of "write in use" is set in the reception side status register 36, that is, if the status of the reception side is "write in use", the microprocessor 121-j determines that the status of the reception side is "write use completed". Execution of the host IO request 41-j is awaited.

On the other hand, when the reception side status is not "write in use", the microprocessor 121-j determines whether or not the reception side status is "write use waiting" (write use completion). (Step S7).
If the reception side status is not "write use wait", that is, "write use completed", the microprocessor 121-j proceeds to step S5 to execute the host IO request 41-j. If the receiving side status is “waiting for write use”, the microprocessor 121-j is
It is determined that the host IO request for writing to the same disk area (at least a part) as the disk area of the logical disk 11-i specified by -j is in the waiting state.
In this case, the microprocessor 121-j determines whether itself is set to a higher priority (step S
8) If the priority is set to high, the process proceeds to step S5 to execute the host IO request 41-j. On the other hand, if its own priority is lower, the microprocessor 121-j waits for execution of the host IO request 41-j until the reception side status becomes "write use completed".

Now, the host computers 20-1, 20-2
To the controller 12-1 of the disk storage system 10,
12-2, disk area 4 of logical disk 11-i
Host IO requests 41-1 and 4-4 that specify a write operation to 0
In the example of FIG. 4 given 1-2, the controller 12-1,
In both of the microprocessors 121-1 and 121-2 of 12-2, the disk cache control circuits 125-1 and 12-1, respectively.
The memory areas 42-1 and 42-2 on the disk caches 124-1 and 124-2 corresponding to the disk area 40 of the logical disk 11-i are designated in the transmission side address register 31 and the size register 32 in 25-2. The same address and size are set (step S1). Naturally, the memory areas 42-1 and 42-2 are the disk caches 124-1 and 1-2.
The positions on 24-2 are the same. In addition, the disk cache 1 is used by both the microprocessors 121-1 and 121-2.
The memory areas 42 having the same positions on 24-1 and 124-2
The pair of the receiving side address register 34 and the size register 35 which specify -1, 42-2 are searched (step S3).
S4). At this time, the receiving side status indicated by the status register 36 corresponding to the pair of the address register 34 and the size register 35 is the disk cache control circuit 1
In both 25-1 and 125-2, "waiting for write use" is shown.

Here, assuming that the controller 12-1 is set to a higher priority than the controller 12-2 in advance, the microprocessor 12 of the controller 12-1.
1-1 proceeds to step S5 first, and the host IO request 41-1
Start executing. At this time, the microprocessor 121
-1 activates the disk cache control circuit 125-1.

Then, in the circuit 125-1 which specifies the memory area 42-1 on the disk cache 124-1 corresponding to the disk area 40 of the logical disk 11-i (specified by the host IO request 41-1). The status indicated by the status register 33, which forms a pair with the transmission side address register 31 and the size register 32, is switched from "write use wait" to "write in use". As a result, the memory area 42-1 is secured on the disk cache 124-1 and the data (write data) specified by the host IO request 41-1 is controlled by the disk cache control circuit 125-1 in the memory area 42-1. It becomes possible to write by.

This is because the disk cache 124-1
Is used as a write-back cache, the memory area 42-1 on the disk cache 124-1
The right to execute the write-back disk IO request 43-1 to write the data written to the disk area 40 on the logical disk 11-i designated by the host IO request 41-1 at an appropriate timing (that is, Logical disk 1
This is equivalent to the controller 12-1 acquiring the access right of the disk area 40 on 1-i). If the disk cache 124-1 is used as a write-through cache, the write data is specified by the host IO request 41-1 when writing the write data to the memory area 42-1 on the disk cache 124-1. The controller 12-1 has the right to execute the disk IO request 43-1 for write-through to write to the disk area 40 on the logical disk 11-i (access right to the disk area 40 on the logical disk 11-i). Has been won.

Now, the disk cache control circuit 125
The status indicated by the status register 33 forming a pair with the transmission side address register 31 and the size register 32 in -1 is switched from "waiting for write use" to "in use for write", and the memory area 42 on the disk cache 124-1. When -1 is secured, the disk cache control circuit 1
The status indicated by the reception side status register 36 in the disk cache control circuit 125-2 corresponding to the transmission side status register 33 in 25-1 is also "wait for write use".
To "in use of light". This allows
The memory area 42-2 is secured on the disk cache 124-2.

On the other hand, the microprocessor 121-2 of the controller 12-2 has the disk cache control circuit 125.
The host side waits for execution of the host IO request 41-2 from the host computer 20-2 until the "write use complete" status is indicated by the receiving side status register 36 in -2.

As described above, in this embodiment, the memory area on the disk cache corresponding to the disk area on the logical disk 11-i designated by the host IO request is secured, and at the same time, it is designated by the host IO request. The exclusive right to access the disk area can be obtained. Therefore, IO exclusive control by communication control or the like can be eliminated, and the speed of IO exclusive control can be increased. By this high-speed IO exclusive control, each host computer 20-
It becomes possible to simultaneously process a plurality of IO requests given to the controllers 12-1 and 12-2 from 1 and 20-2 (if the disk areas to be accessed are different).
This can contribute to improving the performance of the disk storage system 10. Therefore, in this embodiment, the disk cache control circuit 1
Address register 3 on the transmitting side in 25-1 and 125-2
1, a size register 32 and a status register 33, a receiving side address register 34, a size register 35 and a status register 36, respectively.

In the above state, the host computer 20-1
From the host computer 20-1 to the controller 12-1 of the disk storage system 10 is executed in the memory area 42-1 secured on the disk cache 124-1. , Is written under the control of the disk cache control circuit 125-1. In parallel with the data writing to the memory area 42-1, the data written in the memory area 42-1 is controlled by the disk cache control circuit 125-1 via the dedicated bus 13 by the disk cache control of the controller 12-2. Transferred to the circuit 125-2, the disk cache 12
It is written in the memory area 42-2 secured on 4-2.
This enables the disk caches 124-1 and 124-2.
It is possible to make the disk cache data consistent between them.

The data written in the memory area 42-1 on the disk cache 124-1 is transferred to the disk area on the logical disk 11-i designated by the host IO request 41-1 from the host computer 20-1. The disk I / O request 43-1 for writing to 40 is executed. At this time,
On the controller 12-2 side, the memory area 42-2 on the disk cache 124-2 corresponding to the disk area 40 of the logical disk 11-i is synchronized with the securing of the memory area 42-1 on the disk cache 124-1. Has already been secured, the host I that needs the memory area 42-2.
O request 41-2 cannot be executed.

Eventually, when the processing of the host IO request 41-1 on the controller 12-1 side (step S5) is completed,
A transmission side status register 33 paired with a transmission side address register 31 and a size register 32 in the disk cache control circuit 125-1 for designating the memory area 42-1.
The status indicated by is switched to "write use completed". At the same time, the status indicated by the reception side status register 36 in the disk cache control circuit 125-2 corresponding to the transmission side status register 33 in the disk cache control circuit 125-1 is also switched to "write use completed" (step S14). As a result, the disk cache 124-1 for executing the host IO request 41-1,
The memory areas 42-1 and 42-2 secured on 124-2 are released.

When the status indicated by the reception side status register 36 in the disk cache control circuit 125-2 is switched to "write use completed", that is the controller 1 waiting for the execution of the host IO request 41-2.
It is detected by the microprocessor 121-2 of 2-2 (steps S6 and S7). Then microprocessor 1
21-2 controls the disk cache control circuit 125-2 to reserve the memory area 42-2 on the disk cache 124-1 for executing the host IO request 41-2. This is paired with the transmission side address register 31 and the size register 32 in the disk cache control circuit 125-2 that specifies the memory area 42-2, as is apparent from the execution of the host IO request 41-1. This is realized by switching the status set in the transmission side status register 33 from "waiting for write use" to "in use for write". By this switching, the transmission side status register 3
The status set in the reception side status register 36 in the disk cache control circuit 125-1 corresponding to No. 3 is also switched from "waiting for write use" to "in use for write". As a result, the disk cache 124
The memory area 42-1 is newly secured on -1.

In this state, the host IO request 41-2 from the host computer 20-2 is executed, and the data transferred from the host computer 20-2 to the controller 12-2 of the disk storage system 10 becomes the disk cache 1
It is written in the memory area 42-2 secured on 24-2 under the control of the disk cache control circuit 125-2. Further, in parallel with the data writing to the memory area 42-2, the data written to the memory area 42-2 is transferred to the dedicated bus 13 by the disk cache control circuit 125-2.
Is transferred to the disk cache control circuit 125-1 of the controller 12-1 through the disk cache 124-1.
It is written in the memory area 42-1 secured above. As a result, the disk cache data between the disk caches 124-2 and 124-1 can be matched.

The data written in the memory area 42-2 on the disk cache 124-2 is transferred to the disk area on the logical disk 11-i designated by the host IO request 41-2 from the host computer 20-2. The disk I / O request 43-2 for writing to the 40 is executed.

As described above, the host computers 20-1, 20-2
The description has centered on securing the memory area on the disk caches 124-1 and 124 when the host IO requests 41-1 and 41-2 from the same to the same disk area 40 are both write requests. However, a memory area different from that described above can be secured depending on the combination of the types of IO requests.

That is, in this embodiment, the memory area reservation on the disk caches 124-1 and 124 is controlled by the following two types according to the types of IO requests from the host computers 20-1 and 20-2. There is. These two types of control functions are called (i) exclusive function and (ii) shared function. Regarding the exclusive function and the shared function, the host computer 2
Disk cache 124 according to the IO request from 0-1
-1, While the memory area is secured on 124-2,
An example in which an IO request that specifies access to the same disk area as the IO request is given from the host computer 20-2 to the controller 12-2 of the disk storage system 10 will be sequentially described with reference to the flowchart of FIG. To do.

(I) Exclusive Function Now, memory areas are secured in the disk caches 124-1 and 124-2 in response to a write request from the host computer 20-1 to the controller 12-1 of the disk storage system 10. I shall. Here, the address and size for designating the memory area are set in the address registers 31 and 34 and the size registers 32 and 35 in the disk cache control circuits 125-1 and 125-2, and the status registers 33 and 36 are set to ""Burnlight" status is set.

In this state, a read or write request designating access to the same disk area (at least in part) as the above write request is issued from the host computer 20-2 to the controller 12-2 of the disk storage system 10. Given. In this case (step S21
~ S23), the exclusive function works in the controller 12-2,
Regardless of any read / write request from the host computer 20-2 to the controller 12-2, a memory area secured by the write request from the host computer 20-1 to the controller 12-1 (at least a part of ) Use the same memory area as the disk cache 124-2
(And 124-1) cannot be secured (step S24). In other words, execution of a read or write request from the host computer 20-2 to the controller 12-2 is performed by the host computer 20-1 to the controller 12-1.
It is kept waiting until the memory area secured by the write request is released, that is, the status of the area is switched from "write in use" to "write use complete".

(Ii) Sharing Function Now, memory areas are secured in the disk caches 124-1 and 124-2 in response to a read request from the host computer 20-1 to the controller 12-1 of the disk storage system 10. I shall. Here, the address and size for designating the memory area are set in the address registers 31 and 34 and the size registers 32 and 35 in the disk cache control circuits 125-1 and 125-2, and the status registers 33 and 36 are set to " Read in use status is set. However, in response to a read request to the controller 12-1, the disk caches 124-1 and 12-2
When the memory area is secured on 4-2, the memory area on the disk cache 124-2 is not actually used (for reading data from the area).

In this state, the host computer 20-2 gives the controller 12-2 of the disk storage system 10 an IO request designating access to the same disk area (at least in part) as the above read request. It is assumed that In this case (steps S21 to S23), if the sharing function works in the controller 12-2 and the IO request from the host computer 20-2 to the controller 12-2 is a read request (step S25), the host computer 20- The disk cache 124-2 (and 124-1) has the same memory area (at least partly) as the memory area (status is "read in use") secured by the read request from 1 to the controller 12-1.
It can be secured immediately above (step S26).
On the other hand, if the IO request from the host computer 20-2 to the controller 12-2 is a write request (step S25), it is secured by the read request from the host computer 20-1 to the controller 12-1. It is not possible to secure the same memory area (at least partly) as the memory area (whose status is "read in use") on the disk cache 124-2 (and 124-1) (step S24). That is, the host computer 2
The write request from 0-2 to the controller 12-2 is executed by the host computer 20-1 to the controller 12-1.
It is kept waiting until the memory area secured by the read request to the memory is released, that is, the status of the area is switched from "read in use" to "read use completed".

In the above-described embodiment, each of the controllers 12-1 and 12-2 of the disk storage system 10 is connected to one host computer 20-1 and 20-2, respectively. However, the present invention can be similarly applied even if a plurality of host computers are connected to each of the controllers 12-1 and 12-2.
However, there is a possibility that multiple host computers connected to the same controller will (at least in part) issue IO requests that specify access to the same disk area. It is necessary to control access exclusion even between host computers. For that purpose, the address register 31 and the size register 32 on the transmitting side may also be searched in step S3. It is also possible to apply a connection configuration in which each host computer gives an IO request to both the controllers 12-1 and 12-2. Such a connection configuration is realized, for example, by connecting the controllers 12-1 and 12-2 of the disk storage system 10 and each host computer via a network such as a LAN. Further, the controller may be multiplexed.

The present invention is not limited to the above-mentioned embodiment, and can be variously modified in an implementation stage without departing from the scope of the invention. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problem described in the section of the problem to be solved by the invention can be solved, and the effect described in the section of the effect of the invention can be solved. If you get
A configuration in which this component is deleted can be extracted as an invention.

[0064]

As described above in detail, according to the present invention, since the access area of the logical disk can be excluded at the same time by securing the memory area on the disk cache, IO exclusion control such as communication control is unnecessary. Can be Therefore, the exclusive control can be smoothly performed and the IO request can be processed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system including a disk storage system according to an embodiment of the present invention.

FIG. 2 is a diagram showing disk caches 124-1 and 124 in FIG.
The figure for demonstrating that the area of -2 is managed in the unit of block B of fixed size.

FIG. 3 shows a disk cache control circuit 125- in FIG.
The figure which shows the register group provided in 1, 125-2.

FIG. 4 shows a host computer 20 in the same embodiment.
-1, 2 is an operation explanatory diagram when IO requests 41-1 and 41-2 for designating a write operation are given to the disk storage system 10.

FIG. 5 is a block diagram showing an embodiment of the disk cache control circuit 125-1 according to the present embodiment, in which the address and size are set in an address register 31 and a size register 32 in the disk cache control circuit 125-1. 12 is a diagram for explaining how the address register 34 and size register 35 in 125-2 are set.

FIG. 6 is a diagram showing an I for designating a write operation in the embodiment.
Microprocessor 12 when O write request is received
The flowchart for demonstrating the processing procedure of 1-1 and 121-2.

FIG. 7 is a flowchart for explaining a procedure for controlling the memory area reservation on the disk caches 124-1 and 124 according to the type of IO request from the host computers 20-1 and 20-2.

[Explanation of symbols]

10 ... Disk storage system 11-1 to 11-n, 11-i ... Logical disk 12-1, 12-2 ... Controller 13 ... Private bus 20-1, 20-2 ... Host computer 31 ... Sending side address register 32 ... Sending side size register 33 ... Transmitter status register 34 ... Receiving side address register 35 ... Receiving side size register 36 ... Receiving side status register 42-1, 42-2 ... Memory area 121-1 and 121-2 ... Microprocessor 124-1, 124-2 ... Disk cache 125-1 and 125-2 ... Disk cache control circuit

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G06F 12/08 541 G06F 12/08 541Z 3/06 302 3/06 302A

Claims (10)

[Claims] 1. A host computer used in a disk storage system to which a dual controller configuration is applied, comprising at least one logical disk comprising at least one disk device, and the host computer according to an input / output request from the host computer. In a controller for a duplexed controller configuration disk storage system that controls data transfer between a logical disk and a corresponding logical disk, a microprocessor that receives an input / output request from the host computer and controls execution of the request, and the host A disk cache memory in which a memory area specific to a logical address area designated by the input / output request is reserved for temporarily storing data input / output according to an input / output request from a computer; Secured in A disk cache control circuit for controlling writing of data to a memory area and reading of data from the memory area, which is for ensuring a memory area specific to a logical address area designated by an input / output request from the host computer. The memory area information indicating the memory area can be set from the microprocessor, and according to this setting, the memory area information is sent to a disk cache control circuit of another controller in the disk storage system via a dedicated bus. A controller for a disk storage system having a redundant controller configuration, which comprises a disk cache control circuit for setting. 2. When the input / output request from the host computer is a write request, the disk cache control circuit determines that the memory area indicated by the memory area information set by the microprocessor is secured. At the same time that the data specified by the I / O request is written in the secured memory area, the data is transferred to the disk cache control circuit of the other controller via the dedicated bus, so that the data is 2. The controller for a dual controller configuration disk storage system according to claim 1, wherein the controller writes the data in a corresponding memory area secured on the disk cache of the other controller by a disk cache control circuit of the controller. 3. The disk cache control circuit includes at least one transmission side memory area information holding unit used for setting memory area information for securing a memory area by the microprocessor, and a disk of the other controller. 2. The duplex controller configuration disk storage according to claim 1, further comprising at least one receiving side memory area information holding means used for setting memory area information for securing a memory area by the cache control circuit. System controller. 4. The transmission side status holding means for holding the status of the memory area designated by the transmission side memory area information holding means, the disk cache control circuit forming a pair with the transmission side memory area information holding means, The disk control circuit further includes a reception side status holding means for forming a pair with the reception side memory area information holding means and holding the status of the memory area designated by the reception side memory area information holding means. When the status indicated by the transmission side status holding means is updated, the updated status is transferred to the disk control circuit of the other controller by the dedicated bus, so that the reception side included in the disk control circuit of the other controller. It is characterized in that the status indicated by the status holding means is updated to the updated status. The controller for a dual controller configuration disk storage system according to claim 3. 5. The status of the memory area designated by the sending side memory area information holding means forming a pair with the sending side status holding means, and the memory area is secured in the sending side status holding means. 5. The duplexing system according to claim 4, wherein one of a status including a busy status indicating that the memory area is exclusively used and a usage completion status indicating that the exclusive use of the memory area is completed is held. Controller configuration Controller for disk storage system. 6. The disk cache control circuit, wherein the microprocessor, in response to a write-specified input / output request from the host computer, stores memory area information indicating a memory area specific to a logical disk area specified by the input / output request. If the receiving side memory area information holding means indicating at least a part of the memory area common to the memory area is not present in the disk cache control circuit, it is immediately set. , If it exists, refer to the status indicated by the reception side status holding means forming a pair with the reception side memory area information holding means, and immediately if the status indicates that the use is completed, otherwise Wait for the status to switch to the usage complete status, then set the sender memory area information. 6. The controller for a dual controller configuration disk storage system according to claim 5, wherein the status indicated by said transmitting side status holding means forming a pair with the information holding means is updated to indicate that it is in use. 7. The microprocessor indicates memory area information set via the dedicated bus by a disk cache control circuit in the other controller in response to an input / output request from the host computer to the other controller. A memory area in which at least a part of the memory area unique to the logical disk area designated by the received input / output request is received while the input / output request is received from the host computer in the state where the memory area is secured. If the input / output request from the host computer to the other controller is a write request, regardless of whether the received input / output request is a write request or a read request, I / O requests from the host computer to the controller If it is a read request, only when the received I / O request is a write request, a memory unique to the logical disk area designated by the received I / O request until the reserved memory area is released. The controller for a dual controller-configured disk storage system according to claim 1, wherein the controller waits until an area is secured. 8. The first and second controllers according to claim 1, wherein at least one logical disk including at least one disk device and a redundant controller are included. First and second controllers that control data transfer between the host computer and the corresponding logical disk in response to an input / output request from a host computer connected to the controller; and the first and second controllers. And a dedicated bus for connecting the disk cache control circuits in the controller to the disk storage system. 9. An input / output from a host computer connected to the controller, comprising at least one logical disk comprising at least one disk device, and first and second controllers constituting a redundant controller. An I / O request exclusive control method in a disk storage system in which data transfer between a host computer and a corresponding logical disk is controlled by the controller in response to a request, the method comprising: When an input / output request is given from the host computer to one of the controllers, a first memory area for ensuring the memory area specific to the logical address area specified by the input / output request in the disk cache memory of the one controller. Setting the first setting, and the first setting To secure a memory area at the same position as the memory area set in the first setting step in the disk cache memory of the other controller of the first and second controllers according to the setting in step According to the setting in the second setting step and the setting in the first setting step, if the corresponding memory area can be secured on the disk cache memory of the one controller, that effect is set for the one of the one controller. In the step of notifying from the controller to the other controller via the dedicated bus, and in the other controller that has received the notification of the memory area reservation in the notifying step, depending on the setting in the second setting step. Securing the corresponding memory area on the disk cache memory of the other controller An input / output request exclusive control method in a disk storage system, comprising: 10. When the input / output request is a write request,
Upon receiving the input / output request, the one controller writes the data specified by the input / output request in the memory area secured on the disk cache memory after the notification step, and at the same time, writes the data in the other side. 10. The method according to claim 9, further comprising the step of writing the data in a corresponding memory area secured on the disk cache memory of the other controller by transferring the data to another controller via the dedicated bus.
I / O request exclusive control method in the described disk storage system.