JP2003163840A - Flicker correction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flicker correction circuit that can adjust a slice level depending on a flicker correction coefficient so as to effectively reduce noise even when a noise level is partially increased. <P>SOLUTION: A flicker coefficient extraction circuit 2 obtains the flicker correction coefficient 22 from a video signal S21 including flicker, a multiplier circuit 3 multiplies the flicker correction coefficient 22 with the video signal S21 to uniformize levels of frames thereby preventing the flicker from appearing in the video signal. Further, a multiplier circuit 5 multiples a flicker correction coefficient 22b with a level slice coefficient 25 to produce a new level slice coefficient and applies the new level slice coefficient to a level slice circuit 7 so as to make the level slice coefficient correspondent to fluctuations in a noise component by a noise extracting high pass filter circuit 4 thereby obtaining a noise signal S27 from which edge components are eliminated, and a multiplier circuit 9 and a subtractor circuit 10 reduces the noise by using the noise signal S27. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a flicker (flick).
er) correction circuit, and more particularly, to a flicker correction circuit that allows level slices to be adjusted according to a flicker correction coefficient so that noise reduction can be effectively performed even when a noise level is high.

[0002]

2. Description of the Related Art When an image is recorded by a camera function of a digital video camera or a mobile phone, the illumination may be outdoor natural light or indoor fluorescent light. When the illumination is artificial light, the illumination light flickers depending on the frequency of the power supply. Therefore, flicker occurs due to the interference between the illumination cycle and the video frame cycle. With respect to this flicker, conventionally, flicker correction is performed by detecting the periodic level fluctuation of the image signal due to the flicker and applying the coefficient of the inverse characteristic to the video signal to cancel the periodic level fluctuation. There is. At the same time as flicker correction, noise reduction is also performed to detect the noise level and eliminate the influence of noise on the video signal.

FIG. 6 shows a conventional flicker correction circuit.
The flicker correction circuit 200 is connected to the flicker correction coefficient extraction circuit 102 connected to the input terminal 101, the input terminal 101 and the multiplication circuit 103 connected to the output terminals of the flicker correction coefficient extraction circuit 102, and the output terminal of the multiplication circuit 103. The high-pass filter circuit 104 for extracting the noise component,
Level slice circuit 1 connected to the input terminal 105 and the output terminal of the noise component extracting high-pass filter circuit 104
06, the input terminal 107 and the multiplication circuit 108 connected to the output terminal of the level slice circuit 106, and the multiplication circuit 10
8 and the output terminal of the multiplication circuit 103 are connected to the subtraction circuit 109. This subtraction circuit 1
An output terminal 118 is connected to 09.

FIG. 7 shows the operation of the flicker correction circuit having the configuration shown in FIG. The video signal S111 is input to the input terminal 101. This video signal S111 has a noise component 1 in each frame (or scanning line), as shown in FIG.
25, and periodical level fluctuations occur for each frame due to flicker. Video signal S111
Is a flicker correction coefficient extraction circuit 102 and a multiplication circuit 10.
Input to 3. The flicker correction coefficient extraction circuit 102
A flicker correction coefficient 112 for correcting the video signal S111 whose level has changed due to flicker is generated.
The flicker correction coefficient 112 is 100/12 depending on the level fluctuation of the video signal S111, as shown in FIG.
Coefficient values such as 0 and 100/80 are set. The flicker correction coefficient 112 and the video signal S111 including the flicker are
Both are applied to the multiplication circuit 103. The multiplication circuit 103 multiplies the flicker correction coefficient 112 and the video signal S111, and outputs a flicker-free video signal S113. Since the video signal S111 is multiplied by the flicker correction coefficient 112, the level fluctuation that has occurred in the video signal S111 is corrected, and the video signal S113 has a uniform level in each frame as shown in FIG. 7C. Has become.

Video signal S output from multiplication circuit 103
Reference numeral 113 is a high-pass filter circuit 10 for noise component extraction.
4 and the high-pass filter circuit 104 for noise component extraction outputs a high-frequency component signal S1 including a noise component 125 and an edge component 121, as shown in FIG.
14 is generated. The high frequency component signal S114 is input to the level slice circuit 106. Level slice circuit 1
06 is level sliced by the level slice coefficient 115 input from the input terminal 105 as shown in FIG. 7E, and the noise component 12 from which the edge component 121 has been removed.
5 is generated. A coefficient 116 that determines the strength of noise reduction is input from the input terminal 107.
16 is multiplied by the output signal S117 of the level slice circuit 106 by the multiplication circuit 108 to generate the noise signal S117 as shown in FIG. The noise signal S117 and the video signal S1 output from the multiplication circuit 103
13 is a subtraction process [(video signal S
113)-(noise signal S117)] is calculated, and the signal obtained by this calculation is the output signal (video signal) S11.
8 is output from the output terminal 110.

[0006]

However, according to the conventional flicker correction circuit, the noise signal S117 is amplified by the flicker correction coefficient, which results in the noise signal S11.
7, the level slice coefficient 115 is a constant value regardless of the size of the flicker correction coefficient. Therefore, the noise components 122a and 122b that exceed the slice level 130 are regarded as the edge component 121 and are removed from the noise component 125. Actually, only the edge component 121 component is removed from the signal waveform of FIG. 7D, and the noise signal S1 is generated as shown in FIG.
Although it is desirable that a difference be generated in 17, the noise signal S having the same level at any signal timing
, 117a, 117b, ..., and the noise signal S117b becomes the video signal S1 as shown in FIG.
The video signal S118 left in 13 is output.

As described above, the conventional flicker correction circuit is
In some cases, noise reduction does not work because it is not possible to deal with noise that has become large due to flicker correction.
Further, if the slice level is increased on the assumption that the noise level increases, the edge component 121 is regarded as the noise component 125, and the edge component 121 is subtracted by the subtraction circuit 109. Therefore, the video signal S11
There is a new problem that the edge of 8 becomes dull (the rising end and falling start of the waveform are curved).

It is an object of the present invention to provide a flicker correction circuit that enables the slice level to be adjusted according to the flicker correction coefficient, so that noise reduction can be effectively performed even when the noise level partially increases. To do.

[0009]

In order to achieve the above-mentioned object, the present invention multiplies a flicker-caused video signal by a flicker correction coefficient to make the level uniform, and a periodic fluctuation appears in the video signal. And a flicker correction unit for eliminating the flicker correction unit, and a noise component is extracted from the video signal subjected to the flicker correction by the flicker correction unit, and a slice level corresponding to the level of the noise component is used as the flicker correction coefficient by the flicker correction unit. There is provided a flicker correction circuit including a noise reduction unit that removes the noise component by setting based on the setting.

According to this structure, with respect to the portion where the noise component increases due to the flicker correction, the slice level for removing the noise component is changed by using the flicker correction coefficient, and the edge component is changed. Only the noise component is removed so that the noise component has a level according to the flicker correction, and noise reduction is performed based on the noise signal thus obtained. As a result, it is possible to obtain a flicker correction circuit in which the edges of the image signal are not blunted and much noise is not left.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the flicker correction circuit of the present invention. The flicker correction circuit 100 of the present invention is
The flicker correction coefficients 22a, 22 are connected to the input terminal 1.
flicker correction coefficient extraction circuit 2 for generating b, input terminal 1
And a multiplication circuit 3 connected to the output terminal of the flicker correction coefficient extraction circuit 2, a noise component extracting high-pass filter circuit 4 connected to the output terminal of the multiplication circuit 3, an output terminal and an input terminal of the flicker correction coefficient extraction circuit 2. 6 connected to the multiplier circuit 5, the output terminal of the multiplier circuit 5 and the level slice circuit 7 connected to the output terminal of the noise component extracting high-pass filter circuit 4, the input terminal 8 and the output terminal of the level slice circuit 7. In addition to being connected to the output terminal of the multiplication circuit 9 and the output terminal of the multiplication circuit 3, the output terminal of itself is connected to the output terminal 11, and the subtraction circuit 10 is configured. The subtraction circuit 10 has its (+) input terminal connected to the output terminal of the multiplication circuit 9 and its (−) input terminal connected to the output terminal of the multiplication circuit 3.

FIG. 2 shows a flicker correction circuit 1 shown in FIG.
00 operation is shown. The video signal S21 shown in FIG. 2A is input to the input terminal 1. This video signal S21
Has a waveform with a noise component 31 on each frame and a periodic level fluctuation due to flicker, and the first input of the flicker correction coefficient extraction circuit 2 and the multiplication circuit 3 through the input terminal 1. Input to the terminal. The flicker correction coefficient extraction circuit 3 has a flicker correction coefficient 22a (for example, 100/120, 100/8) for keeping the video signal whose level is periodically changed by flicker constant.
0) is extracted as shown in FIG. 2B and output to the multiplication circuits 3 and 5. The multiplication circuit 3 multiplies the flicker-containing video signal S21 by the flicker correction coefficient 22a to generate a video signal S23 shown in FIG. 2C in which the flicker is eliminated and the levels of the respective frames are equal. .

At this point, the periodic level fluctuation occurring in each frame of the video signal S21 is corrected and the video signal S23 having the same level in each frame is obtained, but the gain different depending on the frame causes a noise component. Therefore, the fluctuation of the flicker correction coefficient 22a is also added to the noise component. Therefore, in the present invention, noise having the periodicity is effectively reduced by performing the following noise reduction.

Video signal S23 output from the multiplication circuit 3
Is applied to the noise component extracting high-pass filter circuit 4. In the noise component extraction high-pass filter circuit 4,
A high frequency signal S24 including an edge component and a noise component is shown in FIG.
(D) of the level slice circuit 7
Output to. On the other hand, the level slice coefficient 25 that determines the slice level is input to the input terminal 6 from a circuit (not shown), and the multiplication circuit 5 multiplies the level slice coefficient 25 and the flicker correction coefficient 22b. The signal 26 is output. The level slice circuit 7 generates the noise signal S27 from which the edge component 32 has been removed, with the signal S26 set to the slice level. At this time, the level is increased by the flicker correction as shown in (f) of FIG. 2 as compared with the state of (e) of FIG. 2 (state of the conventional level slice signal S105) in which the signal S22 and the multiplication circuit 5 are not provided. A slice level 36 that is larger than the slice level 33 is obtained corresponding to the noise level 35.

The high-frequency signal S24 which is the output signal of the noise component extracting high-pass filter circuit 4 is input to the level slice circuit 7. The level slice circuit 7 receives the signal S
26 as a level slice coefficient, noise signals S27a, 27b, 27c, ... With different noise component levels for each frame are obtained as shown in FIG. The noise signals S27a, 27b, 27c, ... Are multiplied by the coefficient 28 that determines the strength of the noise reduction input from the input terminal 8 in the multiplication circuit 9, and the edge component 3
2 removed noise signal S29 is obtained. The noise signals S27a, 27b, 27c, ...
2 and is subtracted from the video signal S23 having the waveform of FIG. 2C, the subtraction circuit 10 outputs the noise component 31 from each frame of the video signal S21 as shown in FIG. The video signal S34 having a waveform that has been removed and flicker-corrected is output.

As described above, according to the flicker correction circuit 100 of the present invention, the flicker correction coefficient 22b controls the slice level of the level slicing circuit 7 for removing the edge component from the high frequency component of the noise reduction. It is possible to make the noise of the video signal S23 whose noise level periodically fluctuates due to the correction inconspicuous.

FIG. 3 shows a detailed configuration of the flicker correction coefficient extraction circuit 2. The flicker correction coefficient extraction circuit 2 includes a frame average value calculation circuit 202 connected to an input terminal 201,
An average value calculation circuit 203 connected to the frame average value calculation circuit 202, an output terminal of the frame average value calculation circuit 202 and a divider 204 connected to the output terminal of the average value calculation circuit 203, and an output terminal of the divider 204. Delay circuits 205, 206, 207, 208 connected in series to the subtraction circuits 209, 2 connected in parallel to the output terminals of the delay circuit 205.
10, 211, an absolute value conversion circuit (ABS) 212 connected to the output end of the subtraction circuit 209, an absolute value conversion circuit (ABS) 213 connected to the output end of the subtraction circuit 210, and an output end of the subtraction circuit 211 Absolute value conversion circuit (ABS) 2
14. A 3-input minimum value extraction circuit (MIN) 215 which receives the output signals of the absolute value conversion circuits 212 to 214 as input signals, and outputs the output signal of the 3-input minimum value extraction circuit 215 and the output signal of the absolute value conversion circuit 212. Equivalent comparison circuits 216 and 3 for comparison
The output signal of the input minimum value extraction circuit 215 and the absolute value conversion circuit 2
Equivalent comparison circuit 217 for comparing output signals of 13 and output signal of 3-input minimum value extraction circuit 215 and absolute value conversion circuit 214
Comparison circuit 218 and delay circuit 2 for comparing the output signals of
06-208 output terminals and equivalent comparison circuits 216-21
1 to 3 control signal terminals 219d to 2
19f is connected and signals S305 to S307 from the delay circuits 206 to 208 are input terminals 219a to 219.
The switch circuit 219 is input to c, and the delay circuit 220 is connected between the output terminal of the switch circuit 219 and the output terminal 221.

The first input terminal 21 of the switch circuit 219
The output signal of the delay circuit 206 is input to 9a
The output signal of the delay circuit 207 is input to the input terminal 219b of the input terminal 219, and the output signal of the delay circuit 208 is input to the third input terminal 219c. The switch circuit 219 includes switches 219g, 219h, and 219i, each of which has first to third control signal input terminals 219d and 219.
e, control signals S312 to S313 input to 219f
ON / OFF control is performed by (output from the equivalent comparison circuits 216 to 218). The output signal of the switch circuit 219 is output to the multiplication circuit 3 as a flicker correction coefficient 22a, and the signal (flicker correction coefficient 22b) obtained by delaying the flicker correction coefficient 22a by the delay circuit 220 is output to the multiplication circuit 5. The number of the delay circuits 205 to 208, the subtraction circuits 209 to 211, the absolute value conversion circuits 212 to 214, and the equivalent comparison circuits 216 to 218 are set according to the set number of the flicker correction coefficient, and thus the set number is large. In that case, the number will increase from the configuration of FIG.

FIG. 4 shows the operation of the flicker correction coefficient extraction circuit of FIG. The video signal S21 shown in FIG. 4A, which fluctuates due to flicker, is input to the frame average value calculation circuit 202 via the input terminals 1 and 201. The frame average value calculation circuit 202 calculates a frame average value 301 for each frame of the video signal S21 as shown in FIG. This indicates whether the level of each frame is higher or lower than the reference value “100”. Here, the frame average value 301 is “80” to “12”.
A value of "0" is shown. Based on the frame average value 301, the average value calculation circuit 203 calculates the average value 302 of the entire video signal S21 as shown in FIG. 4C, and applies it to one input terminal of the divider 204. The average value 302 is
The average values of the frame average values 301 in FIG. 4B are shown, and here, {(80 + 120 + 8)
0 + 120 + 80 + 120 + 80 + 120) / 8} = 1
A value of 00 has been obtained. Since the average value 301 is input to the other input terminal of the divider 204, the divider 2
04 is [(frame average value 301) / (average value 30
2)] is calculated as shown in FIG. 4D, and the calculation result is input to the delay circuit 205 as a signal S303. The delay circuit 205 delays the input signal S303 by one frame to generate a signal S304, which is delayed by the delay circuit 20.
6 is applied. The delay circuits 206 to 208 use the signal S30.
4 is sequentially delayed by one frame, and (e) to FIG.
The signals S305 to 307 shown in (h) are generated.

The subtraction circuit 209 has a signal S304 and a signal S
Subtraction of 305 (= signal S305-signal S304) is performed, and the absolute value (| 100 / 80-100 / 120 | etc.) is taken by the absolute value conversion circuit 212 with respect to this subtraction result. The signal S308 shown in is obtained. Similarly, in the subtraction circuit 210, the signals S304 and S
The subtraction of 306 (= signal S306−signal S304) is performed, and the absolute value is obtained by the absolute value conversion circuit 213 with respect to the subtraction result, so that the signal S30 shown in (j) of FIG. 4 is obtained.
9 is obtained. In this case, in the subtraction circuit 210, (100/120) − (100 /
120) = 0, in the next frame (100/80)-(1
00/80) = 0. In the subtraction circuit 211, the signal S304 and the signal S307 are subtracted (the signal S30
7-signal S304) is performed, and the absolute value is obtained by the absolute value conversion circuit 214 with respect to this subtraction result.
The signal S310 shown in (k) is obtained.

The signals S308, S309 and S310 are input to the first to third input terminals 215a to 215c of the 3-input minimum value extraction circuit 215, respectively. The 3-input minimum value extraction circuit 215 extracts the signal having the smallest value among the input S308 to S310, and sets this as the signal S311. Here, comparing (i) to (k) of FIG. 4, it can be seen that the signal S309 is “0” and the average value is the smallest among the three signals, as shown in (j) of FIG. Signal S311 output from the 3-input minimum value extraction circuit 215
Is input to one input terminal of each of the equivalent comparison circuits 216 to 218. The signal S308 is input to the other input terminal of the equivalent comparison circuit 216, and the equivalent comparison circuit 217 is input.
The signal S309 is input to the other input terminal of the
The signal S310 is applied to the other input terminal of the equivalent comparison circuit 218.
Is entered.

The equivalent comparison circuit 216 compares the signal S311 with the signal S308. The signal S308 has a certain value as shown in (i) of FIG. 4, while the signal S311 is "0". Therefore, the equivalent comparison circuit 216 outputs the signal S312 of "0" as shown in (m) of FIG. Further, the equivalent comparison circuit 217 compares the signal S311 and the signal S309, but since both signals have the same content, the equivalent comparison circuit 217 outputs the signal S313 of "1" as shown in (n) of FIG. . Further, the equivalence comparison circuit 216 compares the signal S311 with the signal S308. The signal S308 has a certain value as shown in (i) of FIG.
Since 11 is "0", the equivalent comparison circuit 216 outputs the signal S314 of "0" as shown in (o) of FIG.

The switch circuit 219 receives the signal S3 input to the first to third control signal input terminals 219d to 219f.
One of the signals S308, S309, S310 input to the corresponding input terminals 219a, 219b, 219c is selected depending on whether 12 to S314 are "0" or "1". Here, since the signal S313 is "1", the switch 2
Only 19h is turned on, and the signal S306 in FIG. 4G input to the input terminal 219b is selected. This signal S306 is delayed by one frame by the delay circuit 220 and then output from the output terminal 221 as the flicker correction coefficient S22 as shown in (p) of FIG.
Is applied to the multiplication circuit 3 and the multiplication circuit 5.

Flicker correction coefficient 22b of FIG. 4 (p)
As can be seen by comparing the flicker correction coefficient 22a of FIG. 2B, the flicker correction coefficient 22a has a small value (100/12 when the level of the video signal S21 is high.
0) and the level of the video signal S21 is small, the flicker correction coefficient 22a is a large value (100/8).
0), while the flicker correction coefficient 22b is reversed. As a result, noise reduction can be performed with the noise component as it is, and the noise signal as shown in FIG. 7G is not left on the video signal.

FIG. 5 shows another example of the configuration of the flicker correction coefficient extraction circuit 2. The overall configuration of the flicker correction coefficient extraction circuit 2 is as shown in FIG. 3 and the overall operation is as shown in FIG. 4, but instead of the frame average value calculation circuit 202 of FIG. Value calculation circuit 501
It is characterized by using. Line average value calculation circuit 5
The line average value 502 is output from 01, and is input to the average value calculation circuit 203 and the divider 204.

1 to 4, the output of the flicker correction coefficient extraction circuit 2 is updated on a frame-by-frame basis, whereas according to the configuration of FIG. 5, it is changed on a scanning line (line) basis. As a result, CMOS (Complementary Metal)
Oxide Semiconductor image sensor camera (image
It is also possible to deal with flicker that appears as a step in the scanning line such as sensor camera).

[0027]

As is apparent from the above, according to the flicker correction circuit of the present invention, the flicker correction coefficient is obtained by the flicker correction means, the flicker correction coefficient is used to perform the flicker correction, and the image after the flicker correction is performed. Since the noise reduction means for removing the noise by changing the slice level according to the level of the noise component included in the signal based on the flicker correction coefficient is provided, the edge of the image signal is blunted or the noise is increased. A flicker correction circuit that does not remain can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a flicker correction circuit of the present invention.

FIG. 2 is a timing chart showing the operation of the flicker correction circuit shown in FIG.

FIG. 3 is a block diagram showing a detailed configuration of a flicker correction coefficient extraction circuit 2.

FIG. 4 is a timing chart showing the operation of the flicker correction coefficient extraction circuit of FIG.

FIG. 5 is a block diagram showing another configuration example of the flicker correction coefficient extraction circuit according to the present invention.

FIG. 6 is a block diagram showing a conventional flicker correction circuit.

7 is a timing chart showing an operation of the flicker correction circuit having the configuration of FIG.

[Explanation of symbols]

1,6,8,201 Input terminal 2 Flicker correction coefficient extraction circuit 3 Multiplier circuit 4 High-pass filter circuit for noise component extraction 5,9 Multiplier circuit 7 level slice circuit 10,209,210,211 Subtraction circuit 11,221 output terminals 100 Flicker correction circuit 202 Frame average value calculation circuit 203 Average value calculation circuit 204 divider 205, 206, 207, 208, 220 Delay circuit 212, 213, 214 Absolute value conversion circuit (ABS) 215 3-input minimum value extraction circuit 216, 217, 218 Equivalent comparison circuit 219 switch circuit 219a to 219c Input end 219d to 219f control signal terminals 501 line average value calculation circuit

Claims (4)

[Claims] 1. A flicker correction unit that multiplies a flicker-occurring video signal by a flicker correction coefficient to make the level uniform and prevents periodic fluctuations from appearing in the video signal; and flicker correction by the flicker correction unit. Noise reduction means for removing the noise component by extracting a noise component from the image signal subjected to the above step and setting a slice level corresponding to the level of the noise component based on the flicker correction coefficient by the flicker correction means. A flicker correction circuit comprising. 2. A noise component extracting high-pass filter circuit for extracting a noise component from the video signal subjected to flicker correction by the flicker correction unit, the noise reduction unit, and the flicker correction coefficient by the flicker correction unit. A first multiplication circuit that multiplies with a level slice signal that determines the slice level; and a slice level is set by the output signal of the first multiplication circuit with respect to the output signal of the noise component extraction high-pass filter circuit. A level slice circuit for removing edge components from the flicker-corrected video signal; a second multiplication circuit for multiplying an output signal of the level slice circuit by a coefficient for determining noise reduction; Subtracting the output signal of the second multiplication circuit from the video signal Flicker correction circuit according to claim 1, characterized in that it comprises the that subtraction circuit. 3. The flicker correction coefficient extraction circuit obtains an average value of the level of the video signal in which the flicker has occurred and calculates an average value of flicker correction coefficients, and an output signal of the average value calculation means. A plurality of delay circuits that perform delay in stages, a subtraction unit that obtains a difference value of the flicker correction coefficient between the input and the output of each of the plurality of delay circuits, and the most of the difference values obtained by the subtraction unit. The flicker correction circuit according to claim 1, further comprising a selection unit that determines whether or not to output each output signal of the plurality of delay circuits with a small value as a comparison reference. 4. The average value calculating means obtains an average value of a frame or a scanning line of the video signal as an average value of the video signal in which the flicker has occurred. Flicker correction circuit.