JP2003163328A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a electrode structure under a conductive plug, which does not generate increase in contact resistance due to oxidation of a conductive plug and contact failure even under an oxide dielectric film formation process, and does not deteriorate the ferroelectric properties of the oxide dielectric. <P>SOLUTION: A Pd layer 12 is formed on the exposed surface of a W plug 11. Further, a Ti layer 13 that becomes a diffusion inhibition layer of Pd is formed on the upper surface of the Pd layer 12, and a Pt layer 14 that becomes the diffusion inhibition layer of Ti is formed on the upper surface of the Ti layer 13. Then, a lower electrode 15 is formed on the upper surface of the Ti layer 14, and a ferroelectric film 16 and an upper electrode 17 are formed on the upper surface of the lower electrode 15. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device having a capacitor having a lower electrode, a ferroelectric film and an upper electrode, and a conductive plug connecting the capacitor and an active element. .

[0002]

2. Description of the Related Art Conventionally, as a ferroelectric material used for a ferroelectric capacitor for a ferroelectric memory (FeRAM), PZT (Pb (Zr _1-x Ti _x ) O which is an oxide is used.
₃ ), SBT (SrBiTa ₂ O ₉ ), BTO (Bi
₄ Ti ₃ O ₁₂ ) etc. have been studied.

In general, a heat treatment in an oxygen atmosphere at 600 ° C. or higher is required as a film forming process of a ferroelectric material, particularly as a ferroelectric crystallization process. Further, in the process of manufacturing the conductive plug of the dielectric capacitor, particularly in the case of the stack type structure, the lower electrode (Pt, for example) is directly formed on the polysilicon which is the conductive plug. Therefore, due to the heat treatment in the ferroelectric capacitor process, a silicidation reaction may occur between Pt and polysilicon, which deteriorates the ferroelectric characteristics. In order to prevent this silicidation, a diffusion barrier layer of TiN or the like has conventionally been provided between the lower electrode and polysilicon which is a conductive plug (Japanese Patent Laid-Open No. 4-181766).

However, Ti in the Pt / TiN structure
It has been reported that N is oxidized by oxygen gas that permeates the Pt film grain boundaries during the crystallization process of the ferroelectric film. This oxidation causes a contact failure between the lower electrode and the polysilicon that is the conductive plug.

On the other hand, regarding the material for forming the lower electrode, P
In addition to t, Ir, PtRh, Ru, or oxides thereof (IrO ₂ , PtRhO _x and RuO ₂ ) and the like have characteristics such as their excellent barrier properties and controllability with respect to the oxide dielectric formed above. Has been attracting attention for. However, for example, when forming an IrO ₂ film, IrO ₂ film is formed.
_In the process of forming the _two films and the ferroelectric film, I
At the interface between rO ₂ and polysilicon, contact failure occurs due to the oxidation of polysilicon.

Despite these problems, IrO
The lower electrode of the ₂ / Ir / TiN / Ti structure is SrTiO.
Applicable to high dielectric materials such as ₃ , 200 ℃ ~
When the high dielectric film is formed by a relatively low temperature process of 450 ° C., it has preferable characteristics such as no deterioration of electrical characteristics of the capacitor due to hillock generation and deterioration of flatness. Therefore, it can be said that the lower electrode of the IrO ₂ / Ir / TiN / Ti structure is promising as a stack type structure using a high dielectric capacitor.

When a ferroelectric such as PZT is used, the ferroelectric crystallization process requires an oxygen atmosphere at 600 ° C. or higher. At such high temperatures,
For example, when using a lower electrode structure of Pt / TiN,
Pt hillocks are generated due to the change in film stress due to the oxidation of Ti, resulting in poor contact between the lower electrode and the conductive plug.

To solve the above problems, Japanese Patent Laid-Open No. 2000-408
The "ferroelectric memory element and method for manufacturing the same" described in Japanese Patent Laid-Open No. 00-00100 has a stack type ferroelectric memory element having a lower electrode structure having good contact characteristics with a conductive plug, and the same. A manufacturing method is provided.

According to the present invention, Pt, I which is a noble metal or a base metal is provided in the contact hole where the silicide plug is formed.
r, Ru, Pd, Au, Cu, Ni, Co, Re, P
A metal layer made of b, Al, Si, Cr, Ti, and Be is formed between the lower electrode and the conductive plug to suppress the oxidation of the conductive plug.

However, the above method requires an extra step of forming a thin film of a noble metal or a base metal in the contact hole where the conductive plug is formed, and the noble metal or the base metal on the conductive plug is on top (strong). It is unavoidable to prevent diffusion to the dielectric layer side. For this reason, the noble metal or base metal diffuses upward toward the ferroelectric during the manufacturing process, causing deterioration in the characteristics of the ferroelectric capacitor.

[0011]

Therefore, according to the present invention,
A semiconductor having a conductive plug-lower electrode structure that does not cause increase in contact resistance and contact failure due to oxidation of the conductive plug even after the oxide dielectric film formation process and does not deteriorate the ferroelectricity of the oxide dielectric. Provide a device.

[0012]

In order to achieve the above-mentioned object, a semiconductor device of the present invention has a substrate, an active element formed on the substrate, and an active element formed on the substrate. An insulating film formed on the insulating film, a conductive plug formed by exposing the upper surface to a contact hole of the insulating film and connected to the active element, and a metal formed on the upper surface of the conductive plug and containing palladium. Layer, a conductive layer formed on the upper surface of the metal layer containing palladium, containing titanium, a metal layer containing platinum formed on the upper surface of the conductive layer containing titanium, containing platinum. It is characterized by comprising a lower electrode formed on the upper surface of the metal layer and electrically conducting to the conductive plug, and an upper electrode formed on the upper surface of the ferroelectric film.

In order to achieve the above object, the semiconductor device of the present invention comprises a substrate and a substrate as described in claim 2.
An active element formed on the substrate, an insulating film formed on the substrate, a conductive plug formed by exposing an upper surface to a contact hole of the insulating film and connected to the active element; Formed on the upper surface of the conductive plug, formed on the upper surface of the metal layer containing palladium and the metal layer containing palladium, and formed on the upper surface of the metal layer containing platinum and the metal layer containing platinum. A conductive layer containing titanium, a lower electrode formed on the upper surface of the conductive layer containing titanium and electrically connected to the conductive plug, and a ferroelectric film formed on the upper surface of the lower electrode. And an upper electrode formed on the upper surface of the ferroelectric film.

According to a third aspect of the present invention, there is provided a semiconductor device including a metal film which covers the conductive plug and contains palladium.

According to a fourth aspect of the semiconductor device of the present invention, the conductive plug is made of tungsten.
It is characterized by containing either polycrystalline silicon or palladium.

According to a fifth aspect of the semiconductor device of the present invention, the lower electrode has an iridium layer, and an iridium oxide layer formed on the upper surface of the iridium layer.
And a platinum layer formed on the upper surface of the iridium oxide layer.

Palladium (Pd) has a very strong hydrogen (H ₂ ) storage effect among the platinum group. Due to this property, the reducing property is extremely strong, and it has an action of easily reducing the oxide and the oxide film. The present invention takes advantage of this effect and has a structure in which palladium (Pd), which is a strongly reducing metal, is sandwiched between the conductive plug and the lower electrode. As a result, even in the process step in which the conductive plug and the surroundings of the lower electrode are exposed to oxygen, it is possible to suppress the oxidation of the conductive plug, and it is possible to suppress the increase in contact resistance and the contact failure due to the oxidation of the conductive plug. In addition, a diffusion suppressing layer (Ti as a lower layer, which suppresses diffusion of palladium (Pd), which is a strongly reducing metal, toward the oxide dielectric film side.
By providing Pt as an upper layer or Pt as a lower layer and Pt as an upper layer), it is possible to suppress the deterioration of the ferroelectric characteristics of the oxide dielectric film.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view of a first embodiment of the present invention. In the figure, the semiconductor device 1 includes a tungsten (W) plug 11 which is a conductive plug, a palladium (Pd) layer 12, a titanium (Ti) layer 13, a platinum (Pt) layer 14, a lower electrode 15, a ferroelectric film. Lead zirconate titanate (Pb (Zr, Ti) O ₃ : PZT)
16, the upper electrode 17, the Si substrate 20, the MOS transistor 30, and the interlayer insulating film 40. Of these, the lower electrode 15, the PZT 16 and the upper electrode 17 constitute the ferroelectric capacitor 10.

A MOS transistor 30 for driving the ferroelectric capacitor 10 is formed on the Si substrate 20. Further, an interlayer insulating film 40 made of SiO ₂ or SiN is formed on the Si substrate 20 by the CVD method. The interlayer insulating film 40 has the ferroelectric capacitor 1
A contact hole for forming the W plug 11 forming 0 is formed by etching after patterning.

This contact hole is filled with tungsten by sputtering or CVD, and then CMP is performed.
Is flattened by. With such a method, the W plug 1
1 is formed. The W plug 11 is connected to the source / drain region 31 of the MOS transistor 30.

A Pd layer 12 having a thickness of about 5 nm is formed on the exposed surface of the W plug 11. Further, on the upper surface of the Pd layer 12, a Ti layer 13 having a thickness of about 10 nm serving as a Pd diffusion suppressing layer is formed, and on the upper surface of the Ti layer 13, a Pt layer having a thickness of about 10 nm serving as a Ti diffusion suppressing layer. 14 is deposited.

On the upper surface of the Pt layer 14, an Ir film having a thickness of about 10 nm is formed.
A lower electrode 15 is formed by laminating a layer, an IrO ₂ layer having a thickness of about 5 nm, and a Pt layer having a thickness of about 5 nm in this order. Then, as a ferroelectric film 16, a lead zirconate titanate (Pb (Zr, Ti) O ₃ : P) film having a thickness of about 30 nm is formed on the upper surface of the lower electrode 15.
ZT) is deposited. The ferroelectric film 16 may be formed by a sol-gel method or a sputtering method. Further, on the upper surface of the ferroelectric film 16, an I film having a thickness of about 10 nm is formed.
rO ₂ is deposited as the upper electrode 17. With such a procedure, the semiconductor device 1 is completed.

By adopting the above laminated structure, the oxidation of the W plug 11 during the process step is suppressed and the lower electrode 15 is prevented.
It is possible to prevent contact failure between the W plug 11 and the W plug 11. In addition, the diffusion prevention layer composed of the Ti layer 13 and the Pt layer 14 on the Pd layer 12 allows Pd to be applied to the ferroelectric film 16.
Since the diffusion of Al is suppressed, it is possible to prevent the ferroelectric substance that is an oxide from being reduced and the ferroelectric characteristics from being deteriorated.
Therefore, it is possible to stably manufacture the FeRAM,
It is possible to significantly improve the yield.

FIG. 2 is a sectional view of a modification of the first embodiment. In FIG. 1, a Pd diffusion suppressing layer is formed on the upper surface of the Pd layer 12 in the order of the Ti layer 13 and the Pt layer 14, but as shown in FIG. 2, the Pt layer 14 and the Ti layer 13 are formed in this order. It may be done.

(Second Embodiment) FIG. 2 is a sectional view of a second embodiment of the present invention. In the figure, a semiconductor device 101
Is a tungsten (W) plug 11 which is a conductive plug
1, palladium (Pd) layer 112, titanium (Ti) layer 1
13, platinum (Pt) layer 114, lower electrode 115, lead zirconate titanate (Pb (Zr, Ti), which is a ferroelectric film)
O ₃ : PZT) 116, upper electrode 117, Si substrate 12
0, MOS type transistor 130 and interlayer insulating film 140
It is composed of Of these, the lower electrode 115, P
The ZT 116 and the upper electrode 117 form a capacitor 110.
Is configured.

Similar to FIG. 1, a MOS transistor 130 for driving the ferroelectric capacitor 110 is formed on the Si substrate 120. Further, on the Si substrate 120, the interlayer insulating film 140 made of SiO ₂ or SiN is formed.
Are formed by the CVD method. On the interlayer insulating film 140, the W plug 11 that constitutes the ferroelectric capacitor 110 is formed.
A contact hole for forming 1 is formed by etching after patterning.

The circumference of this contact hole is 5 to 10
It is covered with a Pd film 118 having a thickness of nm. The Pd film 118 is formed by sputtering or CVD. Then, the contact hole covered with the Pd film 118 is filled with tungsten by sputtering or CVD,
It is flattened by CMP. The W plug 111 is formed by such a method. The W plug 111 is connected to the source / drain region 131 of the MOS transistor 130.

Others have the same structure as the semiconductor device 1 of FIG. That is, on the exposed surface of the W plug 111,
A Pd layer 112 having a thickness of about 5 nm is formed. Furthermore, the Pd layer 1
A Ti layer 113 having a thickness of about 10 nm, which serves as a Pd diffusion suppressing layer, is formed on the upper surface of 12, and T is formed on the upper surface of the Ti layer 113.
A Pt layer 114 having a thickness of about 10 nm, which serves as a diffusion suppressing layer for i, is formed.

On the upper surface of the Pt layer 114, an I film having a thickness of about 10 nm is formed.
A lower electrode 115 is formed by laminating an r layer, an IrO ₂ layer having a thickness of about 5 nm, and a Pt layer having a thickness of about 5 nm in this order. Then, as a ferroelectric film 116, lead zirconate titanate (Pb (Zr, Ti)) having a thickness of about 30 nm is formed on the upper surface of the lower electrode 115.
O ₃ : PZT) is deposited. The ferroelectric film 116 may be formed by a sol-gel method or a sputtering method. Further, on the upper surface of the ferroelectric film 116, IrO ₂ having a thickness of about 10 nm is formed as an upper electrode 117. With such a procedure, the semiconductor device 101 is completed.

By adopting the above structure, the W plug 1
Since the periphery of 11 is covered with the Pd film 118, the oxidation of the W plug 111 during the process step is further suppressed and the contact resistance between the lower electrode 115 and the W plug 111 is increased as compared with the first embodiment. Contact failure can be suppressed. Further, as in the first embodiment, the diffusion prevention layer composed of the Ti layer 113 and the Pt layer 114 on the Pd layer 112 suppresses the diffusion of Pd into the ferroelectric film 116, so that an oxide is used. It is possible to prevent deterioration of ferroelectric characteristics due to reduction of a certain ferroelectric substance. Therefore, it is possible to significantly improve the yield in the manufacturing process of the FeRAM.

By the way, in FIG. 3, the Pd diffusion suppressing layer is formed on the upper surface of the Pd layer 112 in the order of the Ti layer 113 and the Pt layer 114, but the Pt layer 114 and the Ti layer 113 are formed in this order. You can

The ferroelectric films 16 and 116 are made of PZT.
Other BST (Barium Strontium Titanate ((B
a / Sr) TiO ₃ )) may be used, and the film forming method may be MOCVD in addition to the method described above. The material of the conductive plugs may be polycrystalline silicon other than W, and Pd plugs can be used instead of W plugs 11 and 111.

[0034]

As described above, according to the present invention, contact failure between the lower electrode and the conductive plug can be suppressed. Further, since the diffusion prevention layer composed of Ti and Pt on Pd suppresses the diffusion of Pd into the ferroelectric film, the ferroelectric substance which is an oxide is reduced and the ferroelectric characteristic is deteriorated. Can be suppressed. Therefore, the FeRAM can be stably manufactured, and the yield can be remarkably improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment.

FIG. 2 is a sectional view of a modification of the first embodiment.

FIG. 3 is a sectional view of a second embodiment.

[Explanation of symbols]

1, 101 Semiconductor device 10,110 Ferroelectric capacitor 11,111 Tungsten (W) plug 12,112 Palladium (Pd) layer 13,113 Titanium (Ti) layer 14,114 Platinum (Pt) layer 15, 115 Lower electrode 16,116 Ferroelectric film 17, 117 Upper electrode 20, 120 Si substrate 30, 130 MOS type transistor 31, 131 source / drain regions 40,140 Interlayer insulation film 118 Palladium (Pd) film

Claims (5)

[Claims] 1. A substrate, an active element formed on the substrate, an insulating film formed on the substrate, and a contact hole of the insulating film, the upper surface of which is exposed and connected to the active element. And a conductive layer formed on the upper surface of the conductive plug and containing palladium, a conductive layer formed on the upper surface of the metal layer containing palladium and containing titanium, and containing titanium. A metal layer containing platinum, which is formed on the upper surface of the conductive layer, and a lower electrode which is formed on the upper surface of the metal layer containing platinum and electrically connected to the conductive plug; A semiconductor device comprising: an upper electrode formed on an upper surface of the semiconductor device. 2. A substrate, an active element formed on the substrate, an insulating film formed on the substrate, and a contact hole of the insulating film, the upper surface of which is exposed and connected to the active element. A conductive plug, a metal layer containing palladium, which is formed on an upper surface of the conductive plug, a metal layer containing platinum, which is formed on an upper surface of the metal layer containing palladium, and which contains platinum. A conductive layer containing titanium that is formed on the upper surface of the metal layer, a lower electrode that is formed on the upper surface of the conductive layer that contains titanium, and is electrically conductive with the conductive plug, and an upper surface of the lower electrode. A semiconductor device comprising: a ferroelectric film formed; and an upper electrode formed on an upper surface of the ferroelectric film. 3. The semiconductor device according to claim 1, further comprising a metal film that covers the conductive plug and contains palladium. 4. The semiconductor device according to claim 1, wherein the conductive plug contains any one of tungsten, polycrystalline silicon and palladium. 5. The semiconductor device according to claim 1, wherein the lower electrode has an iridium layer, an iridium oxide layer formed on an upper surface of the iridium layer, and an upper surface of the iridium oxide layer. A semiconductor device comprising a formed platinum layer.