JP2003158196A5 - - Google Patents

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Publication number
JP2003158196A5
JP2003158196A5 JP2001356354A JP2001356354A JP2003158196A5 JP 2003158196 A5 JP2003158196 A5 JP 2003158196A5 JP 2001356354 A JP2001356354 A JP 2001356354A JP 2001356354 A JP2001356354 A JP 2001356354A JP 2003158196 A5 JP2003158196 A5 JP 2003158196A5
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Japan
Prior art keywords
semiconductor device
resistance element
oxide film
forming
direct
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Pending
Application number
JP2001356354A
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Japanese (ja)
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JP2003158196A (en
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Priority to JP2001356354A priority Critical patent/JP2003158196A/en
Priority claimed from JP2001356354A external-priority patent/JP2003158196A/en
Publication of JP2003158196A publication Critical patent/JP2003158196A/en
Publication of JP2003158196A5 publication Critical patent/JP2003158196A5/ja
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Claims (10)

半導体基板上に形成された素子分離酸化膜と、該素子分離酸化膜上に形成された抵抗素子と、該抵抗素子上に形成された層間膜と、該層間膜を開口して上記抵抗素子上の少なくとも複数箇所に形成されたコンタクト領域と、該コンタクト領域の上面に形成された金属配線層とを備えた半導体装置において、
上記抵抗素子の直表面および直側面の一部を覆うように形成された第1の酸化膜を備えたことを特徴とする半導体装置。
An element isolation oxide film formed on a semiconductor substrate, a resistance element formed on the element isolation oxide film , an interlayer film formed on the resistance element, and opening the interlayer film on the resistance element In a semiconductor device comprising a contact region formed in at least a plurality of locations, and a metal wiring layer formed on the upper surface of the contact region,
A semiconductor device comprising a first oxide film formed so as to cover a part of a direct surface and a direct side surface of the resistance element.
上記第1の酸化膜の直表面および直側面を覆うように形成された窒化膜を備えたことを特徴とする請求項1記載の半導体装置。  2. The semiconductor device according to claim 1, further comprising a nitride film formed so as to cover a direct surface and a direct side surface of the first oxide film. 上記窒化膜の直表面および直側面を覆うように形成された第2の酸化膜を有することを特徴とする請求項2記載の半導体装置。  3. The semiconductor device according to claim 2, further comprising a second oxide film formed so as to cover a direct surface and a direct side surface of the nitride film. 上記抵抗素子の上面および側面の一部を覆うように形成された導電性膜を有することを特徴とする請求項1〜3のいずれかに記載の半導体装置。  The semiconductor device according to claim 1, further comprising a conductive film formed so as to cover a part of the upper surface and side surface of the resistance element. 上記導電性膜を上部電極、上記抵抗素子を下部電極として用い、該上部電極と下部電極の間に上記第1の酸化膜、上記窒化膜および上記第2の酸化膜を層間誘電体膜として設けたことを特徴とする請求項4記載の半導体装置。  The conductive film is used as an upper electrode, the resistive element is used as a lower electrode, and the first oxide film, the nitride film, and the second oxide film are provided as an interlayer dielectric film between the upper electrode and the lower electrode. The semiconductor device according to claim 4, wherein: 上記抵抗素子と上記コンタクト領域との接触部分に形成されたシリサイド層を有することを特徴とする請求項1〜5のいずれかに記載の半導体装置。  6. The semiconductor device according to claim 1, further comprising a silicide layer formed at a contact portion between the resistance element and the contact region. 半導体基板上に素子分離酸化膜を形成する工程と、上記素子分離酸化膜上に半導体材料を形成する工程と、上記半導体材料にイオン注入することで抵抗素子を形成する工程と、上記抵抗素子上に層間膜を形成する工程と、上記層間膜を開口して上記抵抗素子上の少なくとも複数箇所にコンタクト領域を形成する工程と、上記コンタクト領域の上面に金属配線層を形成する工程とを備えた半導体装置の製造方法において、
上記抵抗素子の直表面および直側面の一部を覆うように第1の酸化膜を形成する工程と、
上記第1の酸化膜の直表面および直側面を更に覆うように窒化膜を形成する工程と
を備えたことを特徴とする半導体装置の製造方法。
Forming an element isolation oxide film on a semiconductor substrate; forming a semiconductor material on the element isolation oxide film; forming a resistance element by ion implantation into the semiconductor material; and on the resistance element Forming an interlayer film, forming a contact region in at least a plurality of locations on the resistive element by opening the interlayer film, and forming a metal wiring layer on the upper surface of the contact region In a method for manufacturing a semiconductor device,
Forming a first oxide film so as to cover a part of the direct surface and the direct side surface of the resistance element;
And a step of forming a nitride film so as to further cover the direct surface and the direct side surface of the first oxide film.
上記窒化膜の直表面および直側面を覆うように第2の酸化膜を形成する工程を備えたことを特徴とする請求項7記載の半導体装置の製造方法。  8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a second oxide film so as to cover a direct surface and a direct side surface of the nitride film. 上記抵抗素子の上面および側面の一部を覆うように導電性膜を形成する工程を備えたことを特徴とする請求項7または8記載の半導体装置の製造方法。  9. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a conductive film so as to cover part of the upper surface and side surfaces of the resistance element. 上記抵抗素子と上記コンタクト領域の接触部分において、上記抵抗素子の表面を選択的に高融点金属とシリサイド反応をさせる工程を備えたことを特徴とする7〜9のいずれかに記載の半導体装置の製造方法。  The semiconductor device according to any one of 7 to 9, further comprising a step of selectively performing a silicide reaction with a refractory metal on a surface of the resistance element at a contact portion between the resistance element and the contact region. Production method.
JP2001356354A 2001-11-21 2001-11-21 Semiconductor device and its manufacturing method Pending JP2003158196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001356354A JP2003158196A (en) 2001-11-21 2001-11-21 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001356354A JP2003158196A (en) 2001-11-21 2001-11-21 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JP2003158196A JP2003158196A (en) 2003-05-30
JP2003158196A5 true JP2003158196A5 (en) 2005-07-14

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JP2001356354A Pending JP2003158196A (en) 2001-11-21 2001-11-21 Semiconductor device and its manufacturing method

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004363234A (en) * 2003-06-03 2004-12-24 Renesas Technology Corp Method for manufacturing semiconductor device
JP4786126B2 (en) * 2003-06-04 2011-10-05 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP4546054B2 (en) * 2003-08-29 2010-09-15 パナソニック株式会社 Manufacturing method of semiconductor device
JP5354160B2 (en) * 2008-10-16 2013-11-27 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP5850671B2 (en) * 2011-08-15 2016-02-03 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP2019021659A (en) * 2017-07-11 2019-02-07 キヤノン株式会社 Semiconductor device and equipment

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