JP2003152467A - Power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a radiation which occurs due to the edge of an output voltage in a D class power amplifier. SOLUTION: The power amplifier comprises a pair of pulse modulators 11L, 11R converting an input signal into pulse modulation signal and outputting the signals to a pair of power amplifiers 10L, 10R; a pair of push-pull circuits (15L, 16L), (15R, 16R); and a pair of drive circuits (13L, 14L), (13R, 14R). The power amplifier further comprises loads 19L, 19R connected between the output ends of he push-pull circuit (15L, 15R) and the output ends of the push-pull circuits (15R, 16R). The pulse modulation signal of the power amplifier 10L is the signal rising at the time of starting the one cycle period. The pulse modulation signal of the power amplifier 10R is the signal falling at the time of ending the one cycle period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier device.

[0002]

2. Description of the Related Art As a power amplifier for audio, there is a so-called class D amplifier. This class D amplifier, which performs power amplification by switching, is configured as shown in FIG. 8, for example.

That is, the digital audio signal Pin
Is supplied to the PWM modulation circuit 11 through the input terminal Tin and a clock having a predetermined frequency is supplied from the clock forming circuit 12 to the PWM modulation circuit 11, and the audio signal Pin is converted into a pair of PWM signals PA and PB. To be done.

In this case, as shown in FIG. 10, the pulse widths of the PWM signals PA and PB are determined by the digital audio signal Pin.
Changes according to the level (instantaneous level when the signal Pin is D / A converted; the same applies below). However, the pulse width of one PWM signal PA is larger than the level indicated by the digital audio signal Pin. The pulse width of the other PWM signal PB is the magnitude of the two's complement of the level indicated by the digital audio signal Pin. Further, the PWM signals PA and PB have a rising time at the PWM signal P
The one-cycle period Tc of A and PB is fixed at the start time point, and the trailing time point changes corresponding to the level indicated by the audio signal Pin.

Further, the carrier frequency fc (= 1 / Tc) of the PWM signals PA and PB is the digital audio signal Pin.
For example, 16 times the sampling frequency fs of fs = 48
If it is set to kHz, then fc = 16fs = 16 × 48 kHz = 768 kHz.

Then, one PWM signal PA from the PWM modulation circuit 11 is supplied to the drive circuit 13 and, as shown in FIG. 9A, a pair of drive pulse voltage + PA which is at the same level as the signal PA and whose level is inverted. , -PA are formed, and these pulse voltages + PA, -PA are used as a pair of switching elements, for example, n-channel MOS-FETs.
It is supplied to the gates of (Q11, Q12).

In this case, the FETs (Q11, Q12) form the push-pull circuit 15, and the FETs (Q11)
The drain of is connected to the power supply terminal TPWR, and the source is connected to the drain of FET (Q12).
12) Source is connected to ground. Also, the power supply terminal TPW
A stable DC voltage + VDD is supplied to R as a power supply voltage. The voltage + VDD is, for example, 20V to 50V.

The source of the FET (Q11) and F
The drain of ET (Q12) is connected to one end of the speaker 19 through the low pass filter 17 having a coil and a capacitor.

The other P from the PWM modulation circuit 11
The WM signal PB has the same configuration as the PWM signal PA. That is, the PWM signal PB is supplied to the drive circuit 14, and as shown in FIG. 9B, a pair of drive pulse voltages + PB and -PB, which have the same level as the signal PB and are level-inverted, are formed.
B and -PB are a pair of n that constitutes the push-pull circuit 16.
It is supplied to the gates of the channel MOS-FETs (Q13, Q14).

The source of the FET (Q13) and F
The drain of ET (Q14) is connected to the other end of the speaker 19 through the low pass filter 18 having a coil and a capacitor.

Therefore, when + PA = “H”,
-PA = "L", the FET (Q11) is turned on and the FET (Q12) is turned off.
The voltage VA at the connection point of (11, Q12) becomes the voltage + VDD as shown in FIG. 9C. On the contrary, when + PA = “L”, −PA = “H”, the FET (Q11) is turned off and the FET (Q12) is turned on.
VA = 0.

Similarly, when + PB = "H", -PB
= “L”, the FET (Q13) is turned on and the FET (Q14) is turned off. Therefore, the FET (Q13,
The voltage VB at the connection point of Q14) becomes the voltage + VDD, as shown in FIG. 9D. On the contrary, when + PB = "L", -PB = "H", the FET (Q13) is turned off and the FET (Q14) is turned on, so VB =
It becomes 0.

Then, during the period of VA = + VDD and VB = 0, as shown in FIGS. 8 and 9E, the FET (Q1
From the connection point of 1, Q12), through the line of low pass filter 17 → speaker 19 → low pass filter 18,
A current i flows to the connection point of ET (Q13, Q14).

During the period of VA = 0 and VB = + VDD, the FETs (Q11, Q12) are connected from the connection point of the FETs (Q13, Q14) through the line of the low pass filter 18 → the speaker 19 → the low pass filter 17. A current i flows in the opposite direction to the connection point of. Further, the current i does not flow during the period of VA = VB = + VDD and the period of VA = VB = 0. That is, the push-pull circuits 15 and 16 form a BTL circuit.

The period during which the current i flows is the original P
When the WM signals PA and PB change corresponding to the rising period and the current i flows through the speaker 19,
Since the current i is integrated by the low-pass filters 17 and 18, as a result, the current i flowing through the speaker 19 is an analog current corresponding to the level indicated by the digital audio signal Pin and is a power-amplified current. That is,
The power-amplified output is supplied to the speaker 19.

Thus, the circuit of FIG. 8 operates as a power amplifier. At this time, the FETs (Q11 to Q14) switch the power supply voltage + VDD corresponding to the inputted digital audio signal Pin to amplify the power. Therefore, the efficiency is high and a large output can be obtained.

[0017]

By the way, FIG. 9C, D
As also shown in the figure, since the power supply voltage + VDD is switched at high speed to form the output voltages VA and VB, the output voltage V
Radiation is generated by the rising edges of A and VB (marked by ↑ in FIGS. 9C and 9D). Moreover, at the time of switching, the power supply voltage + VDD is as high as 20V to 50V, so
The radiation will also be quite large. And P
The carrier frequency fc of the WM signals PA and PB is, for example, 768 kHz as described above, and this is included in the broadcasting band of medium-wave broadcasting.

For this reason, when the class D power amplifier as described above is integrated with the receiver or arranged in the vicinity of the receiver as in a car audio system, the output voltage V
Radiation due to the rising edges of A and VB interferes with the reception of broadcasting. Further, the rising edges of the output voltages VA and VB are steep and include many harmonic components, and the harmonic components are also radiated, so that they may interfere with the reception of the FM receiver or the television receiver.

The present invention is intended to provide a power amplifier device in which such radiation is reduced.

[0020]

SUMMARY OF THE INVENTION In the present invention, for example, there are first and second power amplifiers, and each of the first and second power amplifiers outputs an input signal with its quantization level. A first pulse modulation circuit for converting and outputting the first pulse modulated signal shown in the above, and a second pulse modulating circuit for converting the input signal into a second pulse modulated signal indicating the two's complement of the quantization level and outputting the second pulse modulated signal. Pulse modulation circuit and 1
A pair of first and second push-pull circuits configured by push-pull connection of a pair of switching elements and a pair of first and second pulse-modulated signals output from the first pulse-modulation circuit having opposite levels. The drive pulse which is converted into a drive pulse and is supplied to the pair of switching elements of the first push-pull circuit and the second pulse modulation signal which is output from the second pulse modulation circuit have mutually opposite levels. A drive circuit which converts the drive pulse into a pair of drive pulses and supplies the drive pulse to the pair of switching elements of the second push-pull circuit, and in each of the first and second power amplifiers, the first A load is connected between the output end of the push-pull circuit and the output end of the second push-pull circuit, and the first power amplifier of the first power amplifier is connected. Beauty second pulse modulation signal, the 1
A power amplifier device which is a signal which rises at the start of the cycle period, and the first and second pulse modulation signals in the second power amplifier are signals which fall at the end of the one cycle period; To do. Therefore, the radiation generated in the first power amplifier and the radiation generated in the second power amplifier cancel each other out, and the radiation as a whole is reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a general 2-channel stereo, a left channel and a right channel are paired. Further, also in a multi-channel stereo capable of forming a surround sound field, the front channel and the rear channel are a pair of a left channel and a right channel. That is, many audio devices have an even number of channels and therefore an even number of power amplifiers.

The present invention focuses on such a point and reduces the radiation in the class D amplifier. Hereinafter, one mode of the power amplifier device according to the present invention will be described with reference to FIG.

In FIG. 1, reference numerals 10L and 10R denote left and right channel class D power amplifiers, respectively, and a left and right channel digital audio signal P.
L and PR are input terminals TL of the power amplifiers 10L and 10R,
It is supplied to TR respectively.

Then, in the power amplifier 10L,
The digital audio signal PL supplied to the input terminal TL is supplied to the PWM modulation circuit 11L, and a clock (carrier signal) having a predetermined frequency is supplied from the clock forming circuit 12 to the PWM modulation circuit 11L, and the audio signal PL is It is converted into a pair of PWM signals PAL and PBL.

In this case, as shown in FIG. 3, the pulse widths of the PWM signals PAL and PBL change according to the level indicated by the audio signal PL, but the pulse width of one PWM signal PAL is The level of the digital audio signal PL is set to the level, and the pulse width of the PWM signal PB is set to the 2's complement of the level of the digital audio signal PL. The PWM signals PAL and PBL are
The rising time point is fixed to the starting time point of the one-cycle period Tc of the PWM signals PAL and PBL, and the falling time point changes depending on the level indicated by the audio signal PL.

Further, the carrier frequency fc (= 1 / Tc) of the PWM signals PAL and PBL is the digital audio signal P.
For example, the sampling frequency fs of L is set to 16 times, and fs = 4
At 8 kHz, fc = 16fs = 16 × 48kHz = 768kHz.

Then, one PWM signal PAL from the PWM modulation circuit 11L is supplied to the drive circuit 13L and, as shown in FIG. 2A, a pair of drive pulse voltage + PAL having the same level and level inverted as the signal PAL. , -P
AL is formed. In this case, since the pulse voltage + PAL is the drive voltage of the same level as the signal PAL, the rising time point is fixed to the starting time point of the one cycle period Tc of the PWM signal PAL, and the falling time point is the audio signal PL.
Changes according to the level indicated by. Also, the pulse voltage −
Since PAL is a drive voltage obtained by inverting the level of the signal PAL, the rising time point changes corresponding to the level indicated by the audio signal PL, and the falling time point is fixed at the ending time point of the one cycle period Tc.

Then, these pulse voltages + PAL, -P
AL is supplied to a pair of switching elements, for example, the gates of n-channel MOS-FETs (Q11, Q12). In this case, the FETs (Q11, Q12) form the push-pull circuit 15L, the drain of the FET (Q11) is connected to the power supply terminal TPWR, and the source thereof is F.
It is connected to the drain of ET (Q12) and this FET (Q1
The source of 2) is connected to ground. Also, the power supply terminal TPWR
Is supplied with a stable DC voltage + VDD as a power supply voltage. The voltage + VDD is, for example, 20V to 50V.

Further, the source of the FET (Q11) and F
The drain of ET (Q12) is connected to one end of the speaker 19L through a low-pass filter 17L composed of, for example, a coil and a capacitor.

The other PWM signal PBL from the PWM modulation circuit 11L is also constructed in the same manner as for the PWM signal PAL. That is, the PWM signal PBL is supplied to the drive circuit 14L and, as shown in FIG.
A pair of drive pulse voltages + PBL and -PBL having the same level as the BL and the level thereof inverted is formed.

In this case, the pulse voltage + PBL is the signal PBL
Since the drive voltage is at the same level as, the rising time is fixed at the starting time of one cycle period Tc of the PWM signal PAL, and the falling time changes corresponding to the level indicated by the audio signal PL. Also, pulse voltage-PBL
Is a drive voltage obtained by inverting the level of the signal PBL, the rising time changes corresponding to the level indicated by the audio signal PL, and the falling time changes for one cycle period T.
Fixed at the end of c.

Then, these pulse voltages + PBL, -PBL
Are supplied to the gates of a pair of n-channel MOS-FETs (Q13, Q14) that form the push-pull circuit 16L. The source of the FET (Q13) and F
The ET (Q14) drain has a speaker 19L through a low-pass filter 18L having a coil and a capacitor.
Is connected to the other end of.

Further, the power amplifier 10 for the right channel
The R is also configured similarly to the left-channel power amplifier 10L, and the suffix L having the same reference numeral is replaced with the suffix R in the portion corresponding to the circuit and the signal of the power amplifier 10L, and the description thereof will be omitted.

However, in this case, in the power amplifier 10R for the right channel, the PWM signals PAR and PBR output from the PWM modulation circuit 11R rise as in the PWM signals PAL and PBL as shown in FIG. 3B. The time point is fixed to the start time point of the one-cycle period Tc of the PWM signals PAR and PBR, and the falling time point thereof changes depending on the level indicated by the audio signal PR.
Drive circuits 13R and 14R and push-pull circuit 15
Connection with R and 16R is the left channel power amplifier 1
It is different from that in 0L.

That is, the driving pulse voltages + PAR, -PAR output from the drive circuit 13R are supplied to the gates of the FETs (Q14, Q13) of the push-pull circuit 16R and output by the drive circuit 14R. Pulse voltages of + PBR and -PBR are supplied to the gates of the FETs (Q12, Q11) of the push-pull circuit 15R.

According to such a configuration, the following operation is performed in the power amplifier 10L for the left channel. That is, when + PAL = “H”, −PAL =
It is "L", and the FET (Q11) turns on,
FET (Q12) is turned off, so FET (Q11, Q1
The voltage VAL at the connection point 2) becomes + VDD as shown in FIG. 2C. On the contrary, when + PAL = “L”, −PAL = “H”, the FET (Q11) is turned off and the FET (Q12) is turned on, so VAL =
It becomes 0.

Similarly, when + PBL = "H", -P
BL = “L”, the FET (Q13) turns on and the FET (Q14) turns off. Therefore, the FET (Q13,
The voltage VBL at the connection point of Q14) becomes the voltage + VDD as shown in FIG. 2D. On the contrary, when + PBL = “L”, −PBL = “H”, the FET (Q13) is turned off and the FET (Q14) is turned on, so VBL =
It becomes 0. That is, the output voltages VAL and VBL rise at each start point of the one cycle period Tc, and the PWM signal PA
It falls when it corresponds to L and PBL.

Then, during the period of VAL = + VDD and VBL = 0, as shown in FIGS. 1 and 2E, the FET (Q
The current iL flows from the connection point of (11, Q12) to the connection point of the FETs (Q13, Q14) through the line of the low pass filter 17L → the speaker 19L → the low pass filter 18L.

Further, during the period of VAL = 0 and VBL = + VDD, the low pass filter 18L → speaker 19L → low pass filter 1 from the connection point of the FETs (Q13, Q14).
A current iL flows in the opposite direction to the connection point of the FETs (Q11, Q12) through the 7L line. Furthermore, VAL = VBL
The current iL does not flow during the period of = + VDD and the period of VAL = VBL = 0. That is, the push-pull circuit 15L,
16L constitutes a BTL circuit.

The period during which the current iL flows changes depending on the period during which the original PWM signals PAL and PBL rise, and when the current iL flows through the speaker 19L, the current iL is low-pass filters 17L and 18L. As a result, the current iL flowing through the speaker 19L is an analog current corresponding to the level indicated by the digital audio signal PL and is a power-amplified current. Therefore, the circuit 10L operates as a class D power amplifier, and the power-amplified output is supplied to the speaker 19L.

Further, the right channel power amplifier 10
The same operation is performed in R as well. However, in the power amplifier 10R for the right channel, the connection between the drive circuits 13R and 14R and the push-pull circuits 15R and 16R is different from that in the power amplifier 10L for the left channel, so the push-pull circuit 15
The output voltages VAR and VBR of 5 and 16 change, for example, as shown in FIGS.

That is, for simplification, if the input audio signals PL and PR are monaural signals, the driving pulse voltages + PAR, -PAR, + PBR and -PBR output from the drive circuits 13R and 14R are as shown in the figure. 2F and G, pulse voltage + PAL, -PAL, + PBL, -PBL
The waveform is equal to.

However, when + PAR = "H", -P
Since AR (“L”) and the FET (Q14) is turned on and the FET (Q13) is turned off, VBR = 0. On the contrary, when + PAR = “L”, −PAR =
It is "H" and the FET (Q14) is turned off.
Since the FET (Q13) is turned on, VBR = + VDD.

Similarly, when + PBR = "H", -P
Since BR = “L” and the FET (Q12) is turned on and the FET (Q11) is turned off, VBR = 0. On the contrary, when + PBR = "L", -PBR =
It is "H" and the FET (Q12) is turned off.
Since the FET (Q11) is turned on, VBR = + VDD. That is, the output voltages VAR and VBR are the PWM signals PAL and
It rises at every point corresponding to PBL and falls at the start point of one cycle period Tc.

Therefore, the speaker 19R is shown in FIG.
As shown in, when the current iR flows and the current iR flows through the speaker 19R, the current iR is integrated by the low-pass filters 17R and 18R. As a result,
The current iR flowing through the speaker 19R is an analog current corresponding to the level indicated by the digital audio signal PR and is a power-amplified current. Therefore, the circuit 10R
Is also operating as a class D power amplifier,
The power-amplified output is supplied to the speaker 19R.

In this way, the amplifiers 10L and 10R amplify the power by switching, but as shown in FIGS. 2C, D, H, and I, the output voltages VAL and VBL change at the start of the one-cycle period Tc. Direction (arrow ↑)
And the changing directions (arrows ↓) of the output voltages VAR and VBR are opposite to each other, so that the radiation generated by the change of the output voltages VAL and VBL and the radiation generated by the change of the output voltages VAR and VBR cancel each other. Therefore, the radiation of the entire power amplifier device is reduced.

In particular, since the power amplifier device is built in a predetermined case or cabinet, it has a great effect of reducing the radiation, and it is integrated with the receiver in the power amplifier device like a car audio system or the like. Even if it is placed close to the aircraft, it is possible to reduce the interference of radiation on reception of the broadcast.

Further, since the interference of the radiation on the reception of the broadcast can be reduced in this way, it is possible to reduce the number of members for shielding the receiver against the radiation and reduce the cost. Furthermore, since the receiver can be brought closer to the power amplifier device, it is possible to save space.

FIG. 4 shows the PWM modulation circuit 11L (and 1
1R) is shown. That is, the digital audio signal PL of the input terminal TL is supplied to the ΔΣ modulation circuit 111 to reduce the number of bits while suppressing the quantization noise in the audible band, for example, the quantization frequency (= fc) is 16fs. Is converted into a digital audio signal having a quantization bit number of 6 bits.

Then, this digital audio signal is R
It is supplied to the OM 112 and is converted into parallel digital data indicating the quantization level thereof, and is also supplied to the ROM 113 and converted into parallel digital data indicating the two's complement of the quantization level.
It is supplied to the serial shift registers 114 and 115 and converted into serial signals, that is, PWM signals PAL and PBL.

One of the PWM signals PAL is shaped by the flip-flop circuits 131 and 132 and the inverter 135, and the drive voltages of the PWM waveforms + PAL and -P.
AL is output and the other PWM signal PBL is output to the flip-flop circuits 133 and 134 and the inverter 13.
Drive voltage of PWM waveform + PBL shaped by 6
-PBL is output.

In the above, the power amplifiers 10L, 1
When the output stage of 0R is a BTL circuit,
It can also be a single circuit. FIG. 5 shows one form of such a power amplifier device.

That is, in the power amplifier device shown in FIG. 5, in the power amplifier 10L for the left channel, the PWM signal from the PWM modulation circuit 11L to the drive circuit 13L.
WM signal PAL is supplied to drive pulse voltage + P
AL, -PAL are formed, and these pulse voltages + PAL, -P
AL is supplied to the push-pull circuit 15L. The output terminal of the push-pull circuit 15L is connected to the capacitor 21.
The speaker 19L is connected to one end of the speaker 19L through the L and the low pass filter 17L, and the other end is grounded.

The right channel power amplifier 10R
Is also configured similarly to the left-channel power amplifier 10L. However, in this case, similarly to the power amplifier device of FIG. 1, the power amplifier 10R is composed of the PWM modulation circuit 11R, the drive circuit 14R and the push-pull circuit 16R, and the drive pulse voltages + PBR and -PBR are FE.
It is supplied to T (Q12, Q11).

Therefore, also in this power amplifier device, the digital audio signal PL is supplied to the speaker 19L.
The current iL having the polarity and the magnitude corresponding to the current flows, and the current iR having the polarity and the magnitude corresponding to the digital audio signal PR flows in the speaker 19R, and the power amplification is performed.

In that case, the push-pull circuit 15
As shown in FIGS. 2C and 2H, the output voltages VAL and VAR of L and 15R are pulse voltages that change in opposite directions at the start time point of one cycle period Tc, so that the radiation generated at this start time point cancels each other out. As a result, the radiation of the power amplifier device as a whole is reduced.

The power amplifier device shown in FIG. 6 is similar to the power amplifier device shown in FIG.
The output stage of R has a single circuit, and the push-pull circuits 15L and 15R have power terminals TPWR +,
This is a case where a pair of positive and negative DC voltages + VDD and -VDD are supplied from TPWR-. Therefore, the capacitors 21L and 21R in FIG. 5 can be omitted.

Further, in the power amplifier device shown in FIG. 1, as shown in FIG. 3, the PWM signals PAL, PBL,
PAR and PBR are so-called one-sided modulation type PWM signals in which only the falling edges thereof change in response to the digital signals PL and PR, but the PWM signals PAL, PBL, PAR,
It is also possible to adopt a so-called double-sided modulation method in which both the rising edge and the falling edge of PBR change simultaneously.

FIG. 7 shows the waveforms of the drive pulse voltages + PAL to -PBL, + PAR to -PBR, the output voltages VAL, VBL, VAR, VBR, and the output currents iL, iR when the double-sided modulation method is adopted. Note that FIG. 7 shows a case where the input digital audio signals PL and PR are monaural signals. And
In this case, drive pulse voltage + PAL to -PB
L, + PAR to -PBR and output voltages VAL, VBL, VAR,
In VBR, the positions of the rising edge and the falling edge change around the center point of each cycle period Tc. Therefore, also in the case of this double-sided modulation system, the power-amplified output can be supplied to the speaker.

In the above description, the input signals PL, PR
Is a digital audio signal, but it may be an analog audio signal. In addition, the PWM signal PAL,
PBL, PAR, and PBR may be PNM signals or the like. Further, the PWM modulation circuit 11L and the drive circuits 13L and 14L can be integrated, and the PWM modulation circuit 11R and the drive circuits 13R and 14R can be integrated.

In the above description, the power amplifier 10
Although L and 10R are amplifiers for audio, they can also be used as amplifiers for driving electric power devices such as motors. In addition, speakers 19L, 19R
If an arbitrary load is connected instead of, the operating voltage can be supplied to the load, and the magnitude of the voltage supplied to the load can be changed by changing the input signals PL and PR. Therefore, it can also be used as a variable power supply circuit.

[0062]   [List of abbreviations used in this specification]     BTL: Bridged-Tied Load     D / A: Digital to Analog     MOS-FET: Metal Oxide Semiconductor type FET     FET: Field Effect Transistor     PNM: Pulse Number Modulation     PWM: Pulse Width Modulation

[0063]

According to the present invention, the radiation generated in the power amplifier of one channel and the radiation generated in the power amplifier of the other channel cancel each other, so that the radiation of the power amplifier device as a whole can be reduced. . Therefore, like car audio,
Even if the power amplifier device is integrated with the receiver or arranged close to the receiver, it is possible to reduce the interference of radiation on reception of the broadcast.

Further, from this, it is possible to reduce the number of members for shielding the receiver against radiation, and it is possible to reduce the cost. Furthermore, since the receiver can be brought closer to the power amplifier device, it is possible to save space.

[Brief description of drawings]

FIG. 1 is a system diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the circuit of FIG.

FIG. 3 is a waveform diagram for explaining the circuit of FIG.

FIG. 4 is a system diagram showing one form of a part of the circuit of FIG.

FIG. 5 is a system diagram showing another embodiment of the present invention.

FIG. 6 is a system diagram showing another embodiment of the present invention.

FIG. 7 is a waveform chart for explaining the present invention.

FIG. 8 is a system diagram for explaining the present invention.

FIG. 9 is a waveform diagram for explaining the circuit of FIG.

10 is a waveform diagram for explaining the circuit of FIG.

[Explanation of symbols]

10L and 10R ... Power amplifier, 11L and 11
R ... PWM modulation circuit, 12 ... Clock forming circuit, 13
L, 13R, 14L and 14R ... Drive circuit, 15
L, 15R, 16L and 16R ... Push-pull circuit,
17L, 17R, 18L and 18R ... Low-pass filter, 19L and 19R ... Speaker

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Satake             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Ippei Teraguchi             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F term (reference) 5J091 AA02 AA17 AA41 AA66 CA41                       FA08 HA09 HA29 HA33 KA04                       KA32 KA33 KA36 KA42 KA62                       SA05 TA01 TA06 UW01 UW10                 5J500 AA02 AA17 AA41 AA66 AC41                       AF08 AH09 AH29 AH33 AK04                       AK32 AK33 AK36 AK42 AK62                       AS05 AT01 AT06 WU01 WU10

Claims (4)

[Claims] 1. A first power amplifier and a second power amplifier, wherein each of the first and second power amplifiers converts an input signal into a first pulse-modulated signal indicating its quantization level. A first pulse modulating circuit for outputting, a second pulse modulating circuit for converting the input signal into a second pulse modulating signal indicating the two's complement of the quantization level and outputting the second pulse modulating circuit, and a pair of switching elements Convert the first pulse modulation signal output from the first pulse modulation circuit into a pair of drive pulses having mutually opposite levels. And a drive circuit for supplying the pair of switching elements of the first push-pull circuit with the second pulse modulation signal output from the second pulse modulation circuit. A drive circuit which converts the drive pulse into a pair of drive pulses and supplies the drive pulse to the pair of switching elements of the second push-pull circuit, and in each of the first and second power amplifiers, the first The output end of the push-pull circuit and the second
A load is connected between the output terminal of the push-pull circuit and the first and second pulse-modulated signals in the first power amplifier, which are signals that rise at the start point of the one-cycle period, A power amplifier device in which the first and second pulse modulation signals in the second power amplifier are signals that fall at the end of the one cycle period. 2. A first and second power amplifier, each of which has a pulse modulation circuit for converting an input signal into a pulse modulation signal and outputting the pulse modulation signal, and a pair of pulse modulation circuits. A push-pull circuit in which a switching element is push-pull connected, and the pulse-modulated signal output from the pulse-modulation circuit are converted into a pair of drive pulses having mutually opposite levels, and the pair of switching elements in the push-pull circuit. And a drive circuit for supplying the pulse modulation signal in the first power amplifier, the pulse modulation signal in the first power amplifier is a signal that rises at the start point of the one cycle period, and the pulse modulation signal in the second power amplifier is A power amplifier device in which a signal falls at the end of one cycle period. 3. The power amplifier device according to claim 1 or 2, wherein the pulse modulation signal is a PWM signal. 4. A first power amplifier and a second power amplifier, wherein each of the first and second power amplifiers converts an input signal into a first PWM signal indicating its quantization level and outputs the first PWM signal. A first PWM modulation circuit, a second PWM modulation circuit for converting the input signal into a second PWM signal indicating the two's complement of the quantization level and outputting the second PWM signal, and a pair of switching elements First and second push-pull circuits configured by pull connection, and the first P output from the first PWM modulation circuit.
A drive circuit that converts the WM signal into a pair of drive pulses having mutually opposite levels and supplies the drive pulse to the pair of switching elements of the first push-pull circuit; and the second PWM modulation circuit that outputs the drive circuit. 2 P
A drive circuit for converting the WM signal into a pair of drive pulses having mutually opposite levels and supplying the pair of drive pulses to the pair of switching elements of the second push-pull circuit, and the drive circuit of the first and second power amplifiers. In each case, the output end of the first push-pull circuit and the second end of the second push-pull circuit
A load is connected between the push-pull circuit and the output terminal of the push-pull circuit, and the first and second PWM signals in the first power amplifier rise and fall and the second PWM signal rises and falls.
The power amplifier device in which the positional relationship between the rising and falling edges of the first and second PWM signals in the power amplifier is reversed.