JP2003152132A - Semiconductor multichip package and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor multichip package suitable for increasing the number of elements, quickening the operation, and reducing the size by reducing the wiring length and wiring region for connecting a semiconductor element and a substrate. SOLUTION: Conductive wirings 5 and 7, external connection terminals 10 and insulation films 4, 6 and 9 common to two semiconductor elements 1 are arranged on the circuit forming plane 12 of a semiconductor element group 11 consisting of the two semiconductor elements 1 not separated mechanically from each other and then they are packaged. Since the semiconductor elements 1 are connected with the wiring board through wiring, the region between the semiconductor elements 1 is eliminated and the wiring length can be shortened. A semiconductor multichip package suitable for high speed operation and size reduction can thereby be manufactured by an easy wiring work.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor multichip package for packaging a plurality of semiconductor elements as one package, and a method for manufacturing the semiconductor multichip package.

[0002]

2. Description of the Related Art In recent years, in order to perform image data processing at high speed, a plurality of memory elements represented by DRAM (Dynamic Random Access Memory) are packaged in one package to increase capacity and bus width. The demand for multi-chip packages that have expanded is expanding.

As a conventional multi-chip package, a BGA (ball grid array) type package in which a plurality of semiconductor elements are mounted on a printed wiring board having wiring formed on the surface and inside thereof has been used.

This BGA type package is manufactured as follows. That is, a plurality of semiconductor elements divided into individual pieces from a semiconductor wafer are arranged on one surface of a printed wiring board and fixed to the printed wiring board with an adhesive material.

Next, a pad formed on the surface of the semiconductor element opposite to the surface connected to the printed wiring board and a pad provided around the portion on the printed wiring board where the semiconductor element is mounted are gold. Connect electrically with wiring members such as wires.

This wiring member is connected to the printed wiring board so as to be separated from the surface of the semiconductor element in order to prevent contact with the surface of the semiconductor element other than the pads of the semiconductor element.

After connecting the wiring members, the periphery of the semiconductor element and the pad portion on the printed wiring board are sealed with resin so as to cover the other surface of the printed wiring board with external connection terminals made of solder or the like. Form. As above
A BGA type semiconductor multi-chip package is manufactured.

[0008]

The BGA type multi-chip package described above has an advantage that it can be packaged by the conventional package manufacturing technique.

However, as described above, since the pad of the semiconductor element and the pad provided around the semiconductor element on the printed wiring board are connected by the wiring member, a long wiring member is required.

Further, in the BGA type multi-chip package, the external terminals are arranged in an area array on the surface opposite to the semiconductor element mounting surface of the printed wiring board, and the external terminals are also formed directly below the semiconductor element. There are many.

An input / output signal transmitted between the semiconductor element and an external device is supplied from the semiconductor element to a pad of the printed wiring board around the semiconductor element via a wiring member, and the semiconductor element is connected to the pad in the printed wiring board from the pad. The wiring length in the printed wiring board may become long because it reaches the external terminals directly below.

If these wiring members and the wiring in the printed wiring board become long, the electric capacity (inductance) in the multi-chip package increases, and it may not be possible to sufficiently cope with the speedup.

Further, although it is expected that the number of semiconductor elements mounted in the package will increase in the future, it is necessary to secure a connection region between the pad of the printed wiring board and the wiring member on the printed wiring board around the semiconductor element. Therefore, if the number of elements to be mounted increases, the package size may become larger than the chip size, and it becomes difficult to mount it on a portable information device that requires miniaturization.

Further, when the number of mounted semiconductor elements increases, in the conventional BGA type package manufacturing method as described above, the wiring connection work between the pads on the semiconductor element and the pads on the printed wiring board becomes complicated. ,
This may complicate the manufacturing process, lengthen the manufacturing time, and possibly increase the cost of the product.

An object of the present invention is to reduce the connection wiring length and wiring area between a semiconductor element and a printed board, to increase the number of mounted semiconductor elements, to speed up the operation, and to miniaturize the apparatus, and It is an object of the present invention to realize a semiconductor multi-chip package that can be manufactured by an easy wiring operation and a method for manufacturing the semiconductor multi-chip package.

[0016]

In order to achieve the above object, the present invention is configured as follows. (1) In a semiconductor multi-chip package, a plurality of semiconductor elements each having a signal input / output pad formed on a circuit formation surface and a semiconductor element formed on the circuit formation surface of the semiconductor element,
At least a part is provided with a multi-layer insulating film common to the plurality of semiconductor elements, and a conductive wiring formed on the insulating film and connected to the pad.

(2) Preferably, in the above (1),
An external connection terminal, which is joined to a part of the conductive wiring and is connected to an external device, is provided.

According to the above construction, the conductive wiring can be formed within the projection surface of the semiconductor element circuit formation surface, and the wiring length from the pad of the semiconductor element to the external connection terminal connection portion of the conductive wiring can be shortened. can do.

Furthermore, since it is not necessary to secure a connection area for the conductive wiring around the semiconductor element, the package size can be made substantially the same as a plurality of element sizes to be mounted, and the package size can be reduced. Can be achieved.

(3) In a semiconductor multi-chip package, a plurality of semiconductor elements having signal input / output pads formed on the circuit forming surface and a first insulating layer formed on the circuit forming surface of the semiconductor element. A film, a first conductive wiring formed on the first insulating film and connected to the pad, and at least a part of the first insulating film common to the plurality of semiconductor elements Second insulating film, a second conductive wiring formed on the second insulating film and connected to the first conductive wiring, the second insulating film, and the second insulating film. And a third insulating film for surface protection, which is formed on the conductive wiring and is formed by exposing a part of the second conductive wiring.

(4) Preferably, in the above (3),
An external connection terminal that is joined to a part of the second conductive wiring and is connected to an external device is provided.

(5) Further, preferably, in the above (3), a characteristic inspection terminal is provided which is formed on the first conductive wiring and which is connected to an external device for inspecting the characteristic of the semiconductor element. .

With the above structure, the wiring length of the conductive wiring can be shortened, and the package size can be reduced. Further, by forming the characteristic inspection terminal of the semiconductor element on the conductive wiring, the terminal interval can be expanded and the characteristic inspection becomes easy.

(6) In the method of manufacturing a semiconductor multi-chip package, the pads are exposed on a semiconductor wafer having a plurality of semiconductor element regions on the main surface of which a pad for signal input / output is formed on the circuit formation surface. Forming an insulating film on the insulating film, forming a conductive wiring connected to the pad on the insulating film, and externally connecting the conductive wiring to the surfaces of the insulating film and the conductive wiring. And a step of forming an insulating film for surface protection common to a plurality of semiconductor elements and separating the semiconductor wafer into a predetermined number of semiconductor element regions.

(7) Preferably, in the above (6),
The method further includes the step of joining an external connection terminal to the conductive wiring.

(8) In the method of manufacturing a semiconductor multi-chip package, the pads are exposed on a semiconductor wafer having a plurality of semiconductor element regions on the main surface of which a pad for signal input / output is formed on the circuit formation surface. Forming a first insulating film, forming a first conductive wiring connected to the pad on the first insulating film, and at least a part of which is a plurality of semiconductor elements And a step of forming a second insulating film having a predetermined portion exposed on the first insulating film, and a step of forming the second insulating film by the exposed predetermined portion of the second insulating film. Forming a second conductive wiring connected to the first conductive wiring on the second insulating film; and forming a second conductive wiring on the second insulating film and the second conductive wiring,
The external connection terminal joint portion of the second conductive wiring is exposed,
The method includes a step of forming a third insulating film for surface protection common to a plurality of semiconductor elements, and a step of separating the semiconductor wafer into a predetermined number of semiconductor element regions.

(9) Preferably, in the above (8),
The method further includes the step of joining an external connection terminal to the conductive wiring.

(10) Further, preferably, in the step (8), the step of forming a characteristic inspection terminal of the semiconductor element on the first conductive wiring and inspecting the characteristic of each semiconductor element, Further prepare.

According to the method for manufacturing a semiconductor multi-chip package described above, a package can be manufactured by utilizing the wiring and insulating film forming technology for forming a semiconductor element on a wafer, and a plurality of semiconductor elements are mounted in a wafer state. It becomes possible to package the multi-chip package.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a schematic sectional view of a semiconductor multi-chip package which is a first embodiment of the present invention. 2 and 3 are plan views of the semiconductor multi-chip package shown in FIG. 1 with a part of the insulating film removed.

As shown in FIG. 1, the semiconductor multi-chip package according to the first embodiment of the present invention includes a semiconductor element group 11 including two semiconductor elements 1, a passivation film 3, and a first insulating film. 4, the first conductive wiring 5, the second insulating film 6, the second conductive wiring 7, the land 8, the third insulating film 9, and the external connection terminal 10.

The semiconductor element 1 has a circuit forming surface 12
Are formed, and the pads 2 are formed on the circuit forming surface 12. Further, the passivation film 3 is formed on the circuit forming surface 12, and the first insulating film 4 formed on the passivation film 3 is formed.

The first conductive wiring 5 is made up of the first insulating film 4
It is formed above and one end thereof is connected to the pad 2. The second insulating film 6 is formed on the first insulating film 4, the second conductive wiring 7 is formed on the second insulating film 6, and one end thereof is connected to the first conductive wiring 5. .

The land 8 is formed on a part of the second conductive wiring 7, the third insulating film 9 exposes a part of the land 8, and the second insulating film 6 and the conductive wirings 5, 7 are formed. Cover the surface of.
The external connection terminal 10 is joined to the land 8.

Here, the first insulating film 4, the second insulating film 6, the third insulating film 9 and the like correspond to the conventional printed wiring board.

The two semiconductor elements 1 each provided with the pad 2 are divided into regions by a boundary line a, but they are not separated from each other but integrally form a semiconductor element group 11. .

2 and 3 are plan views seen from the surface side on which the external terminals 10 are formed. FIG. 2 is a diagram in which the second insulating film 6 is partially removed from the external connection terminals 10. FIG. 3 is a diagram in which the third insulating film 9 is partially removed.

As shown in FIGS. 2 and 3, the pads 2 are arranged in tandem in the central portion of the circuit forming surface 12 of one semiconductor element 1, and a part of the pad 2 is exposed from the passivation film 3. ing. The first insulating film 4 is formed on the passivation film 3, but the pad 2 is also partially exposed from the first insulating film 4.

One end of the first conductive wiring 5 is connected to the pad 2, and the other end is on the first insulating film 4 and the end portion 1 of the semiconductor element.
It has been extended to the vicinity of 3. A wide portion 15 for joining the second conductive wiring 7 is provided near the semiconductor element end portion 13 of the first conductive wiring 5.

Further, the second insulating film 6 exposes the wide portion 15 of the first conductive wiring, and the first insulating film 4 extends across a plurality of semiconductor elements 1 divided by the boundary line a. Formed on. That is, the second insulating film 6 is one film shared by the plurality of semiconductor elements 1, and is continuously formed on the surfaces of the plurality of semiconductor elements 1.

One end of the second conductive wiring 7 is joined to the wide portion 15 of the first conductive wiring 5, and the second portion is formed from this joined portion.
It is extended on the insulating film 6, and the other end is connected to the land 8 that joins the external connection terminal 10.

Further, the third insulating film 9 for surface protection exposes a part of the land 8 on the circuit forming surface 12 of the semiconductor element 1, and the first insulating film 4 and the first conductive wiring. 5,
The second insulating film 6 and the second conductive wiring 7 are covered. The external connection terminal 10 is joined to the land 8 exposed from the third insulating film 9.

The pad 2 of the semiconductor element 1 and the external connection terminal 10 are electrically connected via the first and second conductive wirings 5 and 7, and the land 8. As is clear from the above description, the insulating film has a three-layer structure of the first to third insulating films 4, 6 and 9.

In the semiconductor multi-chip package shown in the first embodiment of the present invention, the conductive wirings 5, 7, the external connection terminals 10 and the insulating films 4, 6, 9 common to the two semiconductor elements 1. , Which are not mechanically separated from each other 2
The semiconductor element group 11 including the individual semiconductor elements 1 is arranged on the circuit forming surface 12 and packaged.

As a result, the area between the semiconductor elements for connecting the semiconductor element and the wiring board by wiring is unnecessary, and the package size can be made substantially the same as the size of the semiconductor element group 11.

The first and second conductive wirings 5 and 7 from the pad 2 to the land 8 for joining the external connection terminal 10 are mainly formed in the two-dimensional plane of the surface of the insulating film (three-dimensional direction). In addition, the second insulating film 6 is formed only in the thickness direction), and the wiring length can be shortened as compared with the case where the conventional gold wire is used for the wiring member.

Further, as shown in FIG. 2, on the first conductive wiring 5 joined to the pad 2 of the semiconductor element 1, a wiring 16 connecting from a plurality of pads 2 to one wide portion 15 can be formed. .

These are common wires such as a power supply and a ground. Since the number of the wide portions 15 of the first conductive wiring 5 can be reduced by such common wiring, the interval between the wide portions 15 can be made wider than the interval between the pads 2, and the wide portion 15 can be formed. The size can be increased.

As a result, the joint area between the wide portion 15 and the second conductive wiring 7 can be increased, and the joint reliability can be improved.

Copper (Cu) is used for the conductive wirings 5 and 7.
Alternatively, materials such as aluminum (Al), gold (Au), and silver (Ag) are used alone or in an alloy state using a plurality of materials. Further, the surface may be plated with nickel (Ni), chromium (Cr), or the like.

Further, the land 8 connected to the conductive wiring 7 may be formed of the same material as the conductive wiring 7, and the surface thereof may be plated with nickel (Ni), gold (Au) or the like.

The external connection terminals 10 are made of solder material (for example, Pb-Sn eutectic solder, Sn-Ag-Cu).
After a spherical solder material or a paste-like solder material is placed on the land 8 using a system solder or the like, the solder is melted and bonded to the land 8.

For the insulating films 4, 6 and 9, liquid or film-shaped polyimide resin, polyetherimide resin, acrylic modified epoxy resin, rubber-blended epoxy resin, silicone resin or the like can be used.

If a material having a lower elastic modulus than the first insulating film 4 and the third insulating film 9 is used for the second insulating film 6,
When the multi-chip package is mounted on the mounting board by the external connection terminals 10, the effect of reducing the thermal strain generated in the external connection terminals 10 can be obtained.

This is because when a material having a low elastic modulus is used for the second insulating film 6, the thermal strain generated in the external connection terminal 10 due to the difference in the linear expansion coefficient between the multi-chip package and the mounting substrate is the second. This is because it is alleviated by the deformation of the insulating film 6.

By using a material having a low elastic modulus for the second insulating film 6, the reliability of the multi-chip package mounted product can be improved.

It is desirable that the film thickness of the second insulating film 6 be larger than that of the first insulating film 4. Thereby, the electric capacitance (inductance) generated between the first conductive wiring 5 and the second conductive wiring 7 can be reduced, and the signal noise generated when the semiconductor element 1 operates at high speed can be suppressed.

As described above, according to the semiconductor multi-chip package of the first embodiment of the present invention, the conductive wirings 5, 7, the external connection terminals 10 and the two semiconductor elements 1 are provided.
The common insulating films 4, 6, 9 are arranged and packaged on the circuit forming surface 12 of the semiconductor element group 11 composed of two semiconductor elements 1 which are not mechanically separated from each other.

This eliminates the need for a region between the semiconductor elements for connecting the semiconductor element and the wiring board by wiring, and the wiring length can be shortened.
It is possible to realize a semiconductor multi-chip package which is optimal for speeding up the operation and downsizing the device and which can be manufactured by an easy wiring operation.

Further, since the length of the conductive wirings 5 and 7 connecting the pad 2 and the external connection terminal 10 can be shortened and the generation of noise can be suppressed, the operation speed of the multi-chip package can be increased. .

In the semiconductor multi-chip package according to the first embodiment of the present invention shown in FIG. 1, the boundary line a
The semiconductor elements 1 are divided into regions, and the two semiconductor elements 1 each provided with the pad 2 are integrally formed without being separated from each other to form a semiconductor element group.

However, the semiconductor element group forming the semiconductor multi-chip package according to the present invention may be formed by a plurality of semiconductor elements 1 separated from each other in each element region.

FIG. 4 is a schematic sectional view of a semiconductor multi-chip package according to a second embodiment of the present invention in which two semiconductor elements 1 separated from each other are bonded by an adhesive member 17 to form a semiconductor element group 11. Is.

In FIG. 4, the semiconductor elements 1 are joined together by an adhesive member 17 provided on the non-circuit forming surface 14 of the semiconductor element 1 to form a semiconductor element group 11. Similar to the first embodiment shown in FIG. 1, the circuit formation surface 12 of the semiconductor element 1
The insulating films 4, 6, 9 and the conductive wirings 5, 7 and the external connection terminal 10 are formed on the top of the semiconductor multi-chip package.

The semiconductor multi-chip package having the structure shown in FIG. 4 which is the second embodiment of the present invention has the same effect as that of the example shown in FIG. This has an effect that it is effective when a memory and an SRAM (Static Random Access Memory) are combined with each other to form a small multi-chip package.

FIG. 5 is a diagram for explaining a method of manufacturing a semiconductor multi-package according to the first embodiment of the present invention shown in FIG.

In FIG. 5A, a passivation film 3 having a plurality of semiconductor elements 1 divided by a boundary line a and exposing a part of a pad 2 formed on a circuit forming surface 12 is formed on a semiconductor wafer. 18 is formed.

Next, as shown in FIG. 5B, the first insulating film 4 is formed on the surface of the semiconductor wafer 18 by the potting method, spin coating method, printing method or so that a part of the pad 2 is exposed. It is formed by pasting a film material.

A part of the pad 2 is exposed from the first insulating film 4 by covering the exposed part of the pad 2 with a mask and
A method of forming a material to be the insulating film 4 and removing the mask after the formation is performed. Alternatively, a method may be used in which the material of the first insulating film 4 is formed on the entire surface of the semiconductor wafer 18, the portion other than the exposed portion is covered with a mask, and the insulating film material in the exposed portion is removed by an etching method.

Next, in FIG. 5C, the first conductive wiring 5 is formed on the surface of the first insulating film 4 in a predetermined wiring pattern, one end thereof is bonded to the pad 2, and the other end is formed. It is extended to the vicinity of the region boundary line a of the semiconductor element 1.

A wide portion 15 having a wide width in the plane direction is formed in the first conductive wiring 5 in the vicinity of the region boundary line a of the semiconductor element 1. The first conductive wiring 5 is formed by a plating method, a sputtering method, or the like.

Subsequently, in FIG. 5D, the second insulating film 6 is formed so that the wide portion 15 of the first conductive wiring 5 provided near the region boundary line a of the semiconductor element 1 is exposed. It is formed on the first insulating film 4 and the first conductive wiring 5.

Next, in FIG. 5E, the second conductive wiring 7 is formed on the surface of the second insulating film 6 in a predetermined wiring pattern, and one end of the second conductive wiring 7 is formed in the wide portion of the first conductive wiring 5. The land 8 is formed on the second insulating film 6 and is joined to the external connection terminal 10.

Subsequently, in FIG. 5F, the land 8
Of the third insulating film 9 for surface protection so as to expose a part thereof and cover the vicinity of the region boundary line a of the semiconductor element 1, the surface of the second insulating film 6, and the surface of the second conductive wiring 7. To form. The part of the land 8 is exposed from the third insulating film 9 by a method of covering the exposed part of the land 8 with a mask and forming a material to be the third insulating film 9.

Alternatively, the material of the third insulating film 9 is formed on the exposed portion of the land 8 and the portion other than the exposed portion is covered with a mask.
A method of removing the insulating film material in the exposed portion by an etching method or the like is used.

If necessary, a thin film of a metal material such as Ni or Au is formed on the exposed portion of the land 8 by a plating method or a sputtering method.

Next, in FIG. 5G, flux is applied to the exposed portion of the land 8 to place a spherical solder material, and the solder is melted to form the external connection terminal 10.

Finally, in FIG. 5 (h), the wafer is cut along the area boundary line a of the predetermined semiconductor element 1 constituting the semiconductor multi-chip package, and the two wafers shown in the first embodiment of the present invention are cut. Semiconductor element group 1 consisting of semiconductor elements 1
The semiconductor multi-chip package configured in 1 is obtained.

The manufacturing technique of the multi-chip package according to the present invention shown in FIG. 5 is the same as the wafer process technique of manufacturing a semiconductor element in a wafer state. Therefore, by using the wafer process technology to manufacture a multi-chip package including a plurality of semiconductor element groups in a wafer state, it becomes possible to manufacture small packages at once.

As described above, according to the method of manufacturing a semiconductor multi-chip package of the present invention, the connection wiring length and the wiring area between the plurality of semiconductor elements and the printed circuit board are reduced, and the number of mounted semiconductor elements is increased. It is possible to realize a semiconductor multi-chip package and a method for manufacturing a semiconductor multi-chip package which are optimal for high-speed operation and miniaturization of a device and which can be manufactured by an easy wiring operation.

In the multi-chip package according to the first embodiment shown in FIG. 1, the other end of the first conductive wiring 5 having one end bonded to the pad 2 extends from the pad 2 toward the end 13 of the semiconductor element 1. However, the extending direction from the pad 2 of the first conductive wiring 5 is not limited to one direction as shown in FIG. 1, and it may be two or more directions. good.

FIG. 5 shows the manufacturing method of the example shown in FIG. 1. However, in the case of the example shown in FIG. 4, a plurality of semiconductor elements 1 separated from each other are assembled and bonded to each other with an adhesive. After that, it can be manufactured by a method similar to the method shown in FIG.

FIGS. 6 and 7 are a schematic cross-sectional view of a semiconductor multi-chip package according to a third embodiment of the present invention and a plan view when a part of an insulating film is removed.

In the above-described first embodiment, the first
The extending direction of the conductive wiring 5 from the pad 2 is one direction of the end portion 13 of the semiconductor element group 11, but in the third embodiment, the extending direction of the first conductive wiring 5 from the pad 2 is. In the direction of the end 13 of the semiconductor element group 11 and the semiconductor element 1
This is an example in which there are two directions of the area boundary a direction (direction of the central part).

The basic structure of the third embodiment is the same as that of the multi-chip package according to the first embodiment shown in FIG. 1, except that the first conductive material bonded to the pad 2 of the semiconductor element 1 is used. The wiring 5 extends from the pad 2 to the end 1 of the semiconductor element.
It extends in two directions, namely, the three directions and the boundary a direction of the semiconductor element region.

The wide portion 15 for joining the second conductive wiring 7 is also formed in the vicinity of the end portion 13 of the semiconductor element 1 and in the region boundary a portion of the semiconductor element 1, and the second conductive wiring 7 is provided for each of them. Are joined.

With the above-described structure, the wiring length from the pad 2 of the semiconductor element 1 to the land 8 to which the external connection terminal 10 is joined can be further shortened.

Therefore, according to the third embodiment of the present invention, the same effect as in the first embodiment can be obtained, and the operation in the semiconductor multi-chip package can be further speeded up.

The installation place of the wide portion 15 for joining the second conductive wiring 7 is not limited to the vicinity of the end portion 13 of the semiconductor element or the semiconductor element 1 region boundary a portion, but the land 8 is formed. It can be installed at any place according to the location.

Further, in the semiconductor multi-chip package shown in the first embodiment, an example in which the semiconductor element group 11 is formed by the two semiconductor elements 1 has been shown.
The number of semiconductor elements 1 constituting the above is not limited to two, and may be three or more.

FIG. 8 is a schematic sectional view of a semiconductor multi-chip package according to the fourth embodiment of the present invention. 9 is a plan view of the multi-chip package shown in FIG. 8 with a part of the insulating film removed.

The basic structure of the multi-chip package is the same as that of the first embodiment shown in FIG.
The feature different from the embodiment is that an inspection terminal 19 for inspecting the characteristics of the semiconductor element 1 is formed in a part of the first conductive wiring 5.

As shown in FIG. 2, the inspection terminal 19 is provided in the same manner as the wide portion 15 by sharing the power supply and the ground.
The distance between the pads 2 can be made wider than the distance between the pads 2, and the size of the inspection terminal 19 can be increased.

This facilitates the contact of the inspection probe with the inspection terminals 19, and when manufacturing the multi-chip package in the wafer state as in the manufacturing method shown in FIG. Inspection becomes possible, and labor in the inspection process can be reduced.

As described above, according to the fourth embodiment of the present invention, the same effect as that of the first embodiment can be obtained, and since the inspection terminal 19 is formed, the inspection probe is used. This has the effect that the inspection can be performed easily.

Since the inspection terminals 19 are formed in the fourth embodiment, the semiconductor multi-chip package manufacturing method according to the fourth embodiment is
In addition to the step of forming the characteristic inspection terminal 19 of the semiconductor element 1, it is possible to further include a step of inspecting the characteristic of each semiconductor element 1 using the characteristic inspection terminal 19.

FIG. 10 is a schematic sectional view showing the fifth embodiment of the semiconductor multi-chip package according to the present invention.
FIG. 11 is a plan view of the multi-chip package shown in FIG. 10 with a part of the insulating film removed.

The semiconductor multi-chip package according to the fifth embodiment of the present invention shown in FIG.
Two semiconductor elements 1 each having a pad 2 provided thereon, a passivation film 3 formed on a circuit forming surface 12 of the semiconductor element 1, and a first insulating film 20 formed on the passivation film 3. It has and.

Further, the semiconductor multi-chip package shown in FIG. 10 is formed on the first insulating film 4, and one end of the conductive wiring 21 is connected to the pad 2 and a part of the conductive wiring 21 is formed. Land 22 and this land 22
To expose a part of the first insulating film 20 and the conductive wiring 21.
A second insulating film 23 that covers the surface of the above, and an external connection terminal 10 joined to the land 22.

Then, as shown in FIG. 10, the two semiconductor elements 1 which are divided into areas by the boundary line a and each provided with the pad 2 are integrated without being separated from each other, and the semiconductor element group 11 is formed. Is formed.

Further, as shown in FIG. 11, the pad 2 is
The semiconductor elements 1 are arranged in tandem in the central portion of the circuit forming surface 12, and a part of the pad 2 is formed on the passivation film 3
Exposed from.

Then, the first insulating film 20 is formed on the passivation film 3 so that a part of the pad 2 is exposed. Further, one end of the conductive wiring 21 is connected to the pad 2, and the other end is provided with a land 22 for joining the external connection terminal 10 on the first insulating film 20.

Further, the second insulating film 23 for surface protection
On the circuit formation surface 12 of the semiconductor element 1, a part of the land 22 is exposed to cover the first insulating film 20 and the conductive wiring 21.

The external connection terminal 10 is joined to the land 22 exposed from the second insulating film 23. In the above-described first to fourth embodiments, the insulating film has a three-layer structure of the first to third layers, but in the fifth embodiment, the insulating film is the first insulating film. 20 and the second insulating film 23 have a two-layer structure.

In the semiconductor multi-chip package according to the fifth embodiment, the insulating film 20, 23, the conductive wiring 21, and the external connection terminal 10 are formed into a circuit of a semiconductor element group 11 including two semiconductor elements 1. Place it on surface 12,
Package.

As a result, the package size becomes substantially the same as the size of the semiconductor element group 11. Further, since the insulating film has a two-layer structure of the first insulating film 20 and the second insulating film 23, the package thickness can be reduced.

Further, since the conductive wiring 21 from the pad 2 to the land 22 for joining the external connection terminal 10 is formed within the two-dimensional plane of the surface of the insulating film 20, it is used as a wiring member as in the prior art. The wiring length can be shortened as compared with the case of using a gold wire.

Further, since the pad 2 and the land 22 are connected by the conductive wiring 21 of one layer, the wiring length can be made shorter than that of the multi-chip package of the first embodiment shown in FIG. This is advantageous when forming a multi-chip package with semiconductor elements that need to be integrated.

That is, according to the fifth embodiment of the present invention, the same effect as that of the first embodiment can be obtained, and further, the package thickness can be further reduced, and a semiconductor element which requires a high speed is multi-chip. This has the advantage of being advantageous when constructing a package.

[0110]

As described above, according to the present invention, the connection wiring length and the wiring area between the semiconductor element and the printed circuit board are reduced, the number of mounted semiconductor elements is increased, the operation speed is increased, and the device It is possible to realize a semiconductor multi-chip package and a method for manufacturing a semiconductor multi-chip package which are optimal for downsizing and can be manufactured by an easy wiring operation.

That is, the size of the semiconductor multi-chip package can be made substantially the same as the size of the semiconductor element group consisting of a plurality of semiconductor elements, and the semiconductor multi-chip package can be miniaturized.

Further, since the length of the conductive wiring connecting the pad of the semiconductor element and the external connection terminal can be shortened and the generation of noise can be suppressed, the operation speed of the semiconductor multi-chip package can be increased.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor multi-chip package that is a first embodiment of the present invention.

FIG. 2 is a plan view of the multi-chip package according to the first embodiment shown in FIG. 1 with a part of a second insulating film and a third insulating film removed.

FIG. 3 is a plan view of the multi-chip package according to the first embodiment shown in FIG. 1 with a part of a third insulating film removed.

FIG. 4 is a schematic sectional view of a semiconductor multi-chip package according to a second embodiment of the present invention.

5A and 5B are diagrams illustrating a method of manufacturing the multi-chip package shown in FIG.

FIG. 6 is a schematic sectional view of a semiconductor multi-chip package according to a third embodiment of the present invention.

FIG. 7 is a plan view of the multi-chip package shown in FIG. 6 with a part of the insulating film removed.

FIG. 8 is a schematic sectional view of a semiconductor multi-chip package according to a fourth embodiment of the present invention.

9 is a plan view of the multi-chip package according to the fourth embodiment shown in FIG. 8 with a part of a third insulating film removed.

FIG. 10 is a schematic sectional view of a semiconductor multi-chip package which is a fifth embodiment of the present invention.

FIG. 11 is a plan view of the multi-chip package according to the fifth embodiment shown in FIG. 10 with a part of the second insulating film removed.

[Explanation of symbols]

1 Semiconductor element 2 pads 3 passivation film 4, 20 First insulating film 5 First conductive wiring 6, 23 Second insulating film 7 Second conductive wiring 8,22 land 9 Third insulating film 10 External connection terminal 11 Semiconductor element group 12 Semiconductor element circuit formation surface 17 Adhesive member 18 wafers 19 Inspection terminal 21 Conductive wiring

Claims (10)

[Claims] 1. A plurality of semiconductor elements having pads for signal input / output formed on a circuit formation surface, and at least a part of the semiconductor elements formed on the circuit formation surface common to the plurality of semiconductor elements. A semiconductor multi-chip package comprising: a multi-layer insulating film; and a conductive wiring formed on the insulating film and connected to the pad. 2. The semiconductor multi-chip package according to claim 1, further comprising an external connection terminal joined to a part of the conductive wiring and connected to an external device. 3. A plurality of semiconductor elements having signal input / output pads formed on the circuit forming surface, a first insulating film formed on the circuit forming surface of the semiconductor element, and the first insulating film. A first conductive wiring formed on an insulating film and connected to the pad; and a second insulating film having at least a part common to the plurality of semiconductor elements on the first insulating film. And a second conductive wiring formed on the second insulating film and connected to the first conductive wiring, and formed on the second insulating film and the second conductive wiring. Is
And a third insulating film for protecting the surface, which is formed by exposing a part of the second conductive wiring, and a semiconductor multi-chip package. 4. The semiconductor multi-chip package according to claim 3, further comprising an external connection terminal which is joined to a part of the second conductive wiring and which is connected to an external device. package. 5. The semiconductor multi-chip package according to claim 3, further comprising a characteristic inspection terminal formed on the first conductive wiring and connected to an external device for inspecting the characteristic of the semiconductor element. A semiconductor multi-chip package characterized by. 6. A step of forming an insulating film by exposing the pads on a semiconductor wafer having a plurality of semiconductor element regions on the main surface of which a pad for inputting and outputting a signal is formed on a circuit formation surface A step of forming a conductive wiring connected to the pad on the insulating film, and a surface of the insulating film and the conductive wiring, the external connection terminal joint portion of the conductive wiring is exposed, a plurality of A method of manufacturing a semiconductor multi-chip package, comprising: a step of forming an insulating film for surface protection common to semiconductor elements; and a step of separating the semiconductor wafer into a predetermined number of semiconductor element regions. 7. The method of manufacturing a semiconductor multi-chip package according to claim 6, further comprising the step of bonding an external connection terminal to the conductive wiring. 8. A first insulating film is formed by exposing the pads on a semiconductor wafer having a main surface having a plurality of semiconductor element regions having signal input / output pads formed on the circuit formation surface. A step of forming a first conductive wiring connected to the pad on the first insulating film, at least a part of which is common to a plurality of semiconductor elements, and a predetermined part is exposed. Forming a second insulating film on the first insulating film, and connecting the first insulating film to the first conductive wiring by the exposed predetermined portion of the second insulating film. Forming a second conductive wiring on the second insulating film, and joining an external connection terminal of the second conductive wiring to the second insulating film and the second conductive wiring. A step of forming a third insulating film for surface protection, which is exposed in a portion and is common to a plurality of semiconductor elements; And a step of separating the semiconductor wafer into a predetermined number of semiconductor element regions, and a method of manufacturing a semiconductor multi-chip package. 9. The method of manufacturing a semiconductor multi-chip package according to claim 8, further comprising the step of bonding an external connection terminal to the conductive wiring. 10. The method for manufacturing a semiconductor multi-chip package according to claim 8, wherein the first conductive wiring comprises:
A method of manufacturing a semiconductor multi-chip package, further comprising the step of forming a characteristic inspection terminal of the semiconductor element and inspecting the characteristic of each semiconductor element.