JP2003152103A - Vertical internal connection trench cell (v-ictc) of semiconductor memory device and method of forming the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dynamic RAM (DRAM) device having a vertical transistor and an internal connection strap (ICS) connecting the vertical transistor to a capacitor. SOLUTION: An ICS is not brought into direct contact with a substrate. A DRAM cell is made to operate with a capacity smaller than a capacity required by a conventional buried strap trench (BEST) while all the negative influences upon the performance of a device are practically not caused. Further, the smaller capacity does not need a new material or a new processing method and extends the possibility in a manufacturing technology of a deep trench capacitor. A method of manufacturing a DRAM also includes a process forming a separation film replacing a conventional frame, and a process forming a very thin Di film on a DT cell. An SOI is formed by an internal thermal oxidation method (ITO) so as to have the device used up completely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices and methods of manufacturing the same, and more particularly to deep trench dynamic random access memories having substantially lower cell capacitance.
access memory (DTDRAM) cell and a method of manufacturing the same.

[0002]

2. Description of the Related Art Dynamic random access memory (DRAM) requires refreshing to retain its accumulated charge. A DRAM cell operates by storing charge on its capacitor for a logic one and no charge for a logic zero. Stable circuit operation is achieved by having a large enough capacitor and charge transfer element to hold the accumulated charge such that the signal-to-noise ratio is sufficient.

The latest deep trench DRAM (DT)
DRAM devices are storage node electrodes.
source / drain (S)
/ D) Almost exclusively relies on buried straps (BS) that electrically connect the joints. Since BS is formed in the Si body through the pn junction, it easily leaks. This leaky connection requires holding a high capacitance level (ie> 40 fF / cell) in order to amplify the signal to overcome RC noise. Typically, this high capacitance requirement has been met through the use of deep trench capacitors that preserve the charge storage capacity of the capacitor while minimizing the surface space required.

[0004]

However, the current reliability in BS technology is not satisfactory in many cases, for example dielectric nodes with high k values, surface enhancements in DT, metals with low resistance in DT. It has driven the exploration of new processes and materials, such as filling. Not only are these approaches expensive but relatively undeveloped, many still need to be tested in a manufacturing environment. Moreover, as DRAMs are scaled down to meet higher density requirements, the increased leakage makes the charge retention problem more pronounced.

The minimum feature size F of a DRAM device is generally known in the art as a ground rule (GR).
Called. To determine the area of a DRAM cell, the width of the cell in the X direction is multiplied by the width of the cell in the Y direction, where both dimensions are expressed in units of square GR, ie a multiple of F ² . In a conventional DRAM design, at least one row line, a space between the row lines, a capacitor, and a contact to a device must be made in the X direction for a total width of 4F. Of course, at least one digit line and the spacing between the digit lines must be made in the Y direction, giving a minimum total cell area 8F ² . As the size of the DRAM array decreases,
As the density of integrated circuits in those DRAM arrays increases correspondingly, new trench gates and the process of forming them are required.

If the design density of DRAM devices requires shrinks (<110 nm) below GR, the formation of their collars becomes extremely difficult. The generally held view is that at GR <100 nm, a vertical transistor has a short-channel effect (S
In order to overcome CE), such a vertical transistor, in principle, has an area of 8F ² or less (sub-8F ² ).
Enables DT DRAM layout. However, it is a fully functional DRA with an area of 8F ² or less.
The actual fabrication of M devices has been hampered to date by excessive BS outdiffusion.

Device development has also tended towards a fully depleted device design that improves speed and incorporates latch-up immunity. Such devices include thin silicon-on-insulator (SO
This can be realized by the I) structure because the SOI device is completely released from latch-up. A great many successful search efforts have been devoted to the formation of robust SOI applications. However, in the past, due to the complexity of process integration, vertical SO
There was less success in forming the I structure.

[0008] Thus, there is a need for a fully exhausted vertical cell that minimizes BS out-diffusion.

[0009]

The present invention discloses a fully exhausted vertical cell with no BS outdiffusion and with a direct connection between the storage node and the transistor. Vertical-internally connecte cell of the present invention
d trench cell) (V-ICTC) overcomes this difficulty by spontaneously forming the frame during the transistor formation process, and the strap allows the frame to be formed without any direct connection to the Si substrate. Connected to the inside. BS out-spreading is thereby avoided.

The present invention also provides an internally connected strap (internally) alternative to the traditional buried strap (BS) structure.
-DRAM using a (connected strap) (ICS) structure
A scheme for the integration of the process of manufacturing a device is provided.
The ICS directly connects the memory storage node to the source / drain (S / D) junction region of the transistor without directly forming the pn junction in the Si body, thereby essentially leaking the pn junction. To remove.

The ICS of the present invention is a deep trench (D
T) The required capacity of a memory cell for a conventional BEST (Buried Strap Trench) cell without causing any negative impact on device performance due to its low leakage characteristics. Allows operation at lower cell capacities. The lower cell capacity requirement of the device of the present invention is k
Current DT capacitor fabrication techniques without the reliability of new, relatively untested materials and fabrication methods such as high value dielectric nodes, surface enhancements, low resistance metal fills, etc. and their implementations. Extend the possibilities in.

The method of manufacturing a V-ICTC according to the present invention comprises an oxide isolation film (isol) buried under a Si substrate by angled implantation of oxygen ions.
ation layer) and then a thermal ann
internal thermal oxidation (ITO), which forms a vertical frame body oxide film by eal) is used. This method forms a very thin Si film on top of the DT cell, and at the same time forms a separation film instead of the conventional frame.

SOI with ITO creates a structure in such a way that the device can be fully depleted. The fully depleted V-ICTC device of the present invention allows designing cell layouts below 8F ² using controlled strap formation. V-ICT of the present invention
The C device is a high performance device with a leak-free, fully isolated thin channel film that reduces the operating power requirement and improves device speed.

[0014]

DETAILED DESCRIPTION OF THE INVENTION For discussion of theoretical background, K. Kawamura, et. Al., G., incorporated herein by reference.
ate Oxide Integrity on ITOX-STMOX Substrates and I
nfluence onTest Device Geometry on Characterizatio
n, IEEE Transactions on ElectronDevices, vol. 48,
No. 2, Feb. 2001, pp307-315 and Lee et al., Plasma
Immersion Ion Implantation as an Alternative Deep
See Trench Buried Plate Doping Technology, ITT 2000.

These and other advantages of the present invention include:
It will be better understood from the following detailed description of the preferred embodiments in connection with the drawings.

Referring now to the drawings, FIG. 19 shows a flow chart of the steps of the present invention. FIG. 1 illustrated in FIG.
DT mask stack deposition and lithography are performed for the step in block 1 of 9. FIG. 1 shows a silicon substrate 10, a pad nitride film 11, and borosilica glass.
s) / Tetraethylorthosilicate
Clone) (BSG / TEOS) hard mask layer 12 and mask 13. DRAM manufacturing is silicon (Si)
It requires a precisely controlled amount of impurities to be introduced into a small area of the substrate. Substantially these areas must be interconnected. A pattern defining such a region is manufactured by a lithographic process. Bilevel scheme, or chemical amplification of resist lines
The (CARL) process may be used. Hard anti-reflective coating (HAR
C) or Poly (Poly) hard mask deposition, followed by a continuous pattern transfer scheme.
e) can be used to attenuate the reflectivity at the resist interface, thus providing a minimal reduction in resist performance for linewidth control.

That is, a film of photoresist material is first spin-coated on a Si wafer substrate 10 having, for example, a pad nitride film, a hard mask layer, and an ARC film deposited thereon. The resist is then selectively exposed to some form of radiation using the exposure means and mask 13 to provide the desired selective exposure.

Then, with respect to the step in block 2 illustrated in FIG. 2, the wafer transfers this pattern to the deep trench mask open (DTMO) and polyresist (PR) strips. When the step is performed, the resist pattern is transferred to the hard mask layer. The transfer of the pattern transforms the latent image in the resist into the final image. The resulting resist image 20 after pattern transfer serves as a mask in subsequent etching or ion implantation steps. Conventional mask opening scheme and differential mask opening scheme
cheme) and both are applicable at this step.
It should be noted that for the DT pattern, a hard mask is needed to etch the Si. Therefore, the development processing step is not sufficient for the image transfer step.

The areas of resist remaining after the development process protect the areas of the substrate that they cover. The location where the resist was removed then undergoes a reduced DTMO and DT-Si etch for the step in block 3 illustrated in FIG. This destructive etching is the final DT
The pattern is transferred to the surface of the Si substrate. The etch depth 30 for the device of the present invention may vary as a function of GR, but due to the relatively low capacitance requirement of the present invention, the conventional buried strap trench (BES).
T) About half the depth required by the cell specifications.

With respect to the step in block 4 illustrated in FIG. 4, the BSG / TEOS film 12 is stripped and Si
An N liner 40 was deposited and the next polycrystalline (Pol
Protect the Si substrate 10 during the fabrication and removal of the recess in y). DT is a sacrificial intrinsic (int
rinsic) Filled with polycrystalline (or amorphous Si). Chemical mechanical polishin
g) (CMP) step is optionally performed,
Polycrystalline recess formation 42 then follows to a depth sufficient to form vertical transistors with the ICS.

With respect to the step in block 5 illustrated in FIG. 5, a sacrificial frame 51 is deposited, and then reactive ion etching (re) of the frame is performed for a subsequent wet process.
The bottom 52 of the frame 51 is opened by active ion etching (RIE). The frame 51 and the SiN liner 40 are eroded from the upper part of the trench 5 during the wet bottle process.
Protect 0. The frame 51 also has internal thermal oxidation (ITO).
It can act as a protective oxide during the implant and anneal steps. Ozone TEOS or low temperature oxide deposition may be used.

With respect to the step of block 6 illustrated in FIG. 6, the sacrificial polycrystalline (or amorphous Si) removal, SiN removal, and wet bottle steps are performed on a protected polycrystalline frame ( BPC) in a similar manner. Wet bottle process uses active SO
Optimized to protect part of I. Further, in this preferred embodiment, the interface between the SOI oxide film and the Si film is formed in the next step, but is not laterally protected during the wet bottle process. For example, if the thickness 60 of the active SOI is 50 nm, the wet process requires etching the side surface by 50 nm or more.

With respect to the steps of block 7 illustrated in FIG. 7, PR fill 70, PR pull back 7
1 and Internal Thermal Oxidation (ITO) implant 72 is performed by a graded implant method. The depth of the depression is optimized so as not to expose the bottom of the frame 51 to prevent excessive oxidation of the DT node region. At the same time, a sufficient oxidation height of SOI, which is as deep as or deeper than the frame 51, is obtained. Implant angle, energy, and depth are also optimized to meet these requirements.

With respect to the steps of block 8 illustrated in FIG. 8, PR removal 80, buried plate
e) Dope (BP) 81, clean DT, and form node dielectric 82. After complete removal of PR70, BP doping is performed and gas phase doping (Gas Phas
e Doping) is the preferred choice because of its compatibility and high dosing capacity. In another embodiment, plasma doping may also be used, but its energy should be optimized so as not to degrade the SOI by the penetration of excess arsenic dopant into the active SOI region. . Form a conventional NO node dielectric. Instead of A
l ₂ O ₃ (A1203) or another high k-value material can be integrated as a supplemental option. The effective thickness of node dielectric 82 is determined by the operating voltage and capacitance requirements. The implanted oxygen species are annealed, accumulated on each other, and damaged S, similar to a conventional separation by implanted oxygen (SIMOX) process.
i recrystallizes during the hot node dielectric processing step.

With respect to the steps of block 9 illustrated in FIG. 9, removal of the sacrificial frame 51 and SiN liner 40,
Polycrystalline-1 deposition, (optional CMP planarization), polycrystalline depression-1 fabrication. Similar to the conventional DT scheme, the doped poly as the poly-1 deposition 90 (polycrystalline fill) is then followed by the optional CMP planarization and fabrication of the dimple-1. The depth 91 of the depression must be lower than DT1 (DT at the top).

With respect to the steps of block 10 illustrated in FIG. 10, selective polycrystalline (or Si) of ICS 100.
Ge) deposition and ICS doping. Hemi-spherical grain (HSG) polycrystal and Si
Both Ge and can be used. Additional surface amorphization steps may be required for HSGs. Intrinsic polycrystalline (or SiGe) and in-sit (in-sit) following the separate doping step
u) Both doping can be used. In the case of in-situ doping, the deglazing step must be followed immediately after the deposition step. A modified touch-up recess can be used to remove all residue on sidewalls 92 of DT1. The thickness of the deposited ICS 100 is optimized so as not to interfere with the vertical cell channel technology.

Regarding the step of block 11 illustrated in FIG. 11, S / D 111 and threshold voltage (V _t ) implantation, Trench Top Oxide (TT).
O) 112 is formed. In another embodiment, the source / drain implantation and V _t implant step may placed step process that other intervening. Implantation beveled about V _t implant, and the source - a straight infusion related drain implanting (straight Implantation), can be used respectively. The PR protects the ICS in the trench for straight implants.

With respect to the step of block 12 illustrated in FIG. 12, formation of a gate oxide film and a gate electrode is performed. By forming a uniform gate oxide film 120 and avoiding microcrystal-dependent oxidation, either a surface amorphization technique or another wet oxidation method can be used. Gate electrode 121
(Or gate conductivity type stack) is formed using polycrystalline or other metal gate electrode material.

With respect to the step of block 13 illustrated in FIG. 13, the removal of the pad nitride film 11 and the polycrystalline CMP of the gate are performed. Remove the pad nitride film and oxide film,
The upper film 72 injected with Si10 and ITO is not protected. The gate poly 121 is polished down to the Si substrate 10 and planarized.

With respect to the steps of block 14 illustrated in FIG. 14, oxide depressions and surface straps (surfac).
The e strap (SS) 140 is formed. Upper SOI
The oxide layer 72 is removed, allowing the formation of a surface strap (SS) 140 that electrically connects between the S / D 111 and the bit line contact (CB).
The surface strap 140 is now formed by CMP planarization followed by the deposition of doped polycrystalline. In-situ polycrystalline doping schemes require a frosting step.

With respect to the step of block 15 illustrated in FIG. 15, a pad oxide film and a new nitride film 150 are deposited.

With respect to the steps of block 16 illustrated in FIG. 16, the isolation trench (I
T) 160, cutting gate polycrystal 121, TTO11
2, ICS 100, and about 150 nm polycrystalline-19
0 forms the array devices to a depth sufficient to separate them. The integration procedure is lithography → ITMO
Etching → IT layer etching → Wet cleaning → AA
The oxidation method → HDP oxide film → CMP. Sputtering and etching procedures may be used to etch deep IT 160. Oxide or other hard mask may be used. The IT layout depends on the device design and layout. The illustrated picture is 8F ² L / S
It relates to the IT pattern of (line / space).

For the step of block 17 illustrated in FIG. 17, both CB pads and word line pads are formed. The CB pad 170 is formed by implantation and annealing, and the word line pad 171 is formed by a polycrystalline L / S (line / space) stud.

With respect to the step of block 18 illustrated in FIG. 18, borophosphos glass.
Deposition of ilicate glass) (BPSG) 181, CB / C
S (bit line contact / general source line (bit line c
ontact / common source line)) Etching and M
O etching is performed. The normal BPSG deposition is the upper T
This is performed together with the EOS film 182. SAC (self-aligned contact (se
lf-aligned contact)) A dedicated control gate for CB / CS integrated etching for etching.
(CG) etching continues. The submitted contact scheme can be performed with ion mixing. Ti / TiN by either PVD or CVD as a barrier layer followed by MO damascene etching and thermal annealing
Deposition is performed before W deposition. The CVD W deposition is preferably performed using dichlorosilane (DCS) source gas, followed by W CMP and wet cleaning.

Finally, the back-end of the line (back-e
nd DRA (BEOL) process
Manufacture of M is completed.

Although the present invention has been described in terms of a preferred embodiment, alternatives have been cited by the foregoing discussion and those skilled in the art will be able to carry out the invention with modifications within the spirit and scope of the appended claims. Recognize.

[Brief description of drawings]

1 is a cross-sectional view illustrating the structure of the present invention appearing in the first step of the method of the present invention described in the flowchart of FIG.

2 is a cross-sectional view illustrating the structure of the present invention appearing in the second step of the method of the present invention described in the flowchart of FIG.

FIG. 3 is a cross-sectional view illustrating the structure of the present invention appearing at the third step in the method of the present invention described in the flowchart of FIG.

FIG. 4 is a cross-sectional view illustrating the structure of the present invention appearing in the fourth step of the method of the present invention described in the flowchart of FIG.

5 is a cross-sectional view illustrating the structure of the present invention appearing in the fifth step of the method of the present invention described in the flowchart of FIG.

FIG. 6 is a cross-sectional view illustrating the structure of the present invention appearing in the sixth step of the method of the present invention described in the flowchart of FIG.

7 is a cross-sectional view illustrating the structure of the present invention appearing at the seventh step in the method of the present invention described in the flowchart of FIG.

8 is a cross-sectional view illustrating the structure of the present invention appearing at the eighth step in the method of the present invention described in the flowchart of FIG.

9 is a cross-sectional view illustrating the structure of the present invention appearing in the ninth step of the method of the present invention described in the flowchart of FIG.

10 is a cross-sectional view illustrating the structure of the present invention appearing in the tenth step of the method of the present invention described in the flowchart of FIG.

FIG. 11 is a cross-sectional view illustrating the structure of the present invention appearing in the eleventh step of the method of the present invention described in the flowchart of FIG.

12 is a cross-sectional view illustrating the structure of the present invention appearing in the twelfth step of the method of the present invention described in the flowchart of FIG.

13 is a cross-sectional view illustrating the structure of the present invention appearing in the thirteenth step of the method of the present invention described in the flowchart of FIG.

14 is a cross-sectional view illustrating the structure of the present invention appearing in the fourteenth step of the method of the present invention described in the flowchart of FIG.

FIG. 15 is a cross-sectional view illustrating the structure of the present invention appearing in the fifteenth step of the method of the present invention described in the flowchart of FIG.

16 is a cross-sectional view illustrating the structure of the present invention appearing at the 16th step in the method of the present invention described in the flowchart of FIG.

17 is a cross-sectional view illustrating the structure of the present invention appearing in the 17th step of the method of the present invention described in the flowchart of FIG.

18 is a cross-sectional view illustrating the structure of the present invention appearing at the 18th step in the method of the present invention described in the flowchart of FIG.

FIG. 19 is a flow chart of the method of the present invention.

[Explanation of symbols]

10 Silicon Substrate 11 Pad Nitride Film 12 Borosilicate Glass (BSG) / Tetraethyl Orthosilicate (TEOS) Film 13 Mask 20 Resist Image 30 Etching Depth 40 SiN Liner 42 Polycrystalline Dip 50 Trench Top 51 Frame 52 Frame Bottom 60 Active SOI thickness 70 Polycrystalline resist (PR) filling 71 Polycrystalline resist (PR) pullback 72 Internal thermal oxide (ITO) 80 Polycrystalline resist (PR) removal 81 Buried plate (BP) 82 Node dielectric 90 Polycrystalline Deposit 91 Depth of Depth 92 Sidewall 100 Internal Connection Strap (ICS) 111 Source / Drain (S / D) 112 Trench Top Oxide (TTO) 120 Gate Oxide 121 121 Gate Electrode 140 Surface Strap (SS) 150 New nitride film 160 Isolation trench (IT 170 bit line contacts (CB) pad 171 word lines pad 181 Houhosuhokei silicate glass (BPSG) deposit 182 upper tetraethylorthosilicate (TEOS)
film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H01L 29/78 626A (72) Inventor Wei Wan, 179 Wuling Road, Hsinchu City, Taiwan Mura A22 F term (reference) 5F083 AD02 AD03 AD17 AD62 GA09 GA27 HA02 JA32 JA39 JA40 KA07 NA01 PR01 PR03 PR05 PR12 PR21 PR22 PR29 PR33 PR36 PR37 PR39 PR40 5F110 AA04 AA06 BB06 CC09 DD05 DD13 DD21 EE02 EE0925EE22 GG22 FF22 FF22 FF22 FF22 FF22 FF22 FF22 NN02 NN22 NN33 QQ04

Claims (13)

[Claims] 1. A vertical internally connected trench cell device for a microelectronic device comprising: (a) a substrate; (b) at least one deep trench formed in the substrate; and (i) a vertical trench. Type transistor, (ii) a capacitor, and (iii) an internal strap connecting the transistor to the capacitor, wherein the internal strap is within the at least one deep trench without directly contacting the substrate. A device characterized by full entry. 2. A vertically interconnected trench cell device for a microelectronic device, comprising: (a) a semiconductor substrate having a deep trench therein, (b) a capacitor formed in the trench, and (c) the trench. A vertical transistor formed in
And (i) a gate-conductivity-type stack formed in the trench, and (ii) first and second source / drain regions located on sidewalls of the deep trench. A buried plate, the first and second source / drain regions are separated from each other by the substrate, and (d) the strap is completely within the deep trench without direct connection with the substrate. The device electrically connects the capacitor and the vertical transistor to each other. 3. The device of claim 2, wherein the strap connects the capacitor to one of the source / drain regions. 4. The device of claim 2, wherein the vertical transistor further comprises an oxide film above the strap and below the gate conductivity stack. 5. A surface strap formed on the substrate for contacting one of the first and second source / drain regions, and outside the deep trench for contacting the surface strap. A bit line pad formed on the semiconductor substrate; and a word line pad formed on the gate conductive type stack for contacting the gate conductive type stack. Item 2. The device according to Item 2. 6. The device of claim 2, further comprising an oxide film formed on the substrate to contact the buried plate and the source / drain regions. 7. The device of claim 6, wherein the oxide film is formed by internal thermal oxidation implantation. 8. A method of forming a dynamic random access memory cell having a vertical transistor together with an internal connection strap without directly connecting to a substrate, comprising: (a) a plurality of resists provided on a silicon substrate. The step of transferring the pattern including the location of (b), the step of developing the pattern transferred in the step (a) to selectively remove the resist, and (c) the resist in the step (b). Etching deep trenches in the silicon substrate at each of the plurality of locations removed by: (d) selectively coating sidewalls of each of the deep trenches etched in step (e) with a SiN liner. And (e) a first deposit in each of said deep First filling in a wrench and making a recess with a depth sufficient to form vertical transistors therein with interconnect straps; (f) depositing a frame around each of the deep trenches And opening the bottom of the frame in each of the deep trenches so that each of the frames has the same depth, and (g) removing the first deposit from each of the deep trenches. And then performing a wet step of cleaning the SiN liner and etching each side of the deep trench, and (h) a second fill in each of the deep trenches with a second deposit and the frame. Making a depression having a depth such that the bottom of the body is covered, (i) the Si surrounding each deep trench
Implanting an oxide film having a depth at least equal to the depth of the frame behind the SiN liner at the top of the substrate; (j) removing the second deposit; B) selectively doping a buried plate at a relatively low portion of the sidewalls of each of said deep trenches by driving a dopant into said substrate at said relatively low portion; and (l) each said deep trench. Cleaning the trench, (m) forming a node dielectric on the relatively lower portion of the sidewall of each of the deep trenches, and (n) relatively upper side of the sidewall of each of the deep trenches. Removing the frame and the SiN liner from the portion of D) making a third fill with a third deposit and making a depression in each of the deep trenches that is lower than the height of the relatively upper portion of the sidewall; and (p) each of the deep trenches. Depositing a doped interconnect strap on top of the third deposit, and (q) source into the surface of the substrate at the relatively upper portion of the sidewall in each of the deep trenches. / R drain and threshold voltage implants; (r) forming a trench top oxide over each interconnect trench in each deep trench; and (s) exposing each deep trench. Forming a gate oxide film along the sidewalls, and (t) forming a gate oxide film in each of the deep trenches. Positioning the cathode electrode. 9. The method of claim 8, wherein step (i) is accomplished by a step of internal thermal oxidation. 10. The method of claim 8, further comprising forming a recessed surface strap on the memory cell and electrically connecting to the source / drain. 11. The method further comprises forming isolation trenches between the deep trenches, the isolation trenches having a depth sufficient to isolate an array device of which the memory cell is a part, 9. The method of claim 8, wherein the trench has a layout that depends on the design and layout of the memory cell. 12. The method further comprises implanting a bit line contact pad on the surface of the substrate and connected to the recessed surface strap to form a word line contact pad in contact with the gate electrode. 9. The method according to claim 8, characterized in that 13. (u) further planarizing the memory cell to provide an unprotected planarized substrate surface, an unprotected planarized implanted oxide layer, and a level of the unprotected substrate surface. Producing a surface of the planarized gate electrode at: (v) forming a recessed surface strap on top of the unprotected implanted oxide to form the source / source
Electrically connecting to the drain, (w) depositing pad oxide and nitride on the memory cell, and (x) a depth sufficient to isolate the array device of which the memory cell is a part. Forming isolation trenches between the deep trenches, the height of which is dependent on the design and layout of the memory cells, and (y) of the unprotected substrate connected with the recessed surface straps. Implanting a bit line contact pad on the surface and contacting the surface of the planarized gate electrode to form a word line contact pad, (z) on the bit ship contact pad and the word line contact pad The method of claim 8 including the step of forming a contact.