JP2003147049A - Embedding resin and wiring board using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an embedding resin having both of a low viscosity and high reliability caused by matching thermal expansion coefficients, and further to provide a wiring board having an electronic part arranged in an opening part formed in an insulating substrate, and embedded by using the embedding resin. SOLUTION: This embedding resin has <=85 Pa.s viscosity at 8.4 s<-1> shear rate after being allowed to stand at 25±1 deg.C for 24 hr. An acid anhydride curing agent having <=170 mPa.s viscosity at 25±1 deg.C is used as the curing agent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an embedded resin for embedding electronic components such as chip capacitors, chip inductors, and chip resistors in an insulating substrate, and a wiring board in which the electronic components are embedded in an insulating substrate. .
Particularly, it is suitable for a multilayer wiring board, a package for housing a semiconductor element, and the like.

[0002]

2. Description of the Related Art In recent years, a multi-chip module (MCM) in which many semiconductor elements are mounted on a build-up wiring board
Is being considered. When mounting electronic components such as a chip capacitor, a chip inductor, and a chip resistor, it is common to carry out surface mounting using solder on a mounting wiring layer formed on the surface of a wiring board.

However, when electronic parts are surface-mounted on the surface of the build-up wiring board, a predetermined mounting area corresponding to each electronic part is required, and therefore there is a natural limit to miniaturization. In addition, there is a problem in that the parasitic inductance, which is unfavorable in terms of characteristics, increases due to the routing of the wiring during surface mounting, and it becomes difficult to cope with higher frequencies of electronic devices.

In order to solve these problems, various methods of embedding electronic parts inside the insulating substrate have been studied.
Japanese Unexamined Patent Application Publication No. 11-126978 discloses a method of soldering an electronic component on a wiring board with a transfer sheet, which is made of a metal foil in advance, and then transferring the same. Japanese Patent Laid-Open No. 2000-124352 discloses a multilayer wiring board in which an insulating layer is built up on an electronic component embedded inside a core board.

[0005]

In a method of embedding an electronic component inside an insulating substrate such as a core substrate, a gap between the insulating substrate and the electronic component is filled with a filling resin, and the insulating layer is built up on the gap. It is necessary to electrically connect the formed wiring layer and the electrode of the electronic component by electroless plating or the like. At that time, in order to secure the connection reliability, it is necessary to wrap the embedded resin in the minute gaps between the electrodes of the electronic component. Therefore, the embedded resin needs to have a low viscosity. In addition, considering the usage environment, it is necessary to lengthen the pot life at room temperature (the time during which the curing reaction proceeds to some extent, but the handleability of the embedded resin is kept good).

There are roughly two methods for adjusting the viscosity of the embedding resin. Specifically, it is a method of adjusting the addition amount of the filler, and a method of using a kind of curing agent having a slow curing speed.

Generally, the viscosity can be lowered by reducing the amount of the filler added. However, in order to prevent the occurrence of defects due to the difference in thermal expansion coefficient between materials, it is necessary to match the thermal expansion coefficient of the embedded resin with the thermal expansion coefficient of the material that will be the core substrate or build-up material to some extent. There is. For that purpose, it is necessary to add a certain amount of filler or more.
Thus, it was difficult to achieve both low viscosity and reliability simply by increasing or decreasing the amount of filler added.

According to the present invention, an embedded resin that achieves both low viscosity and high reliability due to matching of thermal expansion coefficients and a wiring embedded with an electronic component arranged in an opening provided in an insulating substrate using the embedded resin. An object is to provide a substrate.

[0009]

[Means for Solving the Problems] Considering the method of using the embedded resin, it is necessary to lower the viscosity in a one-liquid state in which a resin component, an acid anhydride curing agent, a curing accelerator, and an inorganic filler are mixed. There is. Considering workability such as filling,
The viscosity after standing at 25 ° C. ± 1 ° C. for 24 hours is 85 Pa · s or less, preferably 6 at a shear rate of 8.4 s ⁻¹ .
It is preferable to use an embedding resin that can be maintained at 0 Pa · s or less, and more preferably 45 Pa · s or less. More preferably, the viscosity after standing at 25 ° C. ± 1 ° C. for 48 hours should be 85 Pa · s or less, preferably 60 Pa · s or less, and more preferably 55 Pa · s or less at a shear rate of 8.4 s− ¹ . It is preferable to use an embedded resin that can By setting the materials so that the viscosity can be kept low for a long time,
Since it is possible to suppress the increase in viscosity during the operation at room temperature, it is possible to prevent the occurrence of defects such as defective filling and improve the yield.

As the curing agent, an acid anhydride curing agent having a viscosity of 170 mPa · s or less, preferably 100 mPa · s or less, more preferably 60 mPa · s or less at 25 ° C. ± 1 ° C. may be used. The acid anhydride curing agent is a material that contributes to lowering the viscosity of the embedded resin. By using a curing agent having a viscosity as low as possible, it is possible to reduce the viscosity of the embedded resin itself. Since the acid anhydride curing agent having a viscosity of 170 mPa · s or less behaves as a Newtonian fluid unlike the embedding resin, the viscosity thereof does not greatly vary depending on the shear rate. Therefore, the viscosity may be measured at a shear rate different from the shear rate at the time of measuring the embedded resin (8.4 s ⁻¹ ).

Further, by using an extremely low viscosity material as the curing agent, even if the curing reaction of the embedding resin proceeds to some extent,
Can be used with low viscosity (that is, long pot life). As a result, it is possible to obtain effects such as improvement in workability and prevention of air bubbles from being trapped when the filling resin is filled. Moreover, since it is possible to reduce the viscosity of the embedded resin by using a low-viscosity curing agent, it is desirable to use a low-viscosity curing agent.

The acid anhydride curing agent is preferably a phthalic anhydride type. In particular, methyltetrahydrophthalic anhydride or methylhexahydrophthalic anhydride is preferable because of its high storage stability.

In the embedding resin of the present invention, by further optimizing the content of the filler, the filling property can be improved more effectively. The preferable content of the filler is 51 to 74% by mass. Mixing ratio of filler is 5
If the amount is less than 1% by mass, the difference in thermal expansion between the core substrate and the material to be the build-up material becomes large, which causes cracks when heat cycle is applied. On the other hand, if the content of the filler exceeds 74% by mass, the viscosity of the embedding resin will be high, and the filling property will be significantly deteriorated, causing bubbles to be trapped.

The embedding resin of the present invention is preferably an embedding resin in which at least one kind of inorganic filler is added to the resin component. The reason for adding the inorganic filler is to prevent the shape of the embedding resin after the roughening treatment from being collapsed more than necessary due to the adjustment of the thermal expansion coefficient and further the effect of the inorganic filler as an aggregate.

The inorganic filler is not particularly limited, but crystalline silica, fused silica, alumina, silicon nitride and the like are preferable. The coefficient of thermal expansion of the embedded resin can be effectively reduced. As a result, the reliability of the heat cycle is improved.

Regarding the filler diameter of the inorganic filler, it is preferable to use a filler having a particle diameter of 50 μm or less because the embedded resin must easily flow into the gaps between the electrodes of the electronic component. If it exceeds 50 μm, the filler is likely to be clogged in the gap between the electrodes of the electronic component, and a portion having an extremely different coefficient of thermal expansion locally occurs due to defective filling of the embedded resin. The lower limit of the filler diameter is preferably 0.1 μm or more. If it is smaller than this, it becomes difficult to secure the fluidity of the embedded resin. The thickness is preferably 0.3 μm or more, more preferably 0.5 μm or more. In order to achieve low viscosity and high filling of the embedded resin, the particle size distribution may be widened.

The shape of the inorganic filler is preferably substantially spherical in order to enhance the fluidity and filling rate of the embedded resin. In particular, the silica-based inorganic filler is preferable because spherical particles can be easily obtained.

The surface of the inorganic filler may be surface-treated with a coupling agent if necessary. This is because the wettability of the inorganic filler with the resin component is improved, and the fluidity of the embedded resin can be improved. As the type of coupling agent, silane-based, titanate-based, aluminate-based, etc. are used.

In the wiring board in which the electronic component is embedded by using the embedded resin of the present invention, the electronic component is arranged in the opening provided in the insulating substrate, and the gap in the opening is described above. It is characterized in that it is filled with the embedded resin. As used herein, "embedding an electronic component" means an opening (a through hole (eg, FIG. 1) or a recess such as a cavity (eg, FIG. 10) provided in an insulating substrate such as a core substrate or a built-up insulating layer. After arranging the electronic component therein, it means filling the gap created between the electronic component and the opening with the embedding resin. As a specific example, a capacitor built-in flip chip package as shown in FIGS. 1 and 10 can be formed. Not only the bump grid array type package illustrated here, but also a pin grid array type package can be used. The opening may be a through hole formed by punching a substrate or a cavity formed by a multi-layering technique. The substrate used in the present invention is preferably a so-called core substrate such as FR-4, FR-5, BT, etc., but a core substrate is formed by sandwiching a thick copper foil of about 35 μm in a thermoplastic resin sheet such as PTFE. You may use what formed the opening part in what was said. Further, a build-up layer in which insulating layers and wiring layers are alternately laminated is formed on at least one surface of the core substrate, and an opening is formed so as to penetrate at least one of the core substrate and the build-up layer. You can In this case, even in a multilayer wiring board with a built-in capacitor as shown in FIG. 11, the so-called glass-epoxy composite material (insulating board) has a thickness of about 400 μm, which is as thin as half of 800 μm of a normal product. There is an advantage that the height can be reduced. Note that the electronic parts include passive electronic parts such as chip capacitors, chip inductors, chip resistors, and filters, transistors, semiconductor elements, FETs,
It includes active electronic components such as a low noise amplifier (LNA), or electronic components such as a SAW filter, an LC filter, an antenna switch module, a coupler and a diplexer.

By ensuring a sufficient pot life at room temperature and using a low-viscosity embedding resin, the embedding resin can sufficiently sneak into the minute gaps between the electrodes of the electronic component. Therefore, the wiring board of the present invention can be a wiring board with a built-in electronic component that is highly reliable against heat cycles.

On at least one surface of the core substrate, a build-up layer in which insulating layers and wiring layers are alternately laminated is formed, and multilayer wiring using a substrate in which an opening is formed so as to penetrate the core substrate and the build-up layer. The substrate may be manufactured, for example, as follows (FIGS. 11 to 25).

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A wiring board having a so-called "FC-PGA" structure shown in FIG. 11 will be described below. As shown in FIG. 12, an FR-5 double-sided copper-clad core substrate prepared by adhering a copper foil (200) having a thickness of 18 μm to an insulating substrate (100) having a thickness of 0.4 mm is prepared. The characteristics of the core substrate used here are Tg (glass transition point) by TMA of 175 ° C., CTE (thermal expansion coefficient) of the substrate surface direction of 16 ppm / ° C., and CTE (thermal expansion coefficient) of the substrate surface vertical direction of 50 ppm / The dielectric constant ε at 4.7 ° C. and 1 MHz is 4.7, and the tan δ at 1 MHz is 0.018.

A photoresist film is attached on the core substrate and exposed and developed to form an opening having a diameter of 600 μm and an opening (not shown) corresponding to a predetermined wiring shape. The copper foil exposed in the opening of the photoresist film is removed by etching using an etching solution containing sodium sulfite and sulfuric acid. The photoresist film is peeled and removed to obtain a core substrate having an exposed portion (300) as shown in FIG. 13 and an exposed portion (not shown) corresponding to a predetermined wiring shape.

Commercially available etching equipment (made by MEC)
CZ treatment device) is used to perform an etching treatment to roughen the surface of the copper foil, and then a thickness 35 mainly composed of epoxy resin
A μm insulating film is attached to both sides of the core substrate. Then, the insulating layer is formed by curing at 170 ° C. for 1.5 hours. The characteristics of the insulating layer after this curing are TMA.
Tg (glass transition point) by 155 ° C., Tg (glass transition point) by DMA is 204 ° C., CTE (coefficient of thermal expansion) 66 ppm / ° C., permittivity ε at 1 MHz is 3.7, and tan δ at 1 MHz is 0. 033, 30
Weight loss at 0 ° C is -0.1%, water absorption is 0.8%, moisture absorption is 1%, Young's modulus is 3 GHz, and tensile strength is 63M.
Pa and elongation is 4.6%.

As shown in FIG. 14, a via hole (50) for interlayer connection is formed in the insulating layer (400) by using a carbon dioxide laser.
0) is formed. The form of the via hole is a serpentine shape having a surface layer diameter of 120 μm and a bottom diameter of 60 μm. Further, the output of the carbon dioxide laser is increased to form a through hole (600) having a diameter of 300 μm so as to penetrate the insulating layer and the core substrate. The inner wall surface of the through hole has a waviness (not shown) peculiar to laser processing. Then, after immersing the substrate in a catalyst activating liquid containing palladium chloride,
Electroless copper plating is applied to the entire surface (not shown).

Then, a copper panel plating (700) having a thickness of 18 μm is applied to the entire surface of the substrate. Here, a via hole conductor (800) that electrically connects the layers is formed in the via hole (500). Through hole (60
At 0), through-hole conductors (900) for electrically connecting the front and back surfaces of the substrate are formed. An etching treatment is performed by a commercially available etching treatment device (CZ treatment device manufactured by MEC Co., Ltd.) to roughen the surface of the copper plating. Then, a rust preventive agent (trade name: CZ treatment) is applied by the rust preventive agent of the same company to form a hydrophobic surface, and the hydrophobic treatment is completed. The contact angle 2θ of water on the surface of the conductor layer subjected to the hydrophobization treatment was measured by a liquid-property method with a contact angle measuring instrument (trade name: CA-A, manufactured by Kyowa Kagaku Co., Ltd.), and the contact angle 2θ was 101 degrees. .

The non-woven paper is placed on a pedestal equipped with a vacuum suction device, and the substrate is placed on the pedestal. A stainless mask for filling holes having through holes corresponding to the positions of the through holes is placed thereon. Next, a through-hole filling paste containing a copper filler is placed, and the roller-type squeegee is pressed to fill the holes.

As shown in FIG. 15, through holes (60
0) through hole filling paste (100)
0) is temporarily cured under the condition of 120 ° C. for 20 minutes.
Then, as shown in FIG. 16, after polishing (coarse polishing) the surface of the substrate using a belt sander, buffing (finish polishing) to flatten the surface, and cure at 150 ° C. for 5 hours. Complete the hole filling process. A part of the substrate that has completed this hole filling step is used for the hole filling evaluation test.

As shown in FIG. 17, a through hole (opening: 110) of □ 8 mm is formed by using a mold (not shown). As shown in FIG. 18, a masking tape (120) is attached to one surface of the substrate. Then, as shown in FIG. 19, eight multilayer chip capacitors (130) are arranged on the masking tape exposed in the through holes (110) using a chip mounter. This multilayer chip capacitor has a laminated body (1 mm x 0.6 mm x 0.4 mm (1
50), and the electrode (140) is 70 μm from the laminate.
It is sticking out.

As shown in FIG. 20, the embedded resin (160) of the present invention is filled in the through hole (110) in which the multilayer chip capacitor (130) is arranged by using a dispenser (not shown). The embedded resin is defoamed and heat-cured under the conditions of a primary heating step of 80 ° C. for 3 hours and a secondary heating step of 170 ° C. for 6 hours.

As shown in FIG. 21, the surface of the hardened embedded resin (160) is roughly ground using a belt sander and then finished by lapping. On the polishing surface,
The end surface of the electrode (140) of the chip capacitor (130) is exposed. Then, the temporarily cured embedded resin (1
60) is cured at 150 ° C. for 5 hours.

After that, the swelling liquid and the KMnO ₄ solution are used to roughen the polished surface of the embedded resin (160). After activating the Pd catalyst on the roughened surface, copper plating is performed in the order of electroless plating and electrolytic plating. As shown in FIG. 22, a plating layer (170) formed on the embedded resin (160).
Are electrically connected to the end faces of the electrodes (140) of the chip capacitor (130). A resist (not shown) is formed on the plated surface, and a predetermined wiring pattern is patterned. Unnecessary copper is etched away using Na ₂ S ₂ O ₈ / concentrated sulfuric acid. The resist is peeled off, and the formation of the wiring is completed as shown in FIG. The surface of copper plating of the wiring is roughened by performing an etching treatment with a commercially available etching treatment device (CZ treatment device manufactured by MEC Co., Ltd.).

A film (190) serving as an insulating layer thereon
After being laminated and thermally cured, a carbon dioxide laser is irradiated to form a via hole for interlayer connection. The surface of the insulating layer is roughened using the same oxidizing agent as described above, and a predetermined wiring (201) is formed by the same method. A dry film to be a solder resist layer is laminated on the outermost surface of the wiring board, and the mounting pattern of the semiconductor element is exposed and developed to form the solder resist layer (210).
The same method is applied to the back side where the mounting pins are attached, and the predetermined wiring (230) and the solder resist layer (2
40) is formed to obtain a multilayer printed wiring board before pinning, as shown in FIG.

Terminal electrodes (201) for mounting semiconductor elements
Is plated in the order of Ni plating and Au plating (not shown). After printing a solder paste made of low melting point solder on it, a solder bump (220) for mounting a semiconductor element is formed through a solder reflow furnace.

On the other hand, on the side opposite to the semiconductor element mounting surface, after printing a solder paste made of high melting point solder, solder bumps (260) for pinning are formed through a solder reflow furnace. Pin (25) to a jig (not shown)
0) is set and the substrate is placed, and pins are attached through a solder reflow furnace (not shown).
As shown in, FC-PGA before mounting the semiconductor element
A mold multilayer printed wiring board is obtained. Using a projector, the amount of displacement from the predetermined position of the tip of the pin (250) attached to the region corresponding to the opening (110) embedded with the embedded resin (160) was measured and found to be 0.1 mm or less. Good results have been obtained.

A semiconductor element (27
0) is placed at a mountable position, and low melting point solder (22
A semiconductor element is mounted through a solder reflow furnace under a temperature condition in which only 0) is melted. After the underfill material (300) is filled in the mounting portion with a dispenser, it is heat-cured to mount a semiconductor element as shown in FIG.
A semiconductor device using a C-PGA type multilayer printed wiring board is obtained.

In the following, an embodiment of a method for manufacturing a different wiring board according to the present invention will be described. Here, the wiring board shown in FIG. 1 is taken as an example. As shown in FIG. 2, a through hole (2) having a predetermined size is provided in the core substrate (1) by using a mold, a back tape (3) is attached to one surface of the core substrate, and then the back substrate (1) is formed. Place the side with the tape attached on the bottom.

As shown in FIG. 3, the chip capacitor (4) is attached from the other surface to a predetermined position on the adhesive surface of the pack tape (3) in the through hole (opening: 2) using a chip mounter. Deploy. As the chip capacitor used here, it is preferable to use one having an electrode (5) protruding from the capacitor body so that the embedded resin can easily flow around. As shown in FIG. 4, the embedded resin (6) of the present invention is poured into the gap between the chip capacitor (4) arranged in the opening (2) and the opening using a dispenser.

The embedded resin (6) is defoamed and thermoset under the conditions of 100 ° C. × 80 minutes → 120 ° C. × 60 minutes → 160 ° C. × 10 minutes. The surface of the cured resin is
After rough polishing using a belt sander, final polishing is performed by lapping. The surface (60) of the embedded resin (6) after polishing is shown in FIG. Then, as shown in FIG. 6, a via hole (7) is drilled using a carbon dioxide laser to expose the electrode (5) of the chip capacitor (4).

Then, the exposed surface (61) of the embedded resin (6) is roughened using a swelling solution and a KMnO ₄ solution.
After activating the Pd catalyst on the roughened surface, copper plating (8, 9) is performed in the order of electroless plating and electrolytic plating. The state after copper plating is shown in FIG. A resist (not shown) is formed on the plated surface, and a predetermined wiring pattern is patterned. Unnecessary copper is etched away using Na ₂ S ₂ O ₈ / concentrated sulfuric acid. The resist is peeled off to complete the formation of the wiring (90). The state after the wiring is formed is shown in FIG.

A film (14, 1) which will serve as an insulating layer is formed thereon.
After 5) is laminated and heat-cured, a laser is irradiated to form a via hole for interlayer connection. The surface of the insulating layer is roughened using the same oxidizing agent, and a predetermined wiring pattern is formed by the same method. A dry film to be a solder resist layer is laminated on the outermost surface of the wiring board, and a mounting pattern of a semiconductor element is exposed and developed to form a solder resist layer (12). The state is shown in FIG. Ni is used for the terminal electrode (13) for mounting the semiconductor element.
Plating is performed in the order of plating and Au plating. Then, the semiconductor element (18) is mounted through a solder reflow furnace. Solder balls (17) are formed on the electrodes to be mounted on the substrate by using low melting point solder. After filling the mounting portion with the underfill material (21) with a dispenser, it is heat-cured to complete the production of the intended wiring board as shown in FIG.

[0042]

EXAMPLES The operational effects of the wiring board of the present invention will be described below with reference to examples using evaluation samples. The embedded resin is prepared by weighing and mixing the components so that the composition shown in Table 1 is obtained and then kneading with a three-roll mill. here,
Details of the items described in Table 1 are as follows.

Epoxy resin- "HP-4032D": High-purity naphthalene type epoxy resin (manufactured by Dainippon Ink) Hardener "QH-200" (40 mPas): Acid anhydride-based hardener (manufactured by Zeon Corporation)- “B-570” (40 mPa · s): Acid anhydride-based curing agent (manufactured by DIC) · “B-650” (65 mPa · s): Acid anhydride-based curing agent (manufactured by DIC) · “YH-307” ( 200 mPa · s): Acid anhydride type curing agent (made by oiled shell epoxy) “YH-306” (120 mPa · s): Acid anhydride type curing agent (made by oiled shell epoxy) · “YH-300” ( 40 mPa · s): Acid anhydride curing agent (made by Yuka Shell Epoxy) · “KAYAHARD MCD” (250 mPa · s): Acid anhydride curing agent (made by Nippon Kayaku)

Accelerator (Curing accelerator) "2P4MHZ": Imidazole type curing agent (manufactured by Shikoku Chemicals)

Inorganic Filler "TSS-6": Silane Coupling Treated (Tatsumori: Maximum Particle Diameter 24 μm According to Particle Size Distribution)

"Filler content", "carbon content"
Is the value when the epoxy + curing agent + filler is 100%. The “accelerator” is 0.2% when the epoxy + curing agent + filler is 100%. The ratio of the epoxy resin and the curing agent is 100/95 in terms of functional group ratio. The following evaluations are performed on these compositions.

(Reliability Evaluation) The core substrate has a thickness of 0.8 m.
m BT substrate is used. A through hole having a predetermined size is provided in the core substrate by using a mold. After the back tape is attached to one surface of the core substrate, the surface on which the back tape is attached is placed downward. A chip capacitor is arranged using a chip mounter at a predetermined position on the adhesive surface of the pack tape in the opening from the other surface. The embedded resin shown in Table 1 is poured into the gap between the chip capacitor arranged in the opening and the opening using a dispenser.

Embedding resin, 100 ° C. × 80 minutes → 12
Defoam and heat cure under conditions of 0 ° C. × 60 minutes → 160 ° C. × 10 minutes. The surface of the hardened embedded resin is roughly polished by using a belt sander and then finished by lap polishing. Then, a via hole is drilled using a carbon dioxide laser to expose the electrodes of the chip capacitor.

After that, the exposed surface of the embedded resin is roughened using a swelling solution and a KMnO ₄ solution. After activating the Pd catalyst on the roughened surface, copper plating is performed in the order of electroless plating and electrolytic plating. A resist is formed on the plated surface and a predetermined wiring pattern is patterned. Remove unnecessary copper from Na ₂ S ₂ O
₈ / Etch off with concentrated sulfuric acid. The resist is removed to complete the wiring formation.

After laminating a film to be an insulating layer thereon and thermally curing it, a laser is irradiated to form a via hole for interlayer connection. The surface of the insulating layer is roughened using the same oxidizing agent, a predetermined wiring pattern is formed by the same method, and the production of the evaluation sample is completed.

At this time, sample numbers 1 to 1 were used as the embedding resin.
For 9 respectively, 4 hours, 6 hours, 8 hours after preparation,
The embedding resins after 24 hours and 48 hours have been prepared, samples using the respective embedding resins are prepared, and the embedding property is evaluated. The pass / fail criterion is 95% for cavities that did not entrap air bubbles in visual inspection with a magnifying glass.
If there is more than%, it is accepted. If necessary, the buildup layer may be polished and removed so as not to damage the embedded resin, and then the state of the embedded resin may be observed. In Table 2, pass is indicated by ◯, and fail is indicated by x.

Regarding the embedded resins of sample numbers 10 to 15, a thermal shock test (test conditions: -55 ° C to 12 ° C) was conducted.
The thermal shock resistance is evaluated at 5 ° C. for 300 cycles (2 cycles / 1 hour). As a pass / fail criterion, a cracking rate of 5% or less in the visual inspection with a magnifying glass is passed, and the thermal shock resistance is passed. If necessary, the buildup layer may be polished and removed so as not to damage the embedded resin, and then the state of the embedded resin may be observed. In Tables 2 and 3, pass is good and fail is bad.
Indicate.

[0053]

[Table 1]

[0054]

[Table 2]

[0055]

[Table 3]

From the results, it can be seen that good results are obtained in the samples of the examples using the embedding resin of the present invention. On the other hand, in the case of sample numbers 4, 5, 7 and 9 which are comparative examples in which the viscosity of the curing agent exceeds 170 mPa · s, 48
After leaving for a while, the viscosity exceeds 85 mPa · s,
The result was inferior filling property.

[0057]

According to the present invention, the embedding property is good,
It can be seen that an embedded resin and a wiring board using the embedded resin that can withstand use at room temperature for a long time can be obtained. By previously setting the viscosity of the embedding resin to be lower than a predetermined value, the embedding property and the like can be improved. By using a type of acid anhydride curing agent having a viscosity lower than a predetermined value, it is possible to easily reduce the viscosity.

[Brief description of drawings]

FIG. 1 shows a wiring board using the embedded resin of the present invention as a BG.
It is explanatory drawing which shows the example applied to the A board.

FIG. 2 is an explanatory view showing one aspect of a method for manufacturing a wiring board using the embedded resin of the present invention.

FIG. 3 is an explanatory diagram showing one embodiment of a method of manufacturing a wiring board using the embedded resin of the present invention.

FIG. 4 is an explanatory view showing one embodiment of a method of manufacturing a wiring board using the embedded resin of the present invention.

FIG. 5 is an explanatory view showing one embodiment of a method for manufacturing a wiring board using the embedded resin of the present invention.

FIG. 6 is an explanatory view showing one embodiment of a method for manufacturing a wiring board using the embedded resin of the present invention.

FIG. 7 is an explanatory view showing one aspect of a method for manufacturing a wiring board using the embedded resin of the present invention.

FIG. 8 is an explanatory view showing one embodiment of a method for manufacturing a wiring board using the embedded resin of the present invention.

FIG. 9 is an explanatory view showing one embodiment of a method for manufacturing a wiring board using the embedded resin of the present invention.

FIG. 10 is a wiring board B using the embedded resin of the present invention.
It is an explanatory view showing an example applied to a GA substrate.

FIG. 11 is an explanatory diagram of a semiconductor device using an FC-PGA type multilayer printed wiring board according to one embodiment of the present invention.

FIG. 12 is a schematic view of a copper-clad core substrate having a thickness of 400 μm.

FIG. 13 is an explanatory diagram showing a state after patterning of a copper-clad core substrate having a thickness of 400 μm.

FIG. 14 is an explanatory diagram showing a state where via holes and through holes are formed in a substrate in which insulating layers are formed on both surfaces of a core substrate.

FIG. 15 is an explanatory diagram showing a state after panel plating is applied to a substrate in which insulating layers are formed on both surfaces of a core substrate.

FIG. 16 is an explanatory diagram of a substrate in which through holes are filled up.

FIG. 17 is an explanatory view showing a substrate having a through hole punched out.

FIG. 18 is an explanatory diagram showing a state in which a masking tape is attached to one surface of a substrate having a through hole punched out.

FIG. 19 is an explanatory view showing a state in which the multilayer chip capacitor is arranged on the masking tape exposed in the through hole.

FIG. 20 is an explanatory view showing a state in which a through hole is filled with an embedded resin.

FIG. 21 is an explanatory view showing a state where the substrate surface is polished and flattened.

FIG. 22 is an explanatory view showing a state where the polished surface of the substrate is subjected to panel plating.

FIG. 23 is an explanatory diagram showing a state in which wiring is patterned.

FIG. 24 is an explanatory diagram showing a state in which a buildup layer and a solder resist layer are formed on a substrate.

FIG. 25 is an explanatory diagram of an FC-PGA type multilayer printed wiring board that is one embodiment of the present invention.

[Explanation of symbols]

1 core substrate 2 Through hole (opening) 3 back tape 4 electronic components Electrode of 5 electronic parts 6 Embedded resin 60 flattened surface 61 roughened surface

Continued front page    (72) Inventor Kazushige Obayashi             14-18 Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture             Inside this special ceramics company (72) Inventor Toshito Kajima             14-18 Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture             Inside this special ceramics company F term (reference) 4J036 AA01 DA04 DB15 DC41 FA05                       FA13 HA12 HA13 JA07 JA08                       JA10                 5E314 AA25 FF05 FF19 FF21 GG01                       GG14 GG24                 5E346 AA60 CC09 CC32 DD12 EE09                       FF18 FF45 GG15 HH31

Claims (6)

[Claims] 1. An embedded resin containing a thermosetting resin, an acid anhydride curing agent, a curing accelerator and a filler at 25 ° C.
The viscosity after standing for 24 hours at ± 1 ° C is 8.4 at shear rate.
An embedding resin characterized in that it can be maintained at 85 Pa · s or less at s- ¹ . 2. The acid anhydride curing agent as 25 ° C. ± 1
The embedding resin according to claim 1, wherein a curing agent having a viscosity at 170C of 170 mPa · s or less is used. 3. The blending ratio of the filler is 51% by mass to
It is 74 mass%, The embedded resin of Claim 1 or Claim 2 characterized by the above-mentioned. 4. The embedded resin according to claim 1, wherein the filler contains at least one kind of inorganic filler. 5. A wiring board characterized in that an electronic component arranged in an opening provided in an insulating substrate is embedded using the embedding resin according to any one of claims 1 to 4. 6. A buildup layer in which insulating layers and wiring layers are alternately laminated is formed on at least one surface of a core substrate, and an opening is formed so as to penetrate at least one of the core substrate and the buildup layer. An electronic component that uses a substrate and that is arranged in the opening is provided.
A wiring board, wherein the wiring board is embedded using the embedding resin described in any one of 1.