JP2003143556A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device which has scanning line noise improved in a moving picture and has flicker improved in a still picture and has moving picture blur improved by increasing the response speed of a liquid crystal or improving the luminance and avoids an after-image (burning) phenomenon accompanied with application of a DC voltage to a liquid crystal panel. SOLUTION: Two frame memories and three line memories are used for an interlaced video signal input to read out data of three consecutive fields at the same timing, and movement detection is performed by intra-field data, and the detection result is used to perform interlace/non-interlace conversion processing and overdrive processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an interlace type video signal, and a liquid crystal display device,
For display devices that use EL elements, plasma, etc., the number of frame memories is reduced to improve interlace-to-non-interlace conversion processing and overdrive control to improve moving image quality, and to apply a steady DC voltage. The present invention relates to a display device that suppresses the above phenomenon and obtains a good display without an afterimage (burn-in).

[0002]

2. Description of the Related Art Conventionally, as a method of converting the format of an interlaced moving image from a video signal generator into a non-interlaced moving image, for example, Japanese Patent Laid-Open No. 2000-
As disclosed in Japanese Patent No. 152246, an inter-image interpolation signal formed from an image signal of a frame or field different from the interpolation target, and an intra-image interpolation signal formed from an image signal of the same frame or field as the interpolation target In the adaptive processing control device for moving image signals that mixes by changing the mixing ratio according to the motion coefficient, inter-image difference signal means for obtaining a difference between frames or fields of the input image signal as an inter-image difference signal, An activity detecting means for obtaining a difference between scanning lines in a frame or field of an input video signal as a spatial activity, and a normalization for converting a normalized signal by limiting a lower limit at a predetermined value when the spatial activity is a predetermined value or less. A signal forming means and a normalization for obtaining a normalized motion coefficient k by dividing the inter-image difference signal by this normalized signal. Means having a means is known.

FIG. 28 shows a non-interlaced moving picture image disclosed in the above Japanese Patent Publication No. 2000-152246.
It is a schematic block diagram of the scanning line interpolation apparatus which carries out format conversion to the interlaced format moving image. In the figure, 2801 is an image input terminal, 2802 is a field delay device 1, 2803 is a line delay device,
2804 is an adder 1, 2805 is a multiplier 1, 2806 is an adder 2, 28
Reference numeral 07 is an interpolation image output terminal, 2808 is an adaptive control unit, 2809 is a subtractor, 2810 is an adder 3, 2811 is a multiplier 2, and 2812 is a field delay unit 2.

The adaptive controller 2808 outputs the motion coefficient k,
This changes the mixture ratio of the inter-field interpolation and the intra-field interpolation. The interlaced moving image signal input from the image input 2801 is delayed by one field for a predetermined line by the field delay unit 1 2802, and as an upper line image signal, a line delay unit 2803, an adder 1 2804, and an adaptive control unit 28.
Given to 08. Here, the predetermined number of lines is set depending on the vertical area of the motion compensation process, and is about 4 lines.
The line delay unit 2803 delays the upper line signal by one line and supplies it as a lower line image signal to the adder 1 2804 and the adaptive control unit 2808. Field delay device 1 2802
From, a predetermined number of lines ± Y lines and
Pixels delayed by ± X pixels are given to the adder 3 2810 and the adaptive control unit 2808 as a post-field image signal. From the field delay unit 2 2812, the pixels delayed by a predetermined number of lines ± Y lines and ± X pixels by motion compensation are added as a previous field image signal by an adder 3 2810.
To the adaptive control unit 2808. Where ± Y, ± X
Is a motion-compensated motion vector, and the field delay unit 1 280
In 1 and the field delay unit 2 2812, the relationship of the interpolation time is reversed, so that the positive / negative of the delay amount is also reversed. The adder 1 2804 adds the upper line image signal and the lower line image signal to obtain 1 /
It is multiplied by 2 and the multiplier 1 2805 is used as the inter-field interpolation signal.
To the adaptive control unit 2808. Adder 3 2810 adds the previous field image signal and the following field image signal to 1 /
It is multiplied by 2 and is multiplied by the multiplier 2 2811 as an inter-field interpolation signal.
To the adaptive control unit 2808. The multiplier 1 2805 multiplies the motion coefficient k (0 to 1) given from the adaptive controller 2808 and gives it to the adder 2 2806. Multiplier 2 2811 is subtractor 2
The inverse motion coefficient (1-k) given from 809 is multiplied and given to the adder 2 2806. The adder 2 2806 calculates the intra-field interpolation signal multiplied by the motion coefficient k and the inverse motion coefficient (1-
k) and the inter-field interpolation signal multiplied by
The final interpolated signal is formed and output from the interpolated image output 2807.

[0005]

However, in the above-mentioned conventional technique, a delay of field data is required at two places, and when a general-purpose single-port memory is used as a memory device for realizing this, writing and reading are performed. Need to be performed by independent separate memory elements, and there is a problem that a large number of memories are required. Further, when this conventional technique is applied to a liquid crystal panel, the image quality improvement due to the interlace → non-interlace conversion process is taken into consideration, but the liquid crystal is a hold type device and the response speed is slow. No consideration is given to image quality improvement such as video blurring.

It is an object of the present invention to detect a motion by the same field data of adjacent frames and to detect an intra-field corresponding to a detection result when converting an interlaced input video signal into a non-interlaced format in a liquid crystal display device. This is to realize the interpolation processing or the inter-field interpolation processing with a small number of frame memories.

Another object of the present invention is to mount an overdrive process for speeding up the response speed of liquid crystal in addition to the interlace → non-interlace conversion process adapted to motion.
An object of the present invention is to provide a moving image compatible liquid crystal display control device with high image quality at low cost by extracting motion information of a video signal necessary for both of these processes by a common memory.

[0008]

In the present application, the outline of the representative one of the disclosed inventions will be briefly described as follows.

That is, according to the present invention, in a liquid crystal display device, a continuous interlace type video signal is written for each one screen of an even field and an odd field, that is, a first frame memory for writing one frame, and one frame at this timing. A second frame memory for alternately reading the previous video signal, that is, the even field and the odd field data of one frame before is independently provided. Furthermore the first
The field data being written in the frame memory are simultaneously written in another line memory and read at double speed during the latter half of the next line. Also here, the first and second line memories for two lines, which are independent for writing and reading, are provided. A second storing the video signal of the preceding frame
When reading from the frame memory, if the field currently being written is an even field, odd field data is first read at twice the speed at the time of writing, and the read data is written to another third line memory. At the same time, in the next line, the third line memory is also read at double speed, and at the same time, the even field data of one frame before is read at double speed. As a result, it is possible to temporally align the current even field data at the same position, the one-frame previous even field data, and the odd field data, and the motion detection is performed by comparing each even field data with the odd field screen as a master. By performing the inter-field or inter-field interlace → non-interlace conversion processing (hereinafter referred to as IP conversion processing) according to the result, a good display state in which scanning line noise and flicker are suppressed (Also, in the next frame, the relationships of even numbers and odd numbers are all reversed).

Further, the overdrive processing is performed by using the motion detection result of the same field between frames obtained by comparing the current even (odd) field data at the same position and the even (odd) field data one frame before. By doing so, the blur of the moving image for the liquid crystal having a slow response speed is improved.

Further, the display data obtained by the IP conversion processing and the overdrive processing is a constant DC voltage for a liquid crystal panel that needs to drive an interlaced video signal in a non-interlaced format. It is possible to suppress the application and prevent the afterimage (image sticking).

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an overall schematic configuration diagram of a liquid crystal display system using an image processing control method according to the present invention.
An input video signal is a main part of the technique of the present invention.
A video processing circuit 103 provided to obtain a good display before outputting 101 to the liquid crystal module 105.

In FIG. 1, 101 is a personal computer (hereinafter, P
C), television broadcasting (hereinafter referred to as TV), video tape recorder (hereinafter referred to as VTR), and the like, 102 is a liquid crystal display device for displaying the input video signal 101, Reference numeral 103 denotes a video processing circuit that takes in the input video signal 101 and performs video format conversion, image quality adjustment such as contrast and brightness, analog-digital conversion, color number conversion, and display size conversion, and 104 is the video processing circuit 103. A digital video signal that has been subjected to various kinds of processing by 105, a liquid crystal module 105 to which the digital video signal is input, 106 a driver control circuit unit included in the liquid crystal module 105 for generating display timing, 107 a driver control circuit The gate driver control signal output from 106, 108 the same data driver control signal, and 109 the gate driver control signal. Gate drivers that operate over control signal 107 as input, 110
Similarly, a data driver operating with the data driver control signal 108 as an input, and 111 a liquid crystal panel, respectively.

The overall operation of the first embodiment of the present invention will be described below with reference to FIG.

First, an input video signal 101 from a PC, TV, VTR or the like is input to a video processing circuit section inside a liquid crystal display device 102.
Capture to 103. Here, the present invention is intended to improve image quality when converting an interlace type video signal as an input video signal into a non-interlace type video signal which is a liquid crystal driving method. signal
The description of 101 is limited to the interlace format and will be described below. The image processing circuit unit 103 performs image processing such as interlace → non-interlace conversion for realizing the object of the present invention and data correction for improving the liquid crystal response speed on the input image signal 101 that has been taken in. The image-processed digital video signal 104 is input to the driver control circuit 106 inside the liquid crystal module 105, and the gate driver
109 and the data driver 110 is converted to a timing required and a control signal is generated and output. As a result, the liquid crystal panel 111 drives the interlaced format video signal input by sequential scanning, and further performs the video data correction processing that improves the blurring of the moving image display on the liquid crystal due to the slow response speed by the video data before and after the frame. To do.

FIG. 2 shows a schematic diagram of video transfer of interlace format and non-interlace format video signals.

In FIG. 2, the interlace format video signal of (a) transfers odd line and even line video data at different timings (interlaced scanning). As shown in the figure, in the first field, only the data of 1, 3, 5 ... Lines and odd lines are transferred, and in the second field only the data of 2, 4, 6 ... Lines and even lines are transferred. Forward. Then again in the third field 1, 3, 5
.... Transfer only the data of lines and odd lines, and repeat this process. Here, each field period is generally around 60 Hz. In the non-interlace format video signal of (b), odd line and even line video data are alternately transferred in each frame (sequential scanning). Even in the non-interless format, each frame period is generally 60H.
Since it is around z, therefore, twice as much data is transferred as compared with the interlaced format video signal.

Next, the image quality when displaying a moving image of an interlaced video signal will be described.

FIG. 3 is a schematic diagram showing display image quality deterioration (scan line noise occurrence) when interlaced moving images are displayed in the order of input (interpolation between fields). In FIG. 3, each video data of the first screen and the second screen is video data in which odd line data and even line data are combined,
It is assumed that there is a movement (moving image) of video data between the first screen and the second screen. When this video signal is input in interlace format, the display output order is odd 1 field →
Even number 1 → odd number 2 → even number 2 ... Here, when these interlace format video signals are sequentially combined and displayed, the liquid crystal needs to be driven by sequential scanning, and therefore even number 1
Video data such as field + odd 2 fields will be displayed. In this case, the video signal display is shifted for each line, and this is recognized as scanning line noise.

Next, the display image quality when displaying a still image of an interlace format video signal will be described.

FIG. 4 shows deterioration of display image quality when interlaced still images are interpolated (flicker occurs).
A schematic diagram is shown. In FIG. 4, the original image is transferred while being divided into an odd line and an even line. Inter-field interpolation is performed on each interless video signal by interpolating line data (even line data for odd fields, odd line data for even fields) by interpolating upper and lower line data. This makes it possible to display on the liquid crystal only with each field data, but when attention is paid to a specific pixel, the video data (gradation data) differs for each frame, so this is recognized as flicker in a still image. become. Furthermore, when the dot inversion frame alternating current in which the polarity is inverted every frame is used as the alternating current method, the voltage applied to the liquid crystal is biased, and an afterimage (burn-in) occurs due to the steady application of the DC voltage. .

That is, for interlaced video signals, if inter-field interpolation is applied to a moving image, scanning line noise occurs, and if inter-field interpolation is applied to a still image, flicker and , Afterimage (burn-in)
Occurs. Therefore, a motion adaptive three-dimensional IP conversion process that combines these two interpolation methods according to the motion of the video signal is required.

FIG. 5 shows a schematic block diagram of the motion adaptive three-dimensional IP conversion processing.

FIG. 5 shows the case where the conversion process is performed by using the odd field of the (N + 1) frame as the master.
First, the first line of the display data outputs the first line data 1 (2) of the odd field of the (N + 1) frame.
Next, the second line of the display data compares the (N) frame even field data with the (N + 1) frame even field data (motion detection). As a result, the difference is less than or equal to a predetermined value, so it is determined to be a still image. Then, the first line data 2 (2) of the (N + 1) th frame even field is output to suppress the occurrence of flicker and afterimage (burn-in). Next, the third line of the display data is the same as the first line,
The second line data 3 (2) of the odd field of the (N + 1) frame is output. Further, similarly to the second line, the fourth line of display data compares the (N) frame even field data with the (N + 1) frame even field data (motion detection), and as a result, the difference is a predetermined value or more. Therefore, it is determined to be a moving image, and the interpolation data generated from the upper and lower line data 3 (2) and 5 (2) in the odd field of the (N + 1) frame is output, and the generation of scanning line noise is suppressed. The same process is repeated thereafter to generate display data.

The prior art shown in FIG. 30 requires an independent frame memory for four frames and a line memory for four lines to realize this, and has a problem in terms of cost.

A first embodiment according to the present invention for solving this problem will be described below. FIG. 6 shows a schematic configuration diagram for the first embodiment.

In FIG. 6, 101, 103 and 104 are the same as those in FIG.
The input video signal, the video processing circuit, and the digital video signal are shown in the overall schematic configuration diagram of the liquid crystal display system shown in FIG. Inside the video processing circuit 103, 601 is a frame memory 1, 602 is a frame memory 2, 603 is a line memory 1, 604 is a line memory 2, and 605 is the frame memory 1 601 and read data switching from the frame memory 2 602. Reference numeral 606 denotes a line memory 3, 607 denotes a line memory 1 603, line memory 2 604 and a read data switching circuit 605. An arithmetic processing control unit that performs an interless → non-interlace conversion process based on data input from the line memory 1 603, the line memory 2604, the line memory 3 606, and the motion detection control unit 607 is shown.

FIG. 7 shows the internal state of each frame memory when the current input video data is an even field in FIG. 6, and FIG. 8 shows an operation timing chart.

In FIGS. 6, 7 and 8, first, the first line (NE-L1) of the current input video data of the even field is written in the frame memory 2 602 and simultaneously in the line memory 1 603. In the next line, the frame memory 2 6
In 02, the second line of the current input video data (NE-L2) is written, and at the same time, it is also written in the line memory 2 604. On the other hand, in this line, the first line (OO-L1) of the odd field video data of the odd field and even field video data one frame before which is already stored in the frame memory 1 601 is doubled at the time of writing. Read in the first half,
The line memory 3 is output at the same time when the image is output as output data.
Write to 606. In the latter half of the line, the frame memory 1
1 of even field video data one frame before 601
The second line (OE-L1), the video data one line before from the line memory 1 603 (NE-L1) and the video data (OO-L1) written in the first half of the line from the line memory 3 606 are both 2
Read at double speed. Of these three types of video data that were read at the same time, the data (OE-
L1) and the data (NE-L1) from the line memory 1603 are pixel data at the same position before and after one frame, and the motion can be detected by comparing them. In the example of the timing diagram shown in FIG. 8, this comparison result is below the threshold,
It is determined that the video data is a still image, and the read data (NE-L1) from the line memory 1603 is output as the video data of the second line of display (inter-field interpolation). Similarly, the current input video data is written at a double speed for one horizontal period and the first half of the line outputs the odd line data (OO-L *) read from the frame memory 1601 as output data in the first half of the line. In the latter half of the line, even line data (OE-L *) one frame before read from the frame memory 1 601 and even line data of the current frame (NE-L *) read from the line memory 1 603 or line memory 2 604 (NE -L *) compare. If this comparison result exceeds the threshold value, it is determined to be a moving image, and if it does not exceed the threshold value, it is determined to be a still image. When it is determined to be a moving image, the data (OO-L2) read from the line memory 3606 is displayed and output as output data (in-field interpolation), as shown in the fourth line of output data in FIG. That is, when the inter-frame comparison is performed and it is determined that there is motion, the same data as that of one line before is output, so that the intra-field interpolation processing is line doubler control.

9 and 10 show a frame memory 1 601 and a frame memory 2 6 for the next frame in FIG.
An internal state of 02 and an operation timing chart are shown.

In FIGS. 9 and 10, the current input video signal 101 is odd field data, and this data is continuously written in the frame memory 2602. In reading from the frame memory 1601, video data of one frame before is read in the opposite relationship to the case where the current input video signal shown in FIG. 7 is even field data. That is, in FIG. 7 and FIG. 8, the data read from the frame memory 1 601 is used as the line memory 3 606 and the arithmetic processing control unit 6.
Control of whether to output to 08 or to the motion detection control unit 607 is performed by the switching circuit 605 shown in FIG. 6, and this switching control is performed in accordance with the vertical synchronizing signal which is a part of the video input 101.

As described above, according to the first embodiment of the present invention shown in FIGS. 6 to 10, the frame memory is independently used for two frames and the line memory is independently used for three lines.
For interlaced video signals, interlace → non-interlace conversion processing that matches the motion state can be realized, and scanning line noise that becomes a problem when moving images, flicker that becomes a problem when still images, and afterimage ( (Burn-in) can be avoided. However, the line doubler processing, which is an intra-field interpolation when it is determined to be a moving image, has a problem in image quality.

FIG. 11 shows a schematic diagram of interpolation processing by the line doubler method.

In FIG. 11, in the line doubler method, the same line data is repeatedly displayed to realize the interlace → non-interlace conversion process, so that the display of the edge portion becomes stepwise and the whole display becomes rough. Give the impression of

A second embodiment according to the present invention which solves this problem will be described below.

FIG. 12 shows a block diagram of the second embodiment of the present invention. In contrast to the first embodiment of the present invention shown in FIG. 7, a portion for storing read data from the line memory 1 603, the line memory 2 604, and the line memory 3 606 in the line memory again, and the frame memory 1/2 601. , 602 and data to be input to the motion detection unit 607 are temporarily stored in the line memory.

In FIG. 12, 1201 is a line memory 4 for storing the data read from the line memory 3 606, 1202 is a line memory 5 for storing the data read from the line memory 1 603, and 1203 is a line memory 2 604. Line memory 6 for storing the data read from
Also, 1204 is the frame memory 1 601 which is reading
Alternatively, each of the line memories 7 temporarily stores the data read from the frame memory 2 602 and input to the motion detection control unit 607.

FIG. 13 shows an operation timing chart of the configuration diagram of the second embodiment of the present invention shown in FIG.

12 and 13, first, the first line (NE-L1) of the current input video data of the even field is written in the frame memory 2 602 and simultaneously in the line memory 1 603. In the next line, the frame memory 2 602
, The second line of the current input video data (NE-L2) is simultaneously written to the line memory 2 604. On the other hand, in this line, 1 already stored in the frame memory 1 601
Of the odd field video data and the even field video data before the frame, the first line (OO-L1) of the odd field video data is read in the first half of the line at double speed at the time of writing,
At the same time, write to line memory 3 606. In the latter half of the line, the first line (OE-L1) of the even field video data one frame before from the frame memory 1 601 and the video data (NE-L1) one line before from the line memory 1 603 and the line memory 3 606 Video data written in the first half of the line
(OO-L1) is read at double speed. At the same time, the first line (OE-L1) of the even field video data read from the frame memory 1 601 is stored in the line memory 7 1204 and the video data of one line before (N) read from the line memory 1 603 (N
E-L1) is the line memory 5 1202, and the video data (OO-L1) read from the line memory 3 606 is the line memory 4 1201.
Write in each. Of these three types of video data read simultaneously, the data (OO-L1) read from the line memory 3 606 is directly output as video as output data. The output line 2 is the line memory 7 1204 data (OE-L1) written in the output line 1 and the line memory 5 1.
The 202 data (NE-L1) is read and compared. Here, since it is determined that there is no motion, the line memory 5 1202 read data (NE-L1) is output as output second line data (inter-field interpolation). The output for the third output line
Read data from line memory 3 606 as in the first line
Output (OO-L2) directly. For the 4th output line,
Read data from the line memory 7 1204 (OE-L2)
Read data from the line memory 6 1203 (NE-L
2) was compared and it was determined that there was motion here, so frame memory 1 601 read data (OO-L3), which is the upper and lower line data in the master field (Old_ODD), and line memory 4 1201 read data (OO-L2). ) And are output (interpolation within the field). Here, the intra-field interpolation processing when it is determined that there is motion is performed by the line doubler in the first embodiment of the present invention, whereas in the second embodiment of the present invention, the upper and lower line data in the master field is used. Since the interpolation is performed by the calculation processing according to, it is possible to avoid the roughness of the entire display due to the edge portion stepwise display in the line doubler method as shown in FIG.

14 and 15 show the internal state of the frame memory in the block diagram in the next frame of FIGS. 12 and 13 and the operation timing chart thereof.

As in the first embodiment of the present invention, in FIGS. 14 and 15, the current input video signal 101 is odd field data, and this data is the frame memory 2 602.
Continue to write. In reading from the frame memory 1601, the video data of one frame before is read in the opposite relationship to the case where the current input video signal shown in FIG. 12 is even field data.

As described above, according to the second embodiment of the present invention, it is determined that there is motion as a result of motion detection by additionally providing a line memory for four lines in addition to the first embodiment of the present invention. In the intra-field interpolation processing by the master field at this time, the interpolation can be performed by the arithmetic processing using the upper and lower line data, so that the image quality can be improved.

Next, as a third embodiment of the present invention, in addition to the interlace → non-interlace conversion processing according to the first and second embodiments, there is a problem in displaying a moving image in the liquid crystal module. A method of avoiding the display blur phenomenon due to the slow response speed of the liquid crystal will be described.

Here, as a measure for improving the response speed, an output overdrive control method is used in which a correction value corresponding to the amount of data change between adjacent frames is added to the original display data.
FIG. 16 shows a schematic diagram of a response speed improvement measure by overdrive control.

In FIG. 16, an overdrive correction value obtained from the relationship between the gradation data before and after the change is added to the specific pixel in order to obtain the desired brightness value after the change in the next frame from the brightness value before the change. It is an example of a change in luminance in the case. Without correction by the overdrive control, the response speed of the liquid crystal greatly exceeds one frame period (60 Hz → 16.7 ms), and thus it takes a plurality of frame periods to reach the target luminance after the change. This transient period and the lack of effective luminance due to the blunting of the waveform are recognized as a blur of the moving image. In order to improve this, the arrival time to the target brightness after change is shortened by adding the correction data to the output data according to the data value between adjacent frames (speed-oriented correction → FIG. 16A), or Correct the rms value (correction with emphasis on brightness → Fig. 16)
(B))

FIG. 17 is a schematic block diagram showing the structure of the interlace-to-non-interlace conversion processing unit shown in the first embodiment of the present invention when an overdrive processing circuit for improving moving image blur is installed. .

In FIG. 17, reference numeral 1701 indicates the entire overdrive processing circuit, 1702 indicates the frame memory 3, 1703 indicates the frame memory 4, and 1704 indicates the correction processing control unit.

The non-interlace format video signal 104 output from the IP conversion processing circuit unit 103 is written into the frame memory 3 1702 or the frame memory 4 1703 in the overdrive processing circuit 1701 and at the same time correction processing is performed. Also input to the control unit 1704. Here, regarding the relationship between the frame memory 3 1702 and the frame memory 4 1703, it is assumed that writing and reading conflict with each other in frame synchronization. Therefore, the data (1st_Data) read from the frame memory 3 1702 or the frame memory 4 1703 is the I-
Read from the P conversion processing circuit unit 103, and the correction processing control unit 1
The data (2nd_Data) input to 704 is always one frame before. Therefore, it becomes possible to obtain the gradation data before and after the change shown in FIG. 16 from these two data, and the correction processing control unit 1704 can determine the optimum correction value for the output data.

However, in the configuration of FIG. 17, it is necessary to provide a frame memory for two frames in each of the IP conversion processing circuit section 103 in the front stage and the overdrive processing circuit 1701 in the rear stage, which is a problem in terms of cost. Become. The third embodiment of the present invention which solves this problem realizes interlace-> noninterlace conversion processing and overdrive processing while integrating the frame memories existing at these two locations.

FIG. 18 is a schematic diagram showing the memory operation inside the IP conversion processing circuit section 103 of the previous stage in the configuration diagram shown in FIG.

In FIG. 18, 1 is used to detect the motion.
The same field data before and after the frame is compared. Figure 1
In the example of FIG. 8, (N) frame even field data by the frame memory 1 601 is compared with (N + 1) frame even field data by the line memory 1 603 and the line memory 2 604. That is, by using this comparison result as a substitute for the comparison result of 1st_Data and 2nd_Data of the overdrive processing circuit in the subsequent stage, the frame memory 3 1702 and the frame memory 4 1703 are reduced.

FIG. 19 shows a block diagram of a control circuit for performing the IP conversion processing and the overdrive processing when the frame memory 3 1702 and the frame memory 4 1703 are omitted.

In FIG. 19, reference numeral 1901 denotes a data processing section for inputting comparison data between adjacent frames and performing IP conversion processing and overdrive processing. 1902 denotes the motion detection control section 607 in the overdrive processing. A correction value calculation unit for calculating a correction value for output data using the comparison result from 1), 1903 is a non-interlaced video signal output from the IP conversion processing circuit 608, and the correction value calculation unit
The overdrive correction data generation unit that inputs the correction value output from the 1902 and outputs the video signal that has been overdriven is shown.

The detection result from the motion detection control unit 607 is the same as that in the case of FIG. 6, and this detection result is also input to the IP conversion processing circuit 608 and the correction value calculation unit 1902.

FIG. 20 shows an operation flowchart for the third embodiment of the present invention shown in FIG.

This flowchart shows the processing for one pixel from the start to the end, and this flow is repeated for each pixel.

First, the same field data of adjacent frames are compared by the motion detection process. In this same inter-field data, odd and even lines alternate every frame. Next, the detection data obtained by the motion detection process is compared with a threshold serving as a reference for motion determination, and the presence or absence of motion between frames is determined. Here, since the detected data is a difference between inter-frame data, if this difference is smaller than a threshold value, it is determined that there is no motion, and the IP conversion processing unit performs inter-field interpolation processing and ends the processing for one pixel. On the contrary, if the difference between the data between frames is larger than the threshold value, it is determined that there is motion,
The I-P conversion processing unit performs in-field processing to generate a non-interlaced video signal. This video signal is output to the overdrive processing unit, overdrive correction value calculation processing corresponding to the difference between the inter-frame data, and video data in which this correction data is added are generated, output as display data, and processed for one pixel. To finish.

FIG. 21 is a schematic diagram showing the operation of the third embodiment of the present invention. FIG. 21 shows an example in which the odd field of the (N + 1) frame is used as the master field.

First, the first line of the data after IP conversion becomes the first line 1 (2) of the odd field of the (N + 1) frame which is the master field. The data of this line is not subjected to overdrive processing because there is no data compared between frames and is output as it is as display data. Next, the second line of the I-P converted data is the first line 2 (1) of the (N) frame even field data,
First line of (N + 1) frame even field data
Since 2 (2) was compared and it was determined that there was no movement in this example,
First line of (N + 1) frame even field data
2 (2) is output as the second line data after IP conversion (inter-field interpolation). Furthermore, since it is determined that there is no movement, correction processing by overdrive is not necessary, and (N
+1) Frame 1st line of even field data 2
Output (2) as it is as display data. Next display 3
As the first line, the second line 3 (2) of the odd field of the (N + 1) th frame is output as in the first line. Then I-
The fourth line of the P-converted data is compared with the second line 4 (1) of the (N) frame even field data and the second line 4 (2) of the (N + 1) frame even field data. Since it is determined that there is the data, the second line 3 (2) of the (N + 1) frame odd field data is set to IP
Output as the converted fourth line data (in-field interpolation by line doubler). Further, since it is determined that there is movement, the overdrive processing unit obtains the correction value α based on this movement amount, and the data 3 (2) + α in which the correction value α is added is output as display data. Thereafter, by performing the same processing, it is possible to share the motion detection unit and realize the IP conversion processing and the overdrive processing for even lines of the display data.

FIG. 22 is a schematic diagram of the operation when the (N + 1) th frame odd field is the master field and the (N + 1) th even field shown in FIG. 21 is the master field. The basic operation is similar to the case where the odd field of (N + 1) frame shown in FIG. 21 is used as the master field, and the comparison target is the odd field data of (N + 1) frame and the odd field data of (N + 2) frame. . Regarding display data, overdrive processing can be realized for odd lines.

That is, from FIG. 21 and FIG.
The overdrive processing for display data is performed by alternating odd lines and even lines for each frame.

FIG. 23 is an example of an overdrive control method algorithm according to the present invention.

In FIG. 23, the corrected output display data is obtained from the input video data ND of the current frame and the input video data OD of the previous frame by the following relational expression.

Output display data = ND + α × (ND-OD) That is, the difference between adjacent frame image data (ND-O
D) is multiplied by the correction value α, and the input video data ND of the current frame is added to obtain the value. The α value at this time greatly affects the performance. In FIG. 23, the response characteristics of the liquid crystal differ depending on α = a to d, a is a state in which the correction value is almost zero, b is a state in which speed is important, c is a state in which luminance is compensated, and d is a luminance in comparison with c Is a characteristic in the state of emphasizing. The calculation method of α is obtained by observing the response waveform by combining the input video data ND of the current frame and the matrix of the input video data OD of the previous frame and each gradation data. Further, since the liquid crystal has different rising characteristics from low gradation to high gradation and falling characteristics from high gradation to low gradation, as shown in the matrix table of FIG. 23, the input video data ND of the current frame, Two kinds of correction values α are obtained for rising and falling, with Sakai at a point where the input video data OD one frame before is equal.

When the luminance is overemphasized like the characteristic of α = d in FIG. 23, the contrast is emphasized,
Although the image state is sharp, there is a problem caused by the γ characteristic of the liquid crystal panel.

FIG. 24 shows an example of the liquid crystal panel γ characteristic.

FIG. 24 shows an example in which the γ characteristic 1 (upwardly convex) has a characteristic that the luminance gradient in the input low gradation portion is large and the luminance gradient in the input high gradation portion is small. γ characteristic 2 (downwardly convex)
Shows an example in which the luminance gradient in the input low gradation portion is small and the luminance gradient in the input high gradation portion is large. Therefore, when the correction amount of the input gradation is x, γ is obtained in the low input gradation portion.
The luminance difference between the characteristic 1 (upwardly convex) and the γ characteristic 2 (downwardly convex) is b to a, and even with the same correction amount x, the γ characteristic 1 (upwardly convex) has a larger luminance change amount. On the other hand, the luminance difference between the γ characteristic 1 (upwardly convex) and the γ characteristic 2 (downwardly convex) in the input high gradation portion is d: c.
Even with the same correction amount x, the luminance variation amount is larger in the γ characteristic 2 (downwardly convex). Therefore, in FIG.
= If the brightness is overemphasized like the d characteristic, the γ characteristic 1
In (upward convex), by overcorrecting in the low gradation part,
A large amount of change in luminance causes color misregistration. However, since the relative brightness is low, the color shift phenomenon is not subjectively recognized. On the contrary, in the γ characteristic 2 (convex downward), the color shift occurs due to the large amount of change in luminance due to excessive correction in the high gradation portion, and the color shift phenomenon is subjectively recognized due to the high relative luminance. Therefore, when the brightness is excessively emphasized and the contrast is emphasized to obtain a clear image as in the correction value α = d in FIGS. 23 and 24, in a region where the input gradation is high, By providing a limiting circuit that prohibits the correction process by overdrive, subjective color shift is prevented.

Next, in a third embodiment according to the present invention,
It will be described that the afterimage (image sticking) phenomenon due to the steady application of the DC voltage can be avoided.

FIG. 25 is a schematic timing chart showing a state in which a steady DC voltage that causes an afterimage (image sticking) on the liquid crystal panel is applied.

FIG. 25 shows a timing chart when attention is paid to a specific pixel. As an input video signal, black data (minimum gradation) and white data (maximum gradation) are repeated for each frame. Furthermore, since the alternating drive signal repeats positive and negative polarities for each frame, the voltage applied to the liquid crystal panel due to the superposition of the grayscale data described above is in a state in which a negative DC voltage is constantly applied. This causes the afterimage (image sticking). That is, this state occurs when a still image is displayed by using the line doubler method for the interless → non-interlace conversion shown in FIG. On the other hand, the third embodiment of the present invention shown in FIG.
In the embodiment, the afterimage (image sticking) phenomenon due to the steady application of the DC voltage can be avoided.

FIG. 26 is a schematic diagram showing the operation of the third embodiment of the present invention when an interless still image signal is input.

In FIG. 26, the odd field of the (N + 1) th frame is used as the master field, and the first line of the display data is the data of the first line of the master field.
Output 1 (2). The display second line data is (N) frame even field first line data 2 (1) and (N
+1) Frame even field 1st line data 2 (2)
However, since it is a still image, adjacent frame data in the same field match and it is determined that there is no motion. Therefore, the overdrive processing is not performed, and the (N + 1) frame even field first line data 2 (2) is output as the display data. Hereinafter, the same processing as the display first line and the display second line is repeated. That is, since the inter-field interpolation is performed without performing the overdrive processing, the operation shown in FIG. 3 is applied to the still image, and the afterimage (burn-in) phenomenon can be avoided.

FIG. 27 is a schematic diagram showing the operation of the next frame of FIG. In this case, the (N + 1) th frame even field becomes the master field, and the operation of generating the display data is the same as in the case of FIG.

Table 1 shows the number of frame memories required for the IP conversion processing and the overdrive processing for the present invention and the prior art. Here, it is assumed that processing is performed in two parallels in consideration of correspondence to a high-definition video signal, and regarding the number of colors, R-GB = 5-6-5 in consideration of the memory bus width.
And full-color compatible, R-G-B = 8-8-8, and a 64-Mbit product with sufficient capacity in terms of memory configuration and a data bus width of 16 bits and 3
Two types of 2 bits are assumed.

[0076]

[Table 1] In Table 1, the present invention is characterized in that the frame memory of the IP conversion processing unit and the overdrive processing unit are shared, and therefore, in the conventional technology, a maximum of six memory chips is required. The invention does not require it at all (the memory of the IP conversion processing unit is shared). Further, in the case of the total number of full color specifications, the present invention can reduce 12 memory chips by using a 16-bit product memory.

As described above, according to the liquid crystal display control method and the liquid crystal display device having the same according to the present invention, by using the two frame memories and the three line memories, the interlace type video signal is transmitted to the liquid crystal panel. It is possible to realize the motion adaptive three-dimensional interlace → non-interlace conversion process for displaying (Example 1).

Furthermore, by newly adding four line memories, in inter-field interpolation when it is judged as a moving image in motion detection, upper and lower line data are calculated instead of simple line doubler processing to generate interpolated line data. It is possible (Example 2).

Further, the motion detection result obtained by comparing the data between the same fields of the adjacent frames used in the interlace → non-interlace conversion process is diverted as the correction value calculation data of the overdrive processing unit provided in the subsequent stage. It is possible to reduce the number of required memories and realize cost reduction (third embodiment).

Further, in any of the embodiments, it is possible to prevent the steady application of the DC voltage to the liquid crystal panel due to the input of the still image video signal of the interlace type, and to realize the good display without the afterimage (burn-in). It is possible to

[0081]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the liquid crystal display control method of the present invention and the liquid crystal display device using the same, the interlace format video signal is converted into the non-interlace format video signal which is the driving mode of the liquid crystal panel. At this time, motion detection is performed by comparing the same field data between adjacent frames, and it is possible to suppress the number of mounted frame memories required to obtain good display by switching interfield interpolation processing and intrafield interpolation processing, The effect is that the cost can be significantly reduced.

Further, according to the liquid crystal display control method of the present invention and the liquid crystal display device using the same, the interlace
It is possible to compensate the response speed or brightness of the liquid crystal panel by using the motion detection result from the frame memory mounted for non-interlace conversion as the inter-frame motion detection data of the overdrive processing circuit provided in the subsequent stage. The effect of improving moving image blur can be obtained without increasing the cost of newly installing a frame memory.

Further, according to the liquid crystal display control method of the present invention and the liquid crystal display device using the same, the interlace → non-interlace conversion processing and the overdrive processing are controlled by using a common motion detection result. , When an interlaced video signal is input in a still image state, it is possible to obtain a good display state without an afterimage (burn-in) without applying a constant DC voltage to the liquid crystal panel. The effect is obtained.

[Brief description of drawings]

FIG. 1 is an overall schematic configuration diagram of a liquid crystal display system using the technique of the present invention.

FIG. 2 is a schematic diagram of video transfer of interlace format and non-interlace format video signals.

FIG. 3 is a schematic diagram of display image quality deterioration (scan line noise occurrence) when interlaced moving images are displayed in the input order (inter-field interpolation).

FIG. 4 is a schematic diagram of display image quality deterioration (flicker occurrence) when interlacing a still image of an interlaced format.

FIG. 5 is a schematic configuration diagram of motion adaptive three-dimensional IP conversion processing.

FIG. 6 is a schematic configuration diagram for a first embodiment according to the present invention.

FIG. 7 shows the internal state of each frame memory for the case where the current input video data is an even field according to the first embodiment of the present invention.

FIG. 8 shows the internal timing of each frame memory for the case where the current input video data is an even field for the first embodiment of the present invention.

FIG. 9 shows the internal state of each frame memory when the current input video data in the first embodiment of the present invention is an odd field.

FIG. 10 shows the internal timing of each frame memory when the current input video data for the first embodiment of the present invention is an odd field.

FIG. 11 is a schematic diagram of interpolation processing by the line doubler method.

FIG. 12 is a schematic configuration diagram of a second embodiment according to the present invention.

FIG. 13 is an operation timing chart of the configuration diagram of the second embodiment according to the present invention.

FIG. 14 shows the internal state of each frame memory for the case where the current input video data is an odd field for the second embodiment of the present invention.

FIG. 15 shows the internal timing of each frame memory for the case where the current input video data is an odd field for the second embodiment of the present invention.

FIG. 16 is a schematic diagram of a response speed improvement measure by overdrive control.

FIG. 17 is a schematic configuration diagram when an interdrive → non-interlace conversion processing unit configuration diagram according to the first embodiment of the present invention is provided with an overdrive processing circuit for improving moving image blur.

FIG. 18 is a schematic diagram showing an internal memory operation of the IP conversion processing circuit unit 103 in the preceding stage in FIG.

FIG. 19 is a schematic block diagram of a third embodiment according to the present invention.

FIG. 20 is an operation flowchart for the third embodiment according to the present invention.

FIG. 21 is an operation schematic diagram of the third embodiment according to the present invention.

22 is a schematic diagram of an operation when an (N + 1) th frame even field, which is the next frame of FIG. 21, is used as a master field.

FIG. 23 is an example of an overdrive control method algorithm according to a third embodiment of the present invention.

FIG. 24 is an example of a liquid crystal panel γ characteristic.

FIG. 25 is a schematic timing chart showing a state in which a steady DC voltage that causes an afterimage (image sticking) is applied.

FIG. 26 is a schematic view of the operation when an interlaced still image signal is input in the third embodiment of the present invention.

27 is a schematic view of the operation of the next frame in FIG. 26. FIG.

FIG. 28 is a schematic configuration diagram of interlace → non-interlace conversion processing according to a conventional technique.

[Explanation of symbols]

101 ... Input video signal, 102 ... Liquid crystal display device, 103 ... Video processing circuit, 104 ... Digital video signal, 105 ... Liquid crystal module, 106 ... Driver control circuit, 107 ... Gate driver control signal, 108 ... Data driver control signal , 109 ...
Gate driver, 110 ... Data driver, 111 ...
Liquid crystal panel 601, frame memory 1, 602 frame memory 2, 603 line memory 1, 604 line memory 2,
605 ... Read data switching circuit, 606 ... Line memory 3,
607 ... Motion detection section, 608 ... Arithmetic processing control section, 1201 ... Line memory 4, 1202 ... Line memory 5, 1203 ... Line memory 6, 1204 ... Line memory 7, 1701 ... Overdrive processing entire circuit, 1702 ... Frame memory 3 , 1703 ... Frame memory 4, 1704 ... Correction processing control unit, 1901 ... Overdrive data processing unit, 1902 ... Correction value calculation unit, 1903 ... Overdrive correction data generation unit, 2801-2804 ... Frame memory 1-Frame memory 4 , 2805 to 2808 ... Line memory 1 to line memory 4, 2809 ... Data comparison circuit, 2810 ...
Data operation circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 5/391 (72) Inventor Takashi Shoji 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi image information In-system (72) Inventor Tetsuo Takagi 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock company Hitachi Microsoftware Systems In-house (72) Inventor Toshiaki Ohashi 1-1-1 Higashitaga-cho, Hitachi-shi, Ibaraki Hitachi Digital Media Group (72) Inventor Tomohide Ohira 3300 Hayano, Mobara-shi, Chiba F-Term in Hitachi Display Group (reference) 5C006 AA16 AC24 AF01 AF23 AF42 AF44 AF83 BB11 BF02 BF05 FA44 5C063 BA04 BA10 BA12 CA01 CA05 CA07 5C080 AA10 BB05 DD22 EE26 FF09 GG08 JJ01 JJ02 JJ04 JJ05 5C082 AA0 2 BA12 BA35 BB15 BB25 BC06 BC07 BC19 DA53 DA59 DA61 MM04 MM10

Claims (12)

[Claims] 1. Two frame memories each capable of storing data for one frame (one field for each of odd number and even number) and three line memories capable of storing data for one line, the same field, Means for detecting motion information by comparing position pixel data, IP conversion processing means for performing interlace → non-interlace conversion according to the motion information, and display after IP conversion similarly according to the motion information. Correction value calculation means for correcting data,
A display device comprising an overdrive correction data generating means for generating correction data for outputting an image by using the correction value. 2. The display device according to claim 1, wherein video data of two consecutive fields are stored in the two frame memories, and two line memories are written simultaneously with the frame memory to write input video data. A display device characterized in that reading speed from the two frame memories, two line memories, writing to the remaining one line memory, and reading speed are twice as fast as speed. 3. The display device according to claim 1, wherein among the data of consecutive 3 fields to be read out at the same time, when comparing the same field and same position pixel data, if the difference is larger than a prescribed threshold value, input video data Is a moving device, and conversely, if it is smaller than a threshold value, the input image data is controlled to be stationary. 4. The display device according to claim 1, wherein as a result of the motion detection, when it is determined that the input video signal is a moving image, the reference field, that is, the data of the consecutive 3 fields read simultaneously, Interpolation processing is performed within a single field, line data to be interpolated is subjected to line doubler processing that repeats line data one line before, and when it is determined that the input video signal is a still image, the continuous three fields that are read simultaneously are read. A display device which outputs data of a new field of two fields having the same field among data as inter-field interpolation data. 5. The display device according to claim 1, wherein the video data after the interlace → non-interlace conversion is:
In the display device, only the odd lines and the even lines are alternately valid for each frame in the overdrive process for performing the data correction process using the result of the motion detection. 6. The display device according to claim 1, wherein the same three consecutive fields read from the memory,
Motion information detection using the same-position pixel data is used in the interlace → non-interlace processing section to judge the motion of the video depending on whether the difference between the two data is larger or smaller than a specified threshold value. A display device characterized by being used in a drive processing unit to obtain a correction value from data of a previous field according to a transition state of data of a current field. 7. The display device according to claim 1, wherein the image data correction value of the overdrive control unit takes into account the response speed characteristics of the panel, and a correction value and a response that reach the changed target luminance at the fastest speed. Compensate for lack of brightness due to waveform delay,
A display device characterized in that a correction value for reproducing the luminance characteristic of an original image can be arbitrarily set. 8. The display device according to claim 1, wherein a color misregistration preventing function when contrast is emphasized by performing excessive brightness compensation by the overdrive control is provided.
A display device which prohibits overdrive processing for a specific input gradation region. 9. The display device according to claim 8, wherein the specific input gradation region in which the overdrive processing is prohibited is subjectively recognizable, and the luminance change with respect to the overdrive unit correction value is large. Also, the display device is characterized in that the γ characteristic of the liquid crystal panel is downwardly convex and the original data before correction is a high gradation part. 10. The display device according to claim 1, wherein the liquid crystal panel is displayed regardless of whether the video signal subjected to the interlace → non-interlace conversion process and the overdrive process is a moving image or a still image. A display device characterized in that a constant DC voltage is not applied and an afterimage (image sticking) phenomenon can be avoided. 11. The display device according to claim 1, further comprising four line memories, so that inter-field interpolation processing when inter-motion → non-interlace conversion processing determines that there is motion is performed. A display device using data obtained by calculating upper and lower line data. 12. The display device according to claim 1, which can be realized only by mounting a minimum of two frame memory chips depending on the corresponding input video signal mode, the number of display colors, and the configuration of the frame memory to be used. A display device characterized by.