JP2003143120A - Data randomizing circuit and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data randomizing circuit where a processing cycle required only for transposition is not required when randomizing data by transposition and substitution. SOLUTION: The circuit for randomizing the data by transposition conversion and substitution conversion is provided with a data division means for dividing the data, a partial data substitution means for substitute-converting the data, a data combining means for combining the data, and a buffer memory for keeping data temporarily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit and method for agitating data by transposition conversion and transposition conversion. In particular,
The present invention relates to a data mixing circuit and method that does not require a processing cycle required only for transposition conversion.

[0002]

2. Description of the Related Art One of the purposes for mixing digital data represented by binary signals of 0 and 1 is data encryption. DES (Data) which is the current American standard encryption
Encryption Standards and
Technology) Next American standard encryption A
ES (Advanced Encryption St)
The Rijndael cipher, which is the final candidate of the (andard), is a block cipher with a data length of 16 bytes, and the cyclic conversion is a transposition conversion in which 16-byte data represented by a 4 × 4 byte matrix is byte-rotated in units of rows. , And substituting conversion on a column-by-column basis.

National Institute of Standards and Technology NIST (Na
regional Institute of Standard
rd) is the AES Federal Information Processing Standard FIPS (Fed).
eral Information Processi
ng Standard) draft "AES Propo
sal: Rijndael ", and Rijn there
The processing contents of dael are disclosed, and an outline of the processing contents will be described below.

FIG. 7 shows the configuration of the Rijndael encryption. As shown in FIG. 7, the Rijndael cipher is composed of a pre-processing unit for pre-processing input data, a plurality of data agitation processing units for cyclic conversion, and a post-processing unit for post-processing data to be output. .

FIG. 8 shows a configuration in which the data agitation processing means for cyclic conversion is united. What is different from FIG. 7 is that a single data agitation processing means is recursively used by providing a selector for switching data to be input to the data agitation processing means instead of providing a plurality of data agitation processing means.

The data agitation processing means shown in FIGS. 7 and 8 comprises a data transposing means for transposing data and a data substituting means for substituting data.

From this, a 16-byte plaintext {p0, p1, ..., P15} is converted into a ciphertext {c by using FIGS.
Processing for converting into 0, c1, ..., C15} will be described. First, 16-byte plaintext {p0, p1, ..., p
15} is subjected to an exclusive OR operation with the encryption key by the preprocessing means, and then input to the data agitation processing means via the selector.

The data agitation processing means will be described below. The 16-byte data input to the data agitation processing means is first transposed and converted by the data transposing means. After the transposition conversion of the data is performed, the data substitution conversion is subsequently performed by the data substitution unit. The data transposing means and the data replacing means will be described with reference to FIG.

In FIG. 9, x0, x1, ..., X15 are data of 1 byte each, that is, 16 bytes in total, and are represented by a 4 × 4 byte matrix. 16-byte data {x
FIG. 9 shows how 0, x1, ..., X15} are input to the data transposing means to be transposed and then input to the data transposing means to be transposed.

As shown in FIG. 9, 16-byte input data having a 4 × 4 byte matrix shape {x0, x1, ...
,, x15} is line 0 = {x0, x4, x8, x1
2}, ..., Row 3 {x3, x7, x11, x15} is divided for each row and transposed by the data transposing means, and row 0 = {x0, x4, x8, x12}, ... Transposed as row 3 {x15, x3, x7, x11}. The data transposed by the data transposing means is 16-byte data having the original 4 × 4 byte matrix shape {x0, x5,
x10, x15, x4, x9, x14, x3, x8, x
13, x2, x7, x12, x1, x6, x11} are output to the data substitution unit. In this way, the data transposing means performs data rotation on a row-by-row basis,
It is composed of a register that latches the data after the desired shift.

16-byte data in the form of a transposed 4 × 4-byte matrix {x0, x5, x10, x15,
x4, x9, x14, x3, x8, x13, x2, x
7, x12, x1, x6, x11} are in column 0 = {x0,
x5, x10, x15}, column 1 {x4, x9, x14,
x3}, column 2 {x8, x13, x2, x7}, column 3 {x
12, x1, x6, x11}, and the characters are converted by the data converting means after being divided for each column.

That is, four sets of 4-byte data are converted into four sets of 4-byte data by the data converting means, column 0 = {y0, y1, y.
2, y3}, column 1 = {y4, y5, y6, y7}, column 2
= {Y8, y9, y10, y11}, column 3 = {y12,
The characters are converted into y13, y14, y15}. The data converted by the data conversion means is 16-byte data having the original 4 × 4 byte matrix shape {y0, y1, ...
,, y15} is output. As described above, since the data substituting means performs four sets of substituting in units of 4 bytes, it is configured by using four sets of partial data substituting means.

FIG. 10 shows the structure of the partial data substituting means. The partial data substituting means includes four substituting means for substituting byte (8 bit) data based on the substitution table, and four substituting means.
And a polynomial multiplication circuit for performing polynomial multiplication of byte data.

The 4-byte data input to the partial data substituting means is replaced in byte units by the substituting means,
It is calculated by the polynomial multiplication circuit and output. In this case, the processing time required to execute the data agitation processing means once is
There are two cycles in total, one cycle required by the data transposing means and one cycle required by the data transposing means.

Circulating variables are realized by recursively inputting data into the data agitation processing means described above. When the data agitation processing means is circulated a prescribed number of times, the output of the data agitation processing means is finally subjected to exclusive OR operation with the encryption key by the post-processing means, and then the ciphertext {c0, c1, ...
.., c15} is output.

The case where the circuit scale is limited will be described below. As shown in FIG. 10, the partial data substituting means for substituting characters for each column is configured by using four substitution tables that make the circuit large in terms of hardware implementation. Therefore, instead of preparing partial data substituting means for performing substituting conversion for each column in parallel for the number of columns, one partial data substituting means is sequentially used for each column to implement the partial data substituting means. By using one, the circuit scale is reduced. FIG. 11 shows a configuration in which the circuit scale is reduced in this way.

In this case, since the directions of the data strings for the transposition conversion and the character conversion are different, it is necessary to temporarily store the data after the transposition conversion processing. Further, unlike the configuration shown in FIG. 8, the processing time required to execute the data agitation processing means once is one cycle required by the data transposing means and the partial data substitution means for four columns. A total of 5 cycles are required, including the 4 cycles required for

[0018]

In either case of having four sets of partial data substituting means in the data agitation processing means and in the case of having one set, the direction of the matrix of data for performing transposition conversion and substitution conversion is different. Therefore, it is necessary to perform transposition conversion before substituting the data and determine the data after the transposition conversion. Therefore, the transposed data must be stored once. That is, the data agitation processing means 1
In addition to the processing time required to carry out the substituting conversion, the processing time required to execute the times is one cycle extra as the processing time required to carry out the data transposition conversion.

[0019]

In order to solve the above problems, a data shuffling circuit of the present invention is a circuit for shuffling data by transposition conversion and substitution conversion, and a data dividing means for allocating the data and the data. It is characterized by comprising partial data substituting means for substituting the partial data extracted by the dividing means, data joining means for joining the data, and a buffer memory for temporarily storing an intermediate state of the agitated data.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment) FIG. 1 shows the configuration of a data agitation circuit of the present invention. In FIG. 1, 100 is a pre-processing unit for pre-processing input data, 101 is a data agitation processing unit for performing a data agitation process, 103 is a selector for switching the input to the data agitation processing unit 101, and 104 is a The post-processing means performs post-processing of output data. Further, 120 is input data having a 4 × 4 byte matrix shape, and 121 is output data having a 4 × 4 byte matrix shape.

Here, the data agitation processing means 101 comprises a data dividing means 110, a partial data substituting means 111, a data combining means 112, and a buffer memory 102. The data dividing unit 110 sorts the input 16-byte data into 4-byte data that is output to the partial data substituting unit 111 and 12-byte data that is output to the data combining unit 112, and the partial data substituting unit 111 outputs the input 4 bytes data. The byte data is converted into characters, and the data combination unit 112 combines the 4-byte data converted by the partial data conversion unit 111 and the 12-byte data distributed by the data dividing unit 110 to form a 4 × 4 byte matrix. 16-byte data is output. The 16-byte output data from the data combining unit 112 is held in the buffer memory 102, and the data mixing processing unit 10
1 is output to the outside.

From this, the 16-byte plaintext {p0, p
1, ..., p15} is a ciphertext {c0, c1, ...,
The process of converting to c15} will be described. First, a 16-byte plaintext {p0, p1, ..., P15} is input to the preprocessing unit 100 as input data 120 in a 4 × 4 byte matrix shape. The input data 120 is preprocessed by the preprocessing unit 100, such as an exclusive OR operation with the encryption key, and then input to the data mixing processing unit 101 via the selector 103.

The data shuffling process performed by the data shuffling processing means 101 will be described with reference to FIGS. 2 to 5. In FIG. 2, 200 is input to the data agitation processing means 101 4
Input data of a × 4 byte matrix, and 110 is a data dividing means for dividing the input data 200 into 4 byte string data processed by the partial data substituting means 111 and 12 byte data output to the data combining means 112.

The partial data substituting means 111 performs substituting conversion of the input 4-byte data and outputs the substituting 4-byte data. 112 is a data dividing unit 110
It is a data combining unit that combines the 12-byte data distributed by the above and the 4-byte data converted by the partial data converting unit 111 to generate 16-byte intermediate data A300.

In FIG. 2, of the 4 × 4 byte matrix shape data stirring processing performed by the data stirring processing means 101,
The stirring process for the 0th column of the output data is shown.

16-byte input data {x0, x1, ...
., X15} 200 is input to the data dividing means 110. The input data 200 is 4 by the data dividing means 110.
Byte data {x0, x5, x10, x15} 201a
And 12-byte data {x4, x9, x14, x3, x
8, x13, x2, x7, x12, x1, x6, x1
1} 202 and 4-byte data {a0}
201b is input to the partial data substituting means 111. Here, 4-byte data {x0, x5, x10, x15} 2
01a and {a0} 201b are the same data although they are distinguished for explanation. The partial data conversion unit 111 converts the 4-byte data {a0} 201b into characters and outputs 4-byte data {b0} 203. 12-byte data {x
4, x9, x14, x3, x8, x13, x2, x7,
The x12, x1, x6, x11} 202 and the 4-byte data {b0} 203 are 16-byte intermediate data A {x4, x9, x14, x3, x8, x by the data combining means 112.
13, x2, x7, x12, x1, x6, x11, {b
0}} 300, and is temporarily held in the buffer memory 102.

Next, among the 4 × 4 byte matrix shape data stirring processing performed by the data stirring processing means 101,
The agitation process for the first column of output data is shown in FIG.

1 stored in the buffer memory 102
6-byte intermediate data A {x4, x9, x14, x3, x
8, x13, x2, x7, x12, x1, x6, x1
1, {b0}} 300 is input to the data dividing means 110. Intermediate data A300 by the data dividing means 110
Is 4-byte data {x4, x9, x14, x3} 301
a and 12-byte data {x8, x13, x2, x7, x
12, x1, x6, x11, {b0} 302, and 4-byte data {a1} 301b is input to the partial data substituting means 111.

In this case, the data dividing means 110 is 16
The byte intermediate data A300 is set to 0th of the intermediate data A300.
4-byte data corresponding to the column {x4, x9, x14, x
3} 301a and 12-byte data {x8, x13, x2, x7, corresponding to the first to third columns of the intermediate data A300.
x12, x1, x6, x11, and {b0}} 302.

Here, 4-byte data {x4, x9, x1
4, x3} 301a and {a1} 301b are the same data although they are distinguished for explanation. Partial data substitution means 1
11 is a 4-byte data {a1} 301b is converted into characters,
The 4-byte data {b1} 303 is output. 12-byte data {x8, x13, x2, x7, x12, x1, x
6, x11, {b0}} 302 and 4-byte data {b
1} 303 is 16-byte intermediate data B {x8, x13, x2, x7, x12, x by the data combining means 112.
1, x6, x11, {b0}, {b1}} 400, and are temporarily held in the buffer memory 102.

Further, of the 4 × 4 byte matrix shape data stirring processing performed by the data stirring processing means 101,
The stirring process for the second column of output data is shown in FIG.

1 stored in the buffer memory 102
6-byte intermediate data B {x8, x13, x2, x7, x
12, x1, x6, x11, {b0}, {b1}} 40
0 is input to the data dividing means 110. The intermediate data B400 is 4-byte data {x8, x13, x2, x7} 401a and 12-byte data {x12, x1, x6, x11, {b0}, {b by the data dividing means 110.
1}} 402 and 4-byte data {a
2} 401b is input to the partial data substituting means 111.

In this case, the data dividing means 110 is 16
The byte intermediate data B400 is set to 0th of the intermediate data B400.
4-byte data corresponding to the column {x8, x13, x2, x
7} 401a and 12-byte data {x12, x1, x6, x1 corresponding to the first to third columns of the intermediate data B400.
1, {b0}, {b1}} 402.

Here, 4-byte data {x8, x13, x
2, x7} 401a and {a2} 401b are the same data although they are distinguished for explanation. Partial data substitution means 1
11 is character conversion of 4-byte data {a2} 401b,
The 4-byte data {b2} 403 is output. 12-byte data {x12, x1, x6, x11, {b0}, {b
1}} 402 and 4-byte data {b2} 403 are 16-byte intermediate data C {x1 by the data combining means 112.
2, x1, x6, x11, {b0}, {b1}, {b
2}} 500, and is temporarily held in the buffer memory 102.

Of the 4 × 4 byte matrix shape data stirring processing performed by the data stirring processing means 101,
The agitation process for the third column of output data is shown in FIG.

1 stored in the buffer memory 102
6-byte intermediate data C {x12, x1, x6, x11,
{B0}, {b1}, and {b2}} 500 are input to the data dividing means 110. The data dividing unit 110 converts the intermediate data C500 into 4-byte data {x12, x1, x
6, x11} 501a and 12-byte data {{b0},
{B1}, {b2}} 502 and 4-byte data {a3} 501b is divided into partial data substituting means 111.
Is input to.

In this case, the data dividing means 110 is 16
The byte intermediate data C500 is set to 0th of the intermediate data C500.
4-byte data corresponding to the column {x12, x1, x6, x
11} 501a and 12-byte data {{b0}, {b1}, {b corresponding to the first to third columns of the intermediate data C500.
2}} 502.

Here, 4-byte data {x12, x1, x
6, x11} 501a and {a3} 501b are the same data although they are distinguished for the sake of explanation. The partial data conversion unit 111 converts the 4-byte data {a3} 501b into characters and outputs 4-byte data {b3} 503. The 12-byte data {{b0}, {b1}, {b2}} 502 and the 4-byte data {b3} 503 are data combining means 112.
16 bytes of output data {{b0}, {b1},
It is combined with {b2}, {b3}} 510a and temporarily held in the buffer memory 102.

By the data agitation processing performed by the data agitation processing means 101 described with reference to FIGS. 2 to 5, the agitation of 16-byte data is completed once.

As described above, in the data agitation circuit according to the present embodiment, it is not necessary to determine the transposition conversion of data before the data conversion conversion is performed by the partial data conversion unit 111, and conventionally, the transposition conversion is required. The one cycle that was In this case, the processing time required to execute the data agitation processing means once requires one cycle as the processing for each column of data, so that the processing time for the columns 0 to 3 is 4
There are 4 cycles required for the row.

After that, the data of {{b0}, {b1}, {b2}, {b output from the data agitation processing means 101 after agitating the 16-byte data a prescribed number of times is used.
3}} 510a is 16-byte output data {y0, y1,
..., y15} 510b is input to the post-processing unit 104. The 16-byte output data 510b is subjected to post-processing such as exclusive OR operation with the encryption key by the post-processing means 104, and then 16-byte output data {c0, c1, ... c15} 121
Is output as.

In the present embodiment, the circuit configuration for looping the data agitation processing means 101 shown in FIG. 1 has been described. However, as shown in FIG. 6, the data agitation processing means 101 is provided a prescribed number of times. May be realized with. In this case, although the circuit scale is larger than that in the case of FIG. 1, the processing speed becomes high because pipeline processing is possible.

[0044]

INDUSTRIAL APPLICABILITY The present invention is necessary to perform only the data transposition conversion before the data substitution conversion by extracting the data to be the substitution conversion target from the matrix-shaped data by using the data dividing means. The processing time becomes unnecessary, and the time required for the data agitation processing can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a data mixing circuit.

FIG. 2 is a diagram showing a stirring process for the 0th column.

FIG. 3 is a diagram showing a stirring process for the first row.

FIG. 4 is a diagram showing a stirring process for the second row.

FIG. 5 is a diagram showing a stirring process for the third row.

FIG. 6 is a diagram showing a data mixing circuit (pipeline configuration).

FIG. 7 is a diagram showing a conventional example having a plurality of data agitation processing means.

FIG. 8 is a diagram showing a conventional example having a single data agitation processing unit.

FIG. 9 is a view showing a data transposing means and a data transposing means.

FIG. 10 is a diagram showing partial data substituting means.

FIG. 11 is a diagram showing a conventional example when the circuit scale is limited.

[Explanation of symbols]

100 pretreatment means 101 data agitation processing means 102 buffer memory 103 selector 104 post-processing means 110 data dividing means 111 Partial data substitution means 112 Data combining means 120,200 input data 121,510a, 510b output data 300 Intermediate data A 400 Intermediate data B 500 Intermediate data C

Claims (8)

[Claims] 1. A circuit for performing data agitation processing by transposition conversion and character conversion, comprising data dividing means for allocating data, partial data character converting means for converting character conversion of partial data extracted by said data dividing means, and data A data mixing circuit, comprising: a data combining means for combining; and a buffer memory for holding an intermediate state of data to be mixed. 2. The data has a matrix shape, the transposition conversion is a conversion in a row or column direction of matrix-shaped data, and the substitution conversion is a column or row in a direction different from the transposition conversion. The data agitation circuit according to claim 1, wherein substitution conversion is performed on the data. 3. The data agitation processing is to perform substituting conversion after transposition conversion of matrix shape data, and the data dividing means transfers the same data from the matrix shape data to the partial data substituting means after transposition operation. The data agitation circuit according to claim 2, which outputs the data. 4. The data shuffling process is a transposition conversion after substituting conversion of matrix shape data, wherein the data dividing means combines data to be input from the matrix shape data to the partial data substituting means. The data combining means inputs the output of the partial data substituting means and the output of the data dividing means into data equivalent to that after transposition conversion. The data agitation circuit according to claim 2, wherein the data are combined so that 5. A method for performing data mixing processing by transposition conversion and character conversion, comprising a data dividing step of allocating data, a partial data character converting step of converting the partial data extracted by the data dividing step to character conversion, and A data mixing method comprising: a data combining step of combining data; and a buffer memory that holds an intermediate state of data to be mixed. 6. The data has a matrix shape, and the transposition conversion is conversion in a row or column direction of matrix-shaped data, and the substitution conversion is a column or row in a direction different from the transposition conversion. The data shuffling method according to claim 5, wherein substitution conversion is performed on the data. 7. The data agitation processing is to perform transposition conversion after transposition conversion of matrix shape data, and in the data division step, data similar to that after transposition operation is transferred from the matrix shape data to the partial data conversion step. The data mixing method according to claim 6, wherein the data is output. 8. The data mixing process is a transposition conversion after substituting conversion of matrix shape data, and the data dividing step is a data combination of data to be input from the matrix shape data to the partial data substituting step. Data to be input to the step, and the data combining step inputs the output of the partial data substituting step and the output of the data dividing step into data equivalent to that after transposition conversion. 7. The data agitation method according to claim 6, wherein the data are combined so that