JP2003142967A5 - - Google Patents

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Publication number
JP2003142967A5
JP2003142967A5 JP2001341765A JP2001341765A JP2003142967A5 JP 2003142967 A5 JP2003142967 A5 JP 2003142967A5 JP 2001341765 A JP2001341765 A JP 2001341765A JP 2001341765 A JP2001341765 A JP 2001341765A JP 2003142967 A5 JP2003142967 A5 JP 2003142967A5
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JP
Japan
Prior art keywords
circuit
variable gain
signal
variable
stages
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Pending
Application number
JP2001341765A
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Japanese (ja)
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JP2003142967A (en
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Priority to JP2001341765A priority Critical patent/JP2003142967A/en
Priority claimed from JP2001341765A external-priority patent/JP2003142967A/en
Publication of JP2003142967A publication Critical patent/JP2003142967A/en
Publication of JP2003142967A5 publication Critical patent/JP2003142967A5/ja
Pending legal-status Critical Current

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Claims (5)

複数の周波数分割されたチャネルを持つ信号を受信する受信装置において、
利得可変ループを含み、変動する受信信号レベルをあるレベルに保つための利得可変回路と、
前記利得可変回路の出力に基づいて、複数の隣接チャネルから目的の周波数の信号だけを取出すための複数段の帯域通過フィルタとを含み、
前記複数段の帯域通過フィルタの一部を前記利得可変回路の利得可変ループ内に取り込んだことを特徴とする、受信装置。
In a receiving apparatus that receives a signal having a plurality of frequency-divided channels,
A variable gain circuit including a variable gain loop for maintaining a variable received signal level at a certain level;
A plurality of stages of band-pass filters for extracting only signals of a target frequency from a plurality of adjacent channels based on the output of the variable gain circuit;
A receiving apparatus, wherein a part of the plurality of stages of band-pass filters is incorporated in a variable gain loop of the variable gain circuit.
さらに、前記利得可変回路の後段に接続され、前記受信信号のレベルを制限するためのリミッタ回路と、
前記利得可変回路の利得制御信号のレベルと、前記リミッタ回路の信号レベル検出信号とに基づいて受信信号レベルを検出する受信レベル検出回路とを備えたことを特徴とする、請求項1に記載の受信装置。
Further, a limiter circuit connected to the subsequent stage of the variable gain circuit for limiting the level of the received signal;
The reception level detection circuit according to claim 1, further comprising: a reception level detection circuit that detects a reception signal level based on a level of a gain control signal of the gain variable circuit and a signal level detection signal of the limiter circuit. Receiver device.
前記複数段の帯域通過フィルタのうち、前記利得可変ループ内に取込む段数と前記利得可変回路の出力側に接続される段数を可変にしたことを特徴とする、請求項1に記載の受信装置。  2. The receiving device according to claim 1, wherein among the plurality of stages of band-pass filters, the number of stages to be taken into the variable gain loop and the number of stages connected to the output side of the variable gain circuit are made variable. . さらに、制御信号に応じて前記利得可変ループ内の帯域通過フィルタをバイパスするためのバイパス回路を含むことを特徴とする、請求項1ないし3のいずれかに記載の受信装置。  4. The receiving apparatus according to claim 1, further comprising a bypass circuit for bypassing a band-pass filter in the variable gain loop according to a control signal. さらに、受信信号を第1の中間周波数信号に変換する第1の周波数変換回路と、
前記第1の中間周波数信号を第2の中間周波信号に変換して前記利得可変回路に出力する第2の周波数変換回路とを含むことを特徴とする、請求項1ないし3のいずれかに記載の受信装置。
A first frequency conversion circuit for converting the received signal into a first intermediate frequency signal;
4. A second frequency conversion circuit that converts the first intermediate frequency signal into a second intermediate frequency signal and outputs the second intermediate frequency signal to the variable gain circuit. Receiver.
JP2001341765A 2001-11-07 2001-11-07 Receiver Pending JP2003142967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001341765A JP2003142967A (en) 2001-11-07 2001-11-07 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001341765A JP2003142967A (en) 2001-11-07 2001-11-07 Receiver

Publications (2)

Publication Number Publication Date
JP2003142967A JP2003142967A (en) 2003-05-16
JP2003142967A5 true JP2003142967A5 (en) 2005-06-23

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ID=19155738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001341765A Pending JP2003142967A (en) 2001-11-07 2001-11-07 Receiver

Country Status (1)

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JP (1) JP2003142967A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4596178B2 (en) * 2004-03-24 2010-12-08 日本電気株式会社 Base station apparatus and initial setting method thereof
JP4946372B2 (en) 2006-11-13 2012-06-06 パナソニック株式会社 FILTER CIRCUIT, RECEPTION DEVICE AND ELECTRONIC DEVICE USING THE SAME
CN114978213B (en) * 2022-05-17 2023-07-25 重庆邮电大学 Dynamic gain control system for suppressing impulse noise

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