JP2003142967A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver of which the mounting area and cost are reduced by suppressing a load on a passive filter of the preceding stage by incorporating part of an activated BPF (band pass filter) in an AGC circuit and in which the response speed of RSSI (receiving signal strength indicator) is made high by using a control signal for AGC and the RSSI of a detecting circuit of a limiter in combination. SOLUTION: A receiving signal is converted down to a 1st intermediate frequency by a 1st mixer 21 of a reception front end 20 and filtered by a crystal filter 22, and the 1st intermediate-frequency signal is converted down to a 2nd intermediate frequency by a 2nd mixer 31. One stage of a BPF 33 which is made active is inserted into the AGC circuit 32 and the BPF 33 can be powered off with a control signal 38 and bypassed; and the receiving signal outputted from the AGC circuit 32 is inputted to a main BPF 34 and inputted to a limiter circuit 35, whose LIM output is inputted to a base band part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver,
In particular, the present invention relates to the circuit configuration of a receiver having an interference wave filtering circuit.

[0002]

2. Description of the Related Art In a receiving device such as a mobile phone serving as a mobile communication terminal, a high frequency carrier frequency assigned to the radio system is modulated by a number of subcarriers which are frequency-divided. Each sub-carrier frequency is configured so that audio data, video data, and other control data are modulated and transmitted / received in a channel of a specific frequency band divided into time slots of several tens of channels.

In such a system, the input reception signal level received by the terminal varies greatly depending on the usage environment,
There is also a bad environment in which the signal level of the desired wave of the target channel is low and strong interfering waves exist in adjacent channels. Therefore, as a receiver used for such mobile communication, a high frequency circuit of W super reception system is generally adopted. In addition, filters such as crystals and ceramics are used to accurately extract the target frequency.

FIG. 4 is a block diagram of a conventional receiver having a filtering device (passive filter) using physical properties such as crystals and ceramics. In FIG. 4, the reception signal received by the antenna is down-converted to a first intermediate frequency by a first mixer (not shown), and then is converted to a first intermediate frequency amplifier circuit composed of a crystal filter 1 in order to obtain sufficient filtering performance. Given. The first intermediate frequency signal is down-converted to the second intermediate frequency signal by the second mixer 2 and is given to the second intermediate frequency amplifier circuit including the ceramic filter 3. This second intermediate frequency signal is given to the limiter circuit 4, and the waveform thereof is shaped so as to have a constant amplitude, so that the influence of the fluctuation in the vibration of the received signal is removed.

As a result, in a normal reception state, the limiter circuit 4 derives a LIM output of a substantially constant level as its output even if the received signal level has strength. The output of the limiter circuit 4 is a low-pass filter (LP
F) The RSSI (Receiving S) indicating the strength level of the received signal level given to 5 and smoothed.
(Signal Strength Indicator)
The signal is output.

In the receiver having the configuration shown in FIG. 4, the ceramic filter 3 is particularly large and the mounting area is large, which hinders downsizing and cost reduction of the receiver. Therefore, the filtering characteristic of the ceramic filter 3 is applied to a semiconductor circuit by an IC.
A built-in receiving device has been put to practical use.

FIG. 5 is a block diagram of such a receiving device. A portion surrounded by a broken line in FIG. 5 is an integrated circuit 6 which is an integrated circuit. The second intermediate frequency signal output from the second mixer 7 is supplied to the AGC circuit 8, and the activated circuit in the subsequent stage is kept constant. Because it comes to have a saturation level, A
The received signal level is kept below the saturation level by the GC circuit 8. The output of the AGC circuit 8 is given to the limiter circuit 10 via the active filter 9.

[0008]

When the band of the detection circuit used in the AGC circuit 8 shown in FIG. 5 is wide, the gain of the AGC is changed by not only the desired wave but also the interfering wave.
If the level of the disturbing wave is large and the level of the desired wave is relatively small, the level of the desired wave may be suppressed due to the AGC characteristic with respect to the disturbing wave, causing deterioration in sensitivity of the desired wave.

If AGC is applied to the modulation envelope in this state, amplitude distortion occurs even if the desired wave level is relatively large, and demodulation characteristics deteriorate. Therefore, it is necessary to insert a bandpass filter (BPF) also in the preceding stage of the AGC circuit 8 to remove the interfering wave. In the example shown in FIG. 5, the number of poles of the crystal filter 1 of the first intermediate frequency amplifier circuit is increased to secure the filtering ability as a 3-pole crystal filter.

However, since the number of poles of the crystal filter 1 is increased, the size and cost of the crystal filter 1 are disadvantageous, and the ceramic filter 3 shown in FIG.
The meaning of converting to IC will fade.

If the band of the detection circuit used in the AGC circuit 8 is narrowed, the reaction speed of the AGC cannot be increased due to the delay of the bandpass characteristic in the AGC circuit 8. For example, in the mobile radio receiver described in Japanese Patent Laid-Open No. 11-187463, the detection signal after AGC and the detection circuit of the limiter are used together. However, the filter is AGC
Since everything is put in the loop, the AGC operation must be slowed down.

As described above, the conventional receiving device has a problem that the mounting area is disadvantageous in the passive filter and the cost of the BPF provided before the AGC is disadvantageous in the IC filter. In the IC filter, R
There is also a problem that the reaction speed of SSI becomes slow.

Therefore, the main object of the present invention is to
By partially incorporating the activated BPF into the GC circuit, the load of the passive filter in the previous stage can be suppressed to reduce the mounting area and cost, and the control signal of the AGC and the RSSI of the limiter detection circuit can be used together. At RS
It is an object of the present invention to provide a receiver capable of increasing the reaction speed of SI.

[0014]

SUMMARY OF THE INVENTION The present invention, in a receiver for receiving a signal having a plurality of frequency-divided channels, includes a variable gain loop and has a variable gain for maintaining a variable received signal level at a certain level. Circuit, and a bandpass filter for extracting only a signal of a desired frequency from a plurality of adjacent channels based on the output of the variable gain circuit. A part of the bandpass filter is included in the variable gain loop of the variable gain circuit. It is characterized by having been captured.

As a result, the load of the passive filter in the preceding stage is suppressed and the mounting area and the cost are both reduced.
By using the GC control signal and the RSSI of the limiter detection circuit together, the reaction speed of RSSI can be increased.

Further, it is connected to the latter stage of the variable gain circuit,
A limiter circuit for limiting the level of the received signal; and a reception level detection circuit for detecting the received signal level based on the level of the gain control signal of the variable gain circuit and the signal level detection signal of the limiter circuit. Characterize.

Further, the bandpass filter is characterized in that the number of stages taken into the variable gain loop and the number of stages connected to the output side of the variable gain circuit are made variable.

Further, it is characterized by including a bypass circuit for bypassing the band pass filter in the variable gain loop in response to the control signal.

Further, a first frequency conversion circuit for converting the received signal into a first intermediate frequency signal and a second frequency conversion circuit for converting the first intermediate frequency signal into a second intermediate frequency signal and outputting the gain variable circuit. And a frequency conversion circuit of.

[0020]

1 is a block diagram of a receiver according to an embodiment of the present invention. In FIG. 1, the reception signal received by the antenna 40 is the reception front end 2
It is down-converted to the first intermediate frequency by the first mixer (frequency conversion circuit) 21 of 0, filtered by the crystal filter 22 in the same manner as in the conventional example, and given to the reception back end 30. In the reception back end 30, the first intermediate frequency signal is down-converted to the second intermediate frequency by the second mixer 31 and given to the AGC circuit 32 as a gain variable circuit.

One stage of activated BPF 33 is inserted in the variable gain loop of the AGC circuit 32.
It complements the interference wave filtering performance up to the C detector. The BPF 33 is powered off by a control signal 38 provided from a control unit (not shown) when the timing at which the AGC follow-up property such as the burst head becomes a problem and the interfering wave is so small as not to cause a problem. By-passing is enabled, the AGC is operated at high speed, and at the same time, current consumption is reduced.

The reception signal output from the AGC circuit 32 is input to the main BPF 34, and finally to the limiter circuit 35, and the LIM output is input to a baseband section (not shown).

The AGC gain control signal 37 is added to the output of the limiter circuit 35 by an adder circuit 36 as a reception level detection circuit, converted into a voltage according to the gain, and output as an RSSI signal, which is sampled by the baseband section. To be done. Further, the LIM output of the limiter circuit 35 is also sampled by the baseband unit.

The BPF3 incorporated in the AGC loop
By changing the number of stages of 3 and the number of stages of the BPF 34 at the rear stage,
The filtering ability of the GC and the response speed of the AGC may be adjusted so that the filtering ability for the interfering wave and the detection speed of the received signal level are compatible with each other.

FIG. 2 shows an RS according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining the SI detection method, and FIG. 3 similarly shows an RSSI waveform.

The waveform diagrams of FIGS. 2A to 2C show the case where there is no interfering wave. The desired wave shown in FIG. 2A has a certain AGC gain and is amplified by the AGC circuit 32. Figure 2
The waveform of the level shown in (b) is obtained, and since there is no interfering wave, the BPF 33 is bypassed by the control signal 38, passes through the BPF 34, and the waveform shown in FIG. 2C is output from the limiter circuit 35. The adder circuit 36 subtracts the gain voltage of AGC from the RSSI voltage of the limiter circuit 35 and outputs an RSSI signal. When there is no interfering wave as described above, the BPF 33 is not inserted in the AGC loop, so that the AGC operation will not be delayed.

On the other hand, when there is an interfering wave shown by the broken line in FIG. 2D, the level of the desired wave shown by the solid line is suppressed as shown in FIG. 2E due to the AGC characteristics for the interfering wave. . At this time, the control signal 38 causes the AG
The BPF 33 is inserted in the variable gain loop of the C circuit 32, and the interference wave is removed by the BPF 33 as shown in FIG. The adder circuit 36 is the RS of the limiter circuit 35.
Add the SI voltage and the gain voltage of AGC to RSS
Output I signal. If there is such an interfering wave, AG
The interference wave can be removed by inserting the BPF 33 in the variable gain loop of the C circuit 32.

When bypass control in the AGC is not performed,
As shown in FIG. 3A, the rising edge of the RSSI signal becomes gentle. However, the BPF 33 in the AGC is bypassed when high-speed pulling-in of the AGC is required at the start of reception. As a result, as shown in FIG. 3B, the delay due to the BPF 33 is eliminated, and the LPF time constant of the AGC is switched to converge at a high speed, so that the gain control voltage is converged at a high speed, and the RSSI due to the fluctuation of the reception level. The voltage ripple is also improved.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0030]

As described above, according to the present invention, a receiving device that keeps a varying received signal level at a certain level by a variable gain circuit and extracts only signals of a target frequency from a plurality of adjacent channels by a bandpass filter. In the above, since a part of the bandpass filter is incorporated in the loop circuit of the variable gain circuit, the load of the preceding passive filter is suppressed, the mounting area is reduced and the cost is reduced, and the control signal of the AGC and the limiter are reduced. RSSI of detection circuit
It becomes possible to speed up the reaction speed of RSSI by using together.

In addition, when the BPF for ensuring the adjacent channel selectivity is activated, the filter characteristic of the preceding stage can use the performance equivalent to that of the conventional one, which is advantageous in terms of cost.

Further, even if there is an interfering wave, it is possible to detect the RSSI with a small error. Furthermore, the RSSI signal can be detected at high speed when the received signal level changes abruptly or when the power of the receiver is turned on. Therefore, it is possible to configure an inexpensive receiver with high RSSI detection accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram of a receiving device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an RSSI detection method according to an embodiment of the present invention.

FIG. 3 is a diagram showing an RSSI waveform according to an embodiment of the present invention.

FIG. 4 is a block diagram of a conventional receiver having a filtering device (passive filter) using physical properties such as crystals and ceramics.

FIG. 5 is a block diagram of a receiver in which the filtering characteristics of a ceramic filter are integrated in an IC with a semiconductor circuit.

[Explanation of symbols]

20 reception front end, 21 first mixer, 22
Crystal filter, 30 Reception backend, 31
Second mixer, 32 AGC circuit, 33, 34 BPF, 3
5 limiter circuit, 36 adder circuit, 37 AGC gain control signal, 38 control signal.

Claims (5)

[Claims] 1. A receiver for receiving a signal having a plurality of frequency-divided channels, comprising a variable gain loop, and a variable gain circuit for keeping a variable received signal level at a certain level, and the variable gain circuit. A plurality of stages of band pass filters for extracting only signals of a target frequency from a plurality of adjacent channels based on the output, and a part of the plurality of stages of band pass filters in a gain variable loop of the gain variable circuit. Featured in
Receiver. 2. A limiter circuit connected to the latter stage of the gain variable circuit for limiting the level of the received signal, a level of a gain control signal of the gain variable circuit, and a signal level detection of the limiter circuit. The reception device according to claim 1, further comprising a reception level detection circuit that detects a reception signal level based on the signal. 3. Of the plurality of stages of bandpass filters,
The receiving device according to claim 1, wherein the number of stages taken into the variable gain loop and the number of stages connected to the output side of the variable gain circuit are variable. 4. The receiving apparatus according to claim 1, further comprising a bypass circuit for bypassing a bandpass filter in the variable gain loop according to a control signal. 5. A first frequency conversion circuit for converting a received signal into a first intermediate frequency signal; and a gain variable circuit for converting the first intermediate frequency signal into a second intermediate frequency signal. The receiving device according to claim 1, further comprising a second frequency conversion circuit for outputting.