JP2003142963A - Input circuit of ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a high-frequency characteristic by reducing the input capacity of an AD converter. SOLUTION: A preamplifier of the AD converter is provided with a source follower circuit which drives a bulk terminal B1 of an input MOS transistor M1 according to an analog signal. This source follower circuit comprises a MOS transistor M3 which is applied with the analog signal Vin at its gate and has its source connected to the bulk terminal B1 of the MOS transistor M1 and a current source 12 which supplied a bias current to the MOS transistor M3. Consequently, even if the input analog signal Vin various, a current hardly flows to the gate-bulk capacitor (Cgb), and hence the contribution of the gate- bulk capacitor (Cgb) to an input capacitor is nearly eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of an AD converter for converting an analog signal into a digital signal, and more particularly to a circuit technology for improving the high frequency characteristics of the AD converter.

[0002]

2. Description of the Related Art In an AD converter for converting an analog signal into a digital signal, the structure of the fastest AD converter is realized by a parallel type structure which requires comparators (power of 2-1) of resolution. It is often done.

FIG. 4 shows a circuit diagram of such a parallel type AD converter. In the input section of this AD converter, N preamplifiers 10-1 to 10-N (pre-stage amplifiers) are arranged in parallel.
The preamplifiers 10-1 to 10-N are provided to reduce the demand for detection error such as the offset voltage of the comparator connected to the next stage. When the resolution of the AD converter is m bits, N = 2 ^m −1. For example, if the resolution is 8 bits, 255 preamplifiers are required.

The input analog signal Vin from the input terminal 1 is commonly applied to the gates of the MOS transistors M1 of the preamplifiers 10-1 to 10-N. On the other hand, reference voltages Vref1 to VrefN are applied to the gates of the MOS transistors M2 of the preamplifiers 10-1 to 10-N, respectively. The resistor string 22 is connected between the high voltage Vrefp and the low voltage Vrefm generated by the voltage source 20 (N-
1) It is composed of one resistor R. These reference voltages Vref1 to VrefN are generated from the connection points of the resistor string 22.

Further, as described above, the current source 11 for supplying a current to the MOS transistors M1 and M2 forming the differential pair is provided. MOS transistors M1 and M2
Load resistors R1 and R2 are connected between the power supply voltage Vdd and the power supply voltage Vdd (for example, +5 V), and differential outputs are taken out from the connection points.

These preamplifiers 10-1 to 10
The differential output of -N is input to the non-inverting input (+) and the inverting input (-) of the comparators 30-1 to 30-N in the next stage.
The respective outputs of the comparators 30-1 to 30-N are further input to the digital encoder 40 to generate digital signals.

[0007]

As described above, in the parallel type AD converter, for example, when the resolution is 8 bits, 255 preamplifiers and comparators are required, and the analog input signal is fed to these 255 preamplifiers. Connected.

By the way, in recent years, the AD converter is a CMOS
Often realized as an LSI. At this time, the input capacitance of the 255 preamplifiers becomes a large value (for example, about 10 pF), so that the high frequency analog input signal is attenuated and the high frequency characteristics of the CMOS AD converter are deteriorated. .

FIG. 5 is a circuit diagram showing the configuration of one preamplifier. MOS to which input analog signal Vin is applied
The bulk terminal B1 (substrate terminal) of the transistor M1 is connected to the ground voltage Vss (0V). The input capacitance of the preamplifier is the sum of parasitic capacitances associated with the MOS transistor M1, and specifically, the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgs) of the MOS transistor M1.
gd), gate-bulk capacitance (Cgb), and its mirror effect. Here, the gate-bulk capacitance (Cg
The contribution of b) to the input capacitance is 2-3 of the total input capacitance.
Account for

[0010]

Therefore, the present invention aims to improve the high frequency characteristics of the CMOS AD converter by eliminating the contribution of the gate-bulk capacitance (Cgb) to the input capacitance.

That is, the characteristic configuration of the present invention is that the first M
By newly providing a source follower circuit that drives the bulk terminal B1 of the OS transistor M1 according to the analog signal, the potential of the bulk terminal B1 also changes in accordance with the change of the input analog signal Vin.・ Voltage between bulks is almost constant. Therefore, even if the input analog signal Vin changes, the gate-bulk capacitance (Cgb)
Almost no current flows into. Therefore, the gate
The bulk capacitance (Cgb) has almost no contribution to the input capacitance.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a preamplifier (pre-stage amplifier) according to the embodiment of the present invention. The overall configuration of the AD converter is the same as, for example, a parallel AD converter similar to that shown in FIG.
The feature of the present invention is that the configuration of the preamplifiers 10-1 to 10-N is changed.

That is, as shown in FIG. 1, a source follower circuit for driving the bulk terminal B1 of the MOS transistor M1 according to an analog signal is newly provided. In this source follower circuit, an analog signal Vin is applied to the gate, and the source is a MOS transistor M3 connected to the bulk terminal B1 of the MOS transistor M1.
The current source 12 supplies a bias current to the MOS transistor M3. Other configurations are similar to those of the conventional preamplifier. Here, the MOS transistors M1, M2 and M3 are all N-channel type.

As a result, the potential of the bulk terminal B1 changes in association with the change of the input analog signal Vin, so that the gate-bulk voltage becomes substantially constant. Therefore, even if the input analog signal Vin changes, almost no current flows into the gate-bulk capacitance (Cgb). Therefore, the contribution from the gate-bulk capacitance (Cgb) to the input capacitance is almost eliminated.

Incidentally, these MOS transistors M1,
It is preferable that M2 and M3 are formed in well regions separated for each preamplifier 10-1 to 10-N in order to eliminate mutual interference.

The size (GW / GL) of the MOS transistors M1 and M2 forming the differential pair is, for example, 1.
If the size is 00 μm / 0.35 μm, the size (GW / GL) of the MOS transistor M3 is 10 μm / 0.35 μm.
m is about 1/10. Here, GW is the gate width of the transistor, and GL is the gate length. Further, the bias current of the current source 11 that supplies the bias current to the MOS transistors M1 and M2 forming the differential pair is, for example, 2
Assuming 00 μA, the bias current of the current source 12 that supplies the bias current to the MOS transistor M3 is 20 μA.
Then, about 1/10 is enough. The load resistances R1 and R2 are both 1 KΩ. As a result, the increase in power consumption and chip area due to the provision of the source follower circuit is slight.

FIG. 2 is a device structure diagram of one preamplifier formed on a semiconductor substrate. A P-type well region 51 is formed on the surface of an N-type silicon substrate 50 by thermal diffusion. Then, in the P-type well region 51,
N-channel type MOS transistors M1, M2 and M3 are formed.

The structure of the MOS transistors M1, M2, M3 is a conventional type having N + type source / drain layers in FIG. 2, but it is preferable to adopt an LDD structure in order to suppress the short channel effect. Here, the bulk terminals B1, B2, B3 of the MOS transistors M1, M2, M3 are formed of P + layers and are connected to the P-type well region 51 with low resistance.

Although the preamplifier is formed using the N-type silicon substrate in FIG. 2, a deep N-type well region is formed on the P-type substrate, and a P-type well is further formed in the deep N-type well region. A region may be formed, and N-channel type MOS transistors M1, M2, M3, etc. may be formed in the P-type well region.

FIG. 2 shows one preamplifier,
Other preamplifiers are formed on the N-type silicon substrate 50 in separate P-type well regions (not shown) separated from the P-type well region 51.

FIG. 3 shows the result of the circuit simulation of the input capacitance. The horizontal axis is the input analog input signal Vin (V),
The vertical axis represents the input capacitance Cin (pF). The above-mentioned numerical values (transistor size, etc.) are used as parameters for circuit simulation.

As is clear from the result of this circuit simulation, the input capacitance using the preamplifier of the present invention is larger than the input capacitance (shown by the broken line) when the preamplifier of the conventional example is used. Although it shows non-linearity depending on Vin, it can be seen that it is reduced by 20 to 30% as a whole. This is an effect that the gate-bulk capacitance (Cgb) hardly contributes to the input capacitance due to the provision of the source follower circuit.

In the above embodiment, the preamplifier 10-1 is used.
N-channel MOS transistors M1 and M are connected to 10-N
Although 2 and M3 are used, the input capacitance can be reduced by using the same configuration even when a P-channel type MOS transistor is used.

In the above-described embodiment, the comparator 3 is used after amplification by the preamplifiers 10-1 to 10-N.
Although the AD converter in which a digital signal is generated through the digital encoders 0-1 to 30-N has been described, the present invention is characterized by the configuration of the preamplifiers 10-1 to 10-N. The present invention is not limited to the application to a device, but includes an AD having a plurality of pre-amplifiers arranged in parallel.
It can be widely applied to converters, and more specifically, all products that convert analog signals into digital signals and perform digital signal processing, for example, FFT of measuring instruments.
When applied to products such as analyzers and digital oscilloscopes, their high frequency characteristics can be significantly improved.

[0025]

According to the present invention, in the pre-stage amplifier of the input section of the AD converter, the bulk terminal of the input MOS transistor M1 to which the input analog signal is applied is driven by the source follower circuit, so that the input MOS transistor M1 is driven. It is possible to separate the gate-bulk capacitance (Cgb) from the AD converter, and as a result, improve the high frequency characteristics of the AD converter.

M constituting the source follower circuit
The size of the OS transistor M3 is one of the sizes of the MOS transistors M1 and M2 that form the differential pair of the preamplifier.
Since the bias current of the MOS transistor M3 is about 1/10 of the bias current of the MOS transistors M1 and M2, the increase in power consumption and chip size due to the provision of the source follower circuit is AD conversion. It is very small when viewed from the whole vessel.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a preamplifier of an AD converter according to an embodiment of the present invention.

FIG. 2 is a device structure diagram when the preamplifier according to the embodiment of the present invention is realized on a semiconductor substrate.

FIG. 3 is a diagram showing a circuit simulation result of input capacitance.

FIG. 4 is a circuit diagram showing a configuration of an AD converter according to a conventional example.

FIG. 5 is a circuit diagram showing a configuration of a preamplifier according to a conventional example.

[Explanation of symbols]

1 input terminal 11 current source 12 Current source 20 voltage source 22 resistor string 40 digital encoder 50 N type silicon substrate 51 P-type well region

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasuyuki Kimura             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Hideyuki Kogure             1151 Teshigawara, Kamizato-cho, Kodama-gun, Saitama Prefecture F term (reference) 5J022 AA06 BA05 CD03 CF01 CF04                 5J066 AA01 AA12 AA21 CA16 CA61                       FA02 FA20 HA10 HA25 KA05                       KA17 KA33 MA02 ND01 ND11                       ND22 ND23 PD02 QA02 SA00                       TA02                 5J069 AA01 AA12 AA21 CA16 CA61                       FA02 FA20 HA10 HA25 KA05                       KA17 KA33 MA02 QA02 SA00                       TA02                 5J500 AA01 AA12 AA21 AC16 AC61                       AF02 AF20 AH10 AH25 AK05                       AK17 AK33 AM02 AQ02 AS00                       AT02 DN01 DN11 DN22 DN23                       DP02

Claims (9)

[Claims] 1. An input circuit of an AD converter for converting an analog signal into a digital signal, comprising a plurality of pre-stage amplifiers to which an analog signal is commonly applied, and each pre-stage amplifier has an analog signal applied to its gate. The first MO
An S transistor, a reference voltage is applied to the gate, and a second MOS transistor that forms a differential pair with the first MOS transistor and a bulk terminal of the first MOS transistor are driven according to the analog signal. An input circuit of an AD converter comprising a source follower circuit. 2. The source follower circuit according to claim 3, wherein the analog signal is applied to a gate and a source is connected to a bulk terminal of the first MOS transistor.
2. The input circuit of the AD converter according to claim 1, further comprising: a MOS transistor and a current source that supplies a bias current to the third MOS transistor. 3. The input circuit of the AD converter according to claim 2, wherein the size of the third MOS transistor is smaller than the sizes of the first and second MOS transistors. 4. The first, second and third MOS transistors are formed in well regions separated from each other for each of the pre-stage amplifiers. Input circuit of AD converter. 5. The first, second, and third MOS transistors are transistors of a first conductivity type, and the first, second, and third MOS transistors are on a semiconductor substrate of a first conductivity type. 5. The AD according to claim 4, wherein the AD is formed in the formed well region of the second conductivity type.
Input circuit of the converter. 6. An input circuit of an AD converter for converting an analog signal into a digital signal, comprising a plurality of pre-stage amplifiers to which an analog signal is commonly applied, and each pre-stage amplifier has an analog signal applied to its gate. The first MO
An S transistor, a second MOS transistor having a gate to which a reference voltage is applied and forming a differential pair with the first MOS transistor, and the first and second MOS
A first current source for supplying a bias current to the transistor; a third MOS transistor having a gate to which the analog signal is applied and a source connected to a bulk terminal of the first MOS transistor; MOS
A second current source for supplying a bias current to the transistor, and an input circuit of the AD converter, comprising: 7. The input circuit of an AD converter according to claim 6, wherein the bias current supplied by the second current source is smaller than the bias current supplied by the first current source. 8. The AD according to claim 6, wherein the size of the third MOS transistor is smaller than the sizes of the first and second MOS transistors.
Input circuit of the converter. 9. The AD converter according to claim 8, wherein the first, second and third MOS transistors are formed in well regions separated from each other for each of the pre-stage amplifiers. Input circuit.