JP2003141726A - Optical information recording device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the deviation of an optical modulation waveform from a desired value caused by the distortion, skewing or the like of an optical modulation control signal waveform, and to meet the requirements of a higher speed of information recording and higher density recording on an information recording medium without sacrificing costs or performance. SOLUTION: A light is emitted from a light source by a plurality of pulse train waveforms based on a multivalued irradiation level corresponding to a binary signal recorded on an information recording medium and, when the information recording medium is irradiated with the emitted light to form a recording mark corresponding to the binary signal, a frequency and a duty of the pulse train waveforms is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to information on a recordable information recording medium such as a CD-R drive device, a CD-RW drive device, a DVD-R drive device, a DVD-RW drive device and a DVD-RAM drive device. The present invention relates to an optical information recording device for recording information.

[0002]

2. Description of the Related Art Conventionally, in an optical disc apparatus for recording information by optical modulation of a laser beam applied from a light source to a recordable optical disc (information recording medium),
Beam overwrite technology and control by making the light modulation waveform multi-pulse and multi-level (for example, refer to the light modulation waveform of FIG. 4C) for controlling the recording mark shape for higher density. This technique is indispensable, and accordingly, it is necessary to switch a plurality of currents in the light source drive section (hereinafter, also referred to as “LD driver”), and as a result, the number of input signal lines increases.

Further, in order to perform high-speed recording and high-density recording on an optical disk, it is required to further increase the data transfer rate, further divide the pulse division width, and further increase the number of power levels. Has been done. Furthermore, since the pickup equipped with the light source is movable in the radial direction of the optical disc (this operation is called "seek operation"), the pickup and the circuit board on which the signal processing unit and the like are mounted are flexible circuits ( Flexible
Generally, a flexible substrate called a Print Circuit (FPC) substrate is used for connection, and the LD driver is arranged in the vicinity of a light source (LD) mounted in the pickup, and the LD is connected from the signal control unit. The FPC board is used for wiring up to the driver.

However, an FPC that supplies an optical modulation control signal
Since it is inevitable that the board will be a certain length,
Displacement of the switch timing of the LD drive current due to distortion, delay (especially delay difference (skew) between a plurality of control signals) of the optical modulation control signal waveform, and the waveform is disturbed when the switches are switched at the same time. Cannot emit laser light with a desired optical waveform (see FIG. 13). Therefore, the accuracy of the mark shape and the position of the mark formed on the optical disc is impaired, resulting in a data error. Further, a problem of unnecessary radiation from the FPC board occurs, which causes noise.

In order to solve such a problem, the currents of a plurality of current sources are supplied to the light source (LD) through the switch means.
To drive the LD and a drive waveform for driving the LD in response to the binarized recording signal to be recorded on the optical disc (information recording medium), and a drive waveform for controlling the switch means. A light source driving device provided with the same means in the same laser driving integrated circuit (for example, JP-A-11-28).
3249 gazette) is proposed.

[0006]

In the conventional light source driving device as described above, when further speeding up of information recording and high density recording on an optical disk are required in the future, the drive waveform restoring means (optical modulation control signal) is required. Since a higher speed operation of the generation unit) and higher integration of the laser driving integrated circuit are required, a fine CMOS process is suitable. On the other hand, the LD
Since an LD having an operating voltage of about 1 to several V is connected to the drive unit, a high breakdown voltage process (for example, 5 V or 3.3 V) is required. However, usually fine CMO
It is difficult to obtain a high breakdown voltage in the S process (for example, 0.
Since the 18 μm CMOS process has a withstand voltage of only about 1.8 V), it is difficult to realize high speed, or there are problems such as a significant increase in cost, an increase in power consumption, and an increase in integrated circuit size.

Further, depending on the information recording medium, a more complicated optical modulation waveform may be required. For example, when performing high-speed recording, the transit time of the irradiation beam on the information recording medium is shortened, so the amount of energy applied to the information recording medium is reduced, and the amount of heat required to form a recording mark is insufficient. For accurate recording, recording may be performed with a pulse train having a very narrow pulse width, but for that purpose, high laser power is required. Therefore, a method of lowering the frequency of the multi-pulse train and recording with low laser power has been proposed.

On the other hand, when low-speed recording is performed on an information recording medium having high recording sensitivity for high-speed recording, the amount of heat becomes excessive and accurate recording marks cannot be formed. Therefore, a method of increasing the frequency of the multi-pulse train for recording has been proposed. As described above, although various recording methods have been proposed for various types of information recording media, none of them can be handled by the same circuit. There is a demand for a variety of optical modulation waveforms, such as changing the pulse frequency and increasing the multilevel.

The present invention has been made to solve the above problems, and suppresses the deviation of the optical modulation waveform from the desired value due to the distortion or skew of the optical modulation control signal waveform, thereby increasing the speed of information recording. It is an object of the present invention to realize a demand for high density recording on an information recording medium without sacrificing cost and performance.

[0010]

In order to achieve the above object, the present invention provides the following optical information recording devices (1) to (11). (1) The light source is caused to emit light in a plurality of pulse train waveforms based on a multi-valued irradiation level corresponding to a binary signal for recording on the information recording medium, and the emitted light is applied to the information recording medium to cause the binary value. An optical information recording apparatus for forming a recording mark corresponding to a converted signal, wherein the frequency and duty of the pulse train waveform are set arbitrarily.

(2) A light source is caused to emit light with a plurality of pulse train waveforms based on a multi-valued irradiation level corresponding to a binary signal for recording on the information recording medium, and the emitted light is irradiated to the information recording medium. In an optical information recording device for forming a recording mark corresponding to the binarized signal, at least one each of timing information indicating each pulse width of the plurality of pulse train waveforms and pulse number information indicating the number of repetitions of the timing information. Drive waveform generation information holding means for storing the above,
An information selecting means for selecting one of the timing information based on the binarized signal, and a timing of changing the irradiation level based on the timing information and the pulse number information selected by the information selecting means are shown. The modulation signal generation means for generating the modulation signal, the modulation signal generated by the modulation signal generation means, the state transition signal for instructing the transition of the state corresponding to the irradiation level, and the state based on a preset transition rule An optical information recording apparatus provided with a light source drive means for controlling the transition of the light source and driving the light source based on the selected state.

(3) The light source is caused to emit light with a plurality of pulse train waveforms based on a multilevel irradiation level corresponding to a binary signal for recording on the information recording medium, and the emitted light is irradiated to the information recording medium. In an optical information recording device for forming a recording mark corresponding to the binarized signal, at least one each of timing information indicating each pulse width of the plurality of pulse train waveforms and pulse number information indicating the number of repetitions of the timing information. Drive waveform generation information holding means for storing the above,
Information selecting means for selecting one of the timing information for each of the timing information based on the binarized signal, and the change timing of the irradiation level based on the timing information and the pulse number information selected by the information selecting means. Based on the modulation signal generating means for generating the modulation signal shown, the modulation signal generated by the modulation signal generating means, the state transition signal indicating the transition of the state corresponding to the irradiation level, and the preset transition rule At least one of the light source driving means for controlling the state transition and driving the light source based on the selected state, and the state corresponding to at least one of the irradiation levels of the plurality of pulse train waveforms is a plurality of irradiations. Corresponding to the level, one of them is selected according to the irradiation level selection information, and the irradiation level corresponding to the above state is selected above. The optical information recording apparatus provided with the illumination level selection means for changing Le.

(4) The light source is caused to emit light with a plurality of pulse train waveforms based on a multi-valued irradiation level corresponding to a binary signal for recording on the information recording medium, and the emitted light is applied to the information recording medium. In an optical information recording device for forming a recording mark corresponding to the binarized signal, at least one each of timing information indicating each pulse width of the plurality of pulse train waveforms and pulse number information indicating the number of repetitions of the timing information. Drive waveform generation information holding means for storing the above,
Information selecting means for selecting one for each of the timing information according to a recording mark length indicated by the binarized signal or a combination of a space length before and after the recording mark length, and the information selecting means. Modulation signal generating means for generating a modulation signal indicating the change timing of the irradiation level based on the timing information and the pulse number information, a modulation signal generated by the modulation signal generating means, and a state corresponding to the irradiation level. Light source driving means for controlling the transition of the state based on a state transition signal instructing the transition and a preset transition rule, and driving the light source based on the selected state, and irradiation of the plurality of pulse train waveforms At least one of the states corresponding to at least one of the levels corresponds to a plurality of irradiation levels, and the recording mark length or its Irradiation level selection that selects one of them according to the irradiation level selection information generated according to the combination of the space length before and after the recording mark length, and changes the irradiation level corresponding to the above state to the selected irradiation level An optical information recording device provided with means.

(5) In the optical information recording device according to (2) or (3), the information selecting means has a recording mark length that is an odd number or an even number with respect to a reference recording clock, or an odd number except for a specific mark length. An optical information recording device which is a means for selecting the timing information depending on whether it is an even number. (6) In the optical information recording device according to (4), the timing information of the timing selection means is selected depending on whether the recording mark length is an odd number or an even number with respect to the reference recording clock, or whether the recording mark length is an odd number or an even number excluding the specific mark length. An optical information recording device adapted to perform selection and generation of the irradiation level selection information. (7) The optical information recording device according to any one of (2) to (6), wherein the timing information and the pulse number information are changed according to a recording linear velocity.

(8) In the optical information recording apparatus of (3) or (4), the state in which the irradiation level is changed by the irradiation level selecting means corresponds to the head pulse irradiation level of the pulse train waveform. Optical information recording device. (9) In the optical information recording device according to (3) or (4), the state in which the irradiation level is changed by the irradiation level selecting means corresponds to the final pulse irradiation level of the pulse train waveform. apparatus. (10) In the optical information recording apparatus according to (3) or (4), the state in which the irradiation level is changed by the irradiation level selecting means corresponds to the erase start head pulse irradiation level of the pulse train waveform. Information recording device. (11) In the optical information recording device of (3) or (4), the state of changing the irradiation level by the irradiation level selecting means is changed by the state transition signal or the transition rule. .

According to the optical information recording apparatus of the first aspect of the present invention, by configuring as described above, it becomes possible to arbitrarily set the frequency and duty of the pulse train waveform, so that a wide variety of information can be obtained. It is possible to cope with recording on a recording medium or recording linear velocity. Further, according to the optical information recording apparatus of the second aspect of the present invention, with the above configuration, the change timing of the optical modulation waveform is determined only by the modulation signal, and there is a skew between the supplied signals. Does not affect the optical waveform, an accurate emission waveform can be obtained, an accurate recording mark can be formed, and the pulse train frequency can be set arbitrarily according to the binarized signal. It is possible to support recording by a medium or recording linear velocity. Further, according to the optical information recording apparatus of claim 3 of the present invention, by being configured as described above, in addition to the effect of claim 2, the irradiation level of a predetermined pulse can be selected. Highly accurate recording mark formation control can be performed.

According to the optical information recording apparatus of the fourth aspect of the present invention, by being configured as described above, in addition to the same effect as the third aspect, the recording mark length or the recording mark length More precise recording mark formation control can be performed in consideration of the space length in the front and back. Further, according to the optical information recording apparatus of the fifth aspect of the present invention, by configuring as described above, in addition to the effect similar to the second or third aspect, some timing information is shared. Therefore, the memory capacity of the drive waveform generation information holding means can be reduced. Further, according to the optical information recording apparatus of the sixth aspect of the present invention, by configuring as described above, some timing information and irradiation level selection information can be made common,
The memory capacity of the drive waveform generation information holding means can be reduced. Further, according to the optical information recording apparatus of the seventh aspect of the present invention, with the configuration as described above, it is possible to generate an optical waveform most suitable for the recording linear velocity.

Further, according to the optical information recording apparatus of the eighth aspect of the present invention, by virtue of the above-mentioned constitution, it is possible to perform the recording mark formation control with higher precision with a simple constitution.
Further, according to the optical information recording apparatus of the ninth aspect of the present invention, by configuring as described above, it is possible to perform the recording mark formation control with higher accuracy with the same simple configuration. Further, according to the optical information recording apparatus of the tenth aspect of the present invention, by configuring as described above, it is possible to perform the recording mark formation control with higher accuracy with the same simple configuration. Further, according to the optical information recording apparatus of the eleventh aspect of the present invention, by configuring as described above, a pulse having a large influence on the formation of the recording mark depending on the information recording medium, the recording linear velocity and the like is multivalued. The level can be increased, and highly accurate recording mark formation control can be performed.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings. First, the overall configuration and operation outline of an information recording / reproducing apparatus, which is an embodiment of the optical information recording apparatus of the present invention, will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an information recording / reproducing apparatus which is an embodiment of the optical information recording apparatus of the present invention. In FIG.
The information recording medium 100 is an optical disc such as a CD-ROM or a DVD-ROM in which information to be reproduced is recorded in advance, or a CD-R or CD in which information is not recorded and a user can arbitrarily record new information. -RW, DVD-R, DVD-
It is an optical disk such as a RAM, MD, or MO.

The pickup 101 irradiates the information recording medium 100 with light emitted from a light source (for example, a semiconductor laser (LD)) 102 to record information, or receives reflected light from the information recording medium 100 and receives it. A light source 102, a light source driving unit (known in the art, not shown) for driving the light source 102, a light receiving unit 103 for receiving reflected light and converting it into a light receiving signal, and the like are arranged. .
The pickup 101 is also provided with a monitor light receiving unit (also known and not shown) that monitors a part of the emitted light of the light source 102, and the emitted light amount of the light source 102 is output based on the monitor signal which is the output thereof. Control fluctuations.

Further, a tilt detection light receiving section (also known, not shown) for detecting an inclination (referred to as “tilt”) of the information recording medium 100 with respect to the irradiation light may be arranged. Furthermore, in the case of an information recording / reproducing apparatus compatible with a plurality of types of information recording media in which different medium formats are defined (for example, both DVD and CD compatible devices), each information recording medium has a light source of a suitable wavelength. In some cases, a light receiving unit or a monitor light receiving unit for receiving the reflected light from the information recording medium at the time of emitting each light source may be separately provided.

The signal processing section 104 includes the pickup 101.
Light receiving signals from various light receiving units arranged at are input and various signal processing is performed. For example, control is performed such that information is reproduced from a light reception signal, or light is always irradiated within a predetermined error with respect to fluctuations such as surface wobbling and wobbling in the radial direction of the track due to rotation of the information recording medium 100 (focus servo). A servo error signal is generated from the received light signal for control and track servo control), and the pickup 101 is controlled according to the servo error signal. In addition, the information to be recorded is modulated according to a predetermined rule and output as a recording signal to the light source 102 (or the light source driving unit), or the light source 102.
Control the output light quantity of.

The rotation drive unit 105 is used for the information recording medium 100.
The signal processing unit 104 controls the rotation speed (spindle servo control). CLV
When the rotation control is performed, the rotation control signal embedded in the information recording medium 100 is detected via the pickup 101 to perform the rotation control with higher accuracy, and the rotation control is performed based on the rotation control signal. As the rotation control signal, for example, a synchronizing signal arranged at a predetermined interval in recorded information in a reproduction information recording medium or the like, or a wobble in which a recording track meanders at a predetermined frequency in a recordable information recording medium is used.

The controller 106 controls recording and reproduction information with the host computer and command communication to control the entire apparatus. The pickup 101 is movable in the radial direction of the information recording medium (this operation is called "seek operation").
The pickup 101 and the circuit board on which the signal processing unit 104 and the like are mounted are referred to as flexible print circuits (Flexible Print Circ).
It is generally connected by a board (or cable) called a unit (FPC) board (or cable), and the components mounted on the pickup 101 such as the light source 102 and the light receiving unit 103 should be mounted on this FPC board. There are also many.

Next, the internal structure and operation of the signal processing section 104 of the information recording / reproducing apparatus will be described. Figure 2
FIG. 3 is a block diagram showing an internal configuration of the signal processing unit 104 shown in FIG. 1. The signal processing unit 104 of the present embodiment uses two light sources LD1 and LD2 as the light source (LD) 102 in order to support information recording media of different formats.
And the light receiving portions PD1 to PD1 as the light receiving portion 103.
PD5 is provided, and a part of the irradiation light from the light sources LD1 and LD2 is monitored by the light receiving units PD2 and PD5, respectively.

The light receiving portion PD1 receives the reflected light from the information recording medium when the light source LD1 is irradiated, and the light receiving portion PD4 receives the reflected light from the information recording medium when the light source LD2 is irradiated. The light receiving unit PD3 is a light receiving unit for detecting the tilt amount. The light receiving parts PD1, PD3, and PD4 receive light by a divided light receiving element that is divided into a plurality of parts. Depending on the pickup, the light emitted from the light sources LD1 and LD2 may be monitored by the same light receiving section. Similarly, the light receiving unit that receives the reflected light from the information recording medium may be the same.

The light-receiving signal processing unit 2 includes light-receiving units PD1 and PD.
3 and the light reception signals output from the PD 4 are input, and processing such as offset adjustment and gain adjustment of each light reception signal is performed. The servo signal calculation processing section 13 generates a servo error signal from each light reception signal supplied from the light reception signal processing section 2.
At the same time, the servo error signal generated by performing the offset adjustment and the gain adjustment is supplied to the servo processor 14.
The RF selection unit 4 receives the light receiving signals output from the light receiving units PD1 and PD4, and selects or supplies signals necessary for a circuit in the subsequent stage by performing calculations such as partial addition and subtraction.

The wobble signal generator 6 detects wobbles preformatted on a recordable information recording medium. The wobble signal processing unit 15 extracts a binarized wobble signal from the signal output from the wobble signal generation unit 6 and supplies it to the WCK generation unit 17 and the rotation control unit 18.
Further, the wobbled address information is demodulated according to a predetermined rule for each information recording medium, and is supplied to the controller 19.

The RF signal processor / PLL unit 16 reproduces the reproduction RF input from the RF selector 4 by the RF signal processor.
A binarized RF signal is generated from the signal and demodulated according to the modulation method rule of the information recording medium being reproduced. PLL
The reproduction clock is extracted from the binarized RF signal by the unit (PLL circuit). The demodulated data is supplied to the controller 19. Further, the rotation control unit 1 extracts the rotation control signal by the synchronization signal inserted into the binarized RF signal at a predetermined interval.
Supply to 8. The rotation control unit 18 generates a spindle error signal for performing rotation control from a signal input from the wobble signal processing unit 15 or the RF signal processing unit / PLL unit 16, and supplies the spindle error signal to the servo processor 14. When the information recording medium is rotated at a constant angular velocity (CAV), it is based on a signal (also known and not shown) indicating a disk rotation output from a rotation control drive unit (known and not shown). To generate a spindle error signal.

The servo processor 14 is the controller 1
Based on the command from 9, the servo control signal is generated from various input servo error signals and output to the servo driver 20. The servo driver 20 generates a servo drive signal based on the input servo control signal. Each drive unit performs a servo control operation according to the supplied servo drive signal. Here, focus control, track control, seek control, spindle control, and tilt control are performed.

The WCK generator 17 generates the recording clock signal WCK based on the binarized wobble signal supplied from the wobble signal processor 15, and the LD modulation signal generator 10
And to each part of the controller 19. At the time of recording, generation of recording data is performed with reference to the recording clock signal WCK. At the time of recording, the recording data signal Wda is synchronized with the recording clock signal WCK from the controller 19.
ta is supplied to the LD modulation signal generation unit 10. Information to be recorded in the recording data signal Wdata is modulated according to a predetermined rule.

The LD modulation signal generator 10 is an LD for modulating the light source LD1 or the light source LD2 from the recording clock signal WCK input from the WCK generator 17 and the recording data signal Wdata input from the controller 19.
A modulation signal is generated and supplied to the LD drive unit 12. The LD control unit 9 inputs the monitor light receiving signal from the light receiving unit PD2 or the light receiving unit PD5, and sends it to the LD driving unit 12 based on the monitor light receiving signal so that the light emission amounts of the light sources LD1 and LD2 become desired values. An LD control signal is supplied to the so-called APC (Automatic Power).
Control) is performed). LD drive unit 12 is L
Based on the LD control signal input from the D control unit 9 and the LD modulation signal input from the LD modulation signal generation unit 10, the light source LD1 or the light source LD2 is current-driven to emit light. In addition, the controller 19 outputs control signals for each unit.

Next, the LD controller 9 and the LD driver 1
Two detailed embodiments will be described. FIG. 3 is a configuration diagram of an LD drive integrated circuit 1 in which the LD control unit 9 and the LD drive unit 12 shown in FIG. 2 are integrated. FIG. 4 shows the LD shown in FIG.
FIG. 3 is a waveform chart showing an example of output signals of respective parts of the drive integrated circuit 1. The LD drive integrated circuit 1 shown in FIG. On the other hand, LD drive integrated circuit 1
LD modulation signal generator 1 for supplying LD modulation signal WSP to
0 is mounted on the circuit board together with other signal processing units, and the signal line connecting them is transmitted on the FPC board.

Further, the LD modulation signal generator 10 uses the recording clock signal WCK as a reference to generate the recording data signal Wdat.
An LD modulation signal WSP (f) and a state signal STEN (e-1) as shown in FIG. 4 are generated from a. In FIG. 4, the delay of the signals WSP and STEN with respect to the recording data Wdata is disregarded for simplicity of illustration (usually, a predetermined clock is delayed for convenience of the generation circuit).
At this time, it is assumed that the LD modulation signal WSP has been subjected to optimum pulse width control for a required information recording medium. Furthermore, the command signal STCMD is also generated.

The LD drive integrated circuit 1 converts the state signal STEN and the command signal STCMD supplied from the LD modulation signal generation unit 10 into a mode control signal SeqMode which indicates the LD irradiation level and the irradiation mode 22 (CMDDecoder) 22. And LD
LD modulation signal WSP supplied from modulation signal generation unit 10
And state signal STEN and mode control signal SeqMo
A sequencer (Sequencer) 21 that controls the LD irradiation level based on de, and a modulator (Data-Modulation) that generates an LD modulation current Imod based on the modulation data DmodL and DmodH and the modulation signal MOD supplied from the sequencer 21. Equipped with 23.

A PD amplifier section (PD-AM) for inputting a monitor light receiving signal from a monitor light receiving section for monitoring a part of the light emitted from the light source to perform offset adjustment and gain adjustment.
P) 26 and the monitor signal Imon supplied from the PD amplifier unit 26 are generated from the target level signal Dtarget supplied from the sequencer 21.
Bias current control unit (Bias-Control) 27 that controls the bias current Iapc so as to match with et.
And the bias current I output from the bias current controller 27
bias current selection unit (MUX) 29 that selects bias and bias current Iext supplied from the outside to output current Ibias, and differential quantum of the light source LD (light source LD1 or light source LD2) driven from the monitor signal Imon. A differential quantum efficiency control unit (η-Control) 28 that detects the efficiency η and controls the scale Scale of the LD modulation current according to the detection result is also provided.

Further, the high frequency superimposed signal and the offset current Ihfmofs applied to the bias current at the time of high frequency superimposing
A high frequency modulator (HF-Modular
n) 30, the bias current Ibias and the modulation current Imo
High-frequency superposition offset current Ihfmofs by adding d
And a light source LD1 or a light source LD that amplifies the current supplied from the current adder 24
A current drive unit 25 that supplies a drive current ILD of 2 and a control unit 33 that receives a control command supplied from the controller 19 (or via the LD modulation signal generation unit 10) and supplies a control signal to each unit. There is.

The signal waveforms of the respective parts shown in FIG. 4 are examples, and the information recording medium assumed here is a phase change type recording medium (for example, an optical disk such as a CD-RW or a DVD-RW).
Then, based on the recording clock signal WCK (a) and the recording data signal Wdata (b), the light source LD is caused to emit light with the light modulation waveform as shown in FIG. Form. In a phase change type information recording medium, a recording mark is generally formed by three-valued multi-pulses of write power Pw, erase power Pe, and bottom power Pb. At this time, accurate recording is performed by accurately controlling the recording power level and the pulse width / pulse interval of each pulse. Further, in the present embodiment, FIG.
As shown by broken line frames (i), (ii), and (iii), the power of the first pulse, the last pulse, or the last bottom pulse (referred to as "cooling pulse") can be set.

Normally, when a mark is formed depending on the information recording medium or its recording linear velocity, the edge of the mark may be thermally influenced on the medium by the adjacent space length, and the edge of the mark may be variously changed depending on the adjacent space length. is there. In order to avoid this, conventionally, each pulse width of the optical modulation waveform is changed in consideration of the adjacent space length. If the power can be changed in consideration of the adjacent space lengths as in the present embodiment, the amount of heat applied to the medium is equivalent to pulse width correction according to the adjacent space lengths. , Which is substantially equivalent to subdividing the pulse width control resolution, and is suitable for high-speed recording.

Before describing each part in detail, the light source LD to be driven / controlled will be described. FIG. 8 is a diagram showing an example of drive current-optical output characteristics. Usually light source L
The optical output Po with respect to the drive current ILD of D can be approximated based on the equation shown below. Here, η: differential quantum efficiency, Ith: threshold current.

[0041]

[Equation 1] Po = η · (ILD-Ith)

In order to obtain the desired optical modulation waveform P ((b) in FIG. 8), when the LD drive current ILD is the sum of the bias current Ib and the modulation current Im (Ib + Im), the bias current Ib is the threshold current. Is almost equal to Ith, and the modulation current Im
May drive a current such that P = η · Im as shown in FIG. However, in general, this threshold current Ith
The differential quantum efficiency η varies not only with variations among individuals but also with temperature changes. Therefore, in order to always obtain a desired optical modulation waveform P, the bias current Ib varies with the variation of the threshold current Ith and the differential quantum efficiency η. It is desirable to control the modulation current Im. For example, when the threshold current fluctuates to Ith ′ and the differential quantum efficiency fluctuates to η ′ as shown in (ii) of FIG. 8, in order to obtain a desired optical modulation waveform P, the bias current Ib ′ is changed to Ith ′, The modulation current Im ′ may be controlled so that P = η ′ · Im ′ as shown in FIG.

In the LD drive integrated circuit 1 shown in FIG. 3, the bias current control unit 27 mainly performs the bias current control function, and the differential quantum efficiency control unit 28 mainly performs the modulation current control function.

The operation and detailed configuration of each part of the LD drive integrated circuit 1 shown in FIG. 3 will be described below. [Sequencer] The sequencer 21 is an LD modulation signal WSP.
The LD irradiation level of the light source is controlled based on the state signal STEN. FIG. 5 is a state transition diagram of the sequencer 21 shown in FIG. Each state corresponds to the irradiation level of the light source LD, and each state machine of SMa and SMb operates independently. Then, the current states state0 and stat of the state machines SMa and SMb, respectively.
The modulated data DmodL and DmodH are output according to e1.

That is, the modulation data corresponding to each state is set in advance, and the modulation data corresponding to the current state of each state machine is selected and output. Further, the LD modulation signal WSP is output as the modulation signal MOD during recording, and the low signal is output during reproduction.
In FIG. 3, the modulation signal MOD is supplied to the modulation unit 23 via the multiplexer MUX65,
Here, it is assumed that the MUX 65 selectively outputs the modulation signal MOD.

In the modulation section 23 in the next stage, this modulated signal MO
Since the modulation data DmodL is selected when D is low, and the modulation data DmodH is selected when D is high, each state in SMa is the LD modulation signal WSP.
Corresponds to the illumination level when it is low, and each state in SMb corresponds to the illumination level when WSP is high. For example, the modulation signal M at state0 = SPb
When OD = Low, the irradiation level of the light source LD is the bottom power Pb, and when state1 = SPmp and the modulation signal MOD = High (High), the irradiation level of the light source LD is the write power Pw.

The state machine SMa is adapted to make a state transition at the rising edge of the LD modulation signal WSP, and the state machine SMb is adapted to make a state transition at the falling edge of the LD modulation signal WSP. That is,
Since the state transition (change of the modulation data) is performed when the output modulation data is not selected for output, the irradiation level of the light source LD does not change even when the modulation data changes.

Further, the first pulse Ptp and the last pulse Pl
Each modulation data corresponding to p or the final bottom pulse power Pcl can be dynamically changed according to a recording data pattern or the like. That is, a plurality of preset modulation data (for example, Ptp has four values, Ptp0 to 3)
Is selected by the power selection signal PwrSel supplied from the command decoder 22. The power level to be selected is designated by the command signal STCMD, and the command decoder 22 outputs the power selection signal PwrSel.
Is converted to.

Next, the transition condition of each state machine will be described. (G-1) and (g-2) of FIG. 4 are examples of state transitions, and the change time of the LD modulation signal WSP ((f) of FIG. 4) is set to t0 to t27 as illustrated. The state signal STEN2 is the LD modulation signal W
It is re-taken at the trailing edge of SP, and the state machine SMa makes state transitions accordingly. As a result, a stable operation can be performed because the data definite time of the state signal STEN2 can be sufficiently secured with respect to the rising of WSP which is the reference of the state transition in the state machine SMa.

* State machine SMa Unless otherwise specified, the state machine SMa transits in synchronization with the rise of the LD modulation signal WSP. {State SPr} Initial state. During playback (write signal R / W =
0 (at the time of Read) stays here. Start recording (R
/ W rises) and transits to the state Pe. This transition is LD
You may make it not synchronize with the modulation signal WSP. {State SPe} State signal STEN2 = High (High
In h), transition to the next state. Normally, the state transits to the state SPb (for example, time t3), but it may transit to the state SPcl due to a special condition (A) described later (for example, time t25). Also, at the end of recording (R / W fall), the status SP
Transition to r.

{State SPb} STEN2 = Low (Lo
Transition to the next state in w). In the waveform example of FIG. 4, the state SP
Transition to cl (for example, time t7). Further, depending on the mode control signal SeqMode, the state transits to the state SPe. {State SPcl} Transition to the state Pe (for example, time t
9). In addition, the return to the state SPr (reproduction mode) is R
After / W = Raed, the state may be returned to the state SPe first, and then the transition may be performed, or R / W = Read may be forcibly transitioned.

* State machine SMb Unless otherwise specified, the state machine SMb transits in synchronization with the trailing edge of the LD modulation signal WSP. {State SPe} Initial state. When the state signal STEN = High (High), the state transits to the state SPtp (for example, time t2). {State SPtp} State signal STEN = High (High
At the time of h), it transits to the state SPmp (time t4). Further, when the state signal STEN = low (Low), the state transits to the state SPlp (time t18). The state may change to SPe depending on a special condition (A) described later.

{State SPmp} State signal STEN =
When it is low, it transits to the state SPlp (time t
6). If the state signal STEN = High, stay here. {State SPlp} Transition to the state SPe (time t8).
Further, in this embodiment, the transition mode of the state machine can be dynamically changed via the command decoder 22. For example, in the case of generating a waveform (Ptp → Pcl) surrounded by the one-dot chain line frame (A) in FIG. 4, time t (A)
At this time, the mode may be designated and the above state machine may be transitioned under the special condition (A). The initialization of each state machine may be performed by issuing a command via the control unit 33. This is effective, for example, when forcibly returning to the initial state.

[Command Decoder] Command Decoder 2
2 is a state signal STEN and a command signal STCMD
And are converted into a mode control signal SeqMode that specifies the irradiation level and irradiation mode of the light source LD. The mode control signal SeqMode includes the power selection signal P described above.
It includes transition mode signals for wrSel and state machines. The command decoder 22 uses the state signal STEN as a clock and the command signal STCMD as data to fetch data at both edges of the state signal STEN.

In the present embodiment, the command signal STCMD
Is set to 3 bits (Bit), and the final pulse power selection signal PEP (2bi is generated at the rising edge of the state signal STEN.
t) and CL pulse transition mode signal CLMode (1bi
t), the leading pulse power selection signal PTP (2 bits) is fetched at the falling edge of the state signal STEN, and is supplied to the sequencer 21. The final pulse power selection signal PEP selects the final pulse power Plp and the cooling pulse power Pcl, and the CL pulse transition mode signal CLMode specifies the mode of the special transition condition (A). Also, the head pulse power selection signal PT
P selects the head pulse power Ptp. These mode control signals SeqMode may be determined not only according to the distribution of this embodiment but also suitable for a desired optical waveform.

[Modulation Section] The modulation section 23 is a sequencer 21.
The LD modulation current Imod is generated based on the modulation data DmodL and DmodH and the modulation signal MOD supplied from. The PbDAC 40 is a current output DAC (D / A converter) that supplies a current based on the modulation data DmodL.
The PtpDAC 41 is a current output DAC that supplies a current based on the modulation data DmodH. The switch 42 receives the PbDAC 40 or the PtpDAC 4 according to the selection signal supplied from the MUX 65 (the modulation signal MOD, that is, the LD modulation signal WSP is supplied during recording).
The output current of 1 is selected and the LD modulation current Imod is output. Here, the selection signal, that is, the modulation signal MOD is high (H
If it is high, the output of PtpDAC41 is changed to low (Lo).
If w), select the output of PbDAC40.

In addition, PbDAC40 and PtpDAC41
Full scale Iscl is a scale DAC (Scale
DAC 43, which is set according to the scale signal Scale supplied from the differential quantum efficiency control unit 28. Further, the full scale Ifull of the scale DAC 43 is supplied from ηREF and is used as the light source LD.
It may be determined from the differential quantum efficiency of. Full scale Isc
A method of calculating / setting l will be described later. Therefore,
The output currents I0 and I1 of the PbDAC 40 and the PtpDAC 41 are obtained by the calculation based on the formulas shown in the following formulas 2 and 3. Here, PbDAC40, PtpD
AC41 and scale DAC43 are 8 bits
It is DAC.

[0058]

## EQU00002 ## I0 = (DmodL / 255) * (Scale
/ 255) * Ifull

[0059]

(3) I1 = (DmodH / 255) * (Scale
/ 255) * Ifull

Further, as described above, the modulation data Dmod
Since the change timing of L and DmodH is not selected by the switch 42, if the response speed of the PbDAC 40 and PtpDAC 41 is sufficiently high, PbDA
The changes in the output currents I0 and I1 of the C40 and the PtpDAC 41 are also performed while the switch 42 is not selected, and the change in the modulation current Imod is determined only by the change timing of the modulation signal MOD.

FIG. 6 is a block diagram showing another example of the configuration of the modulator 23 shown in FIG. Modulation data (PrData to PlpData) corresponding to each state of the state machines SMa and SMb is supplied from the sequencer 21 and PrDAC80a, PeDAC80b, PbDAC.
80c, PclDAC80d and PeDAC81a, P
tpDAC81b, PmpDAC81c, PlpDAC
81d outputs currents I0a to I0d and I1a to I1d, respectively, based on the modulation data. The switch 82 has currents I0a to I0d according to the signal state0 indicating the current state of the state machine SMa.
One of them is selectively output. Similarly, the switch 83 uses the signal sta indicating the current state of the state machine SMb.
One of the currents I1a to I1d is selectively output according to te1.

The switch 82 is similar to that of FIG.
According to the selection signal supplied from X65, the current I0 or the current I1 supplied from the switch 82 and the switch 83 is selected and the LD modulation current Imod is output. Further, the scale DAC 43 is also the PrDAC 80 as in FIG.
a, PeDAC80b, PbDAC80c, PclDA
C80d, PeDAC81a, PtpDAC81b,
The full scale of PmpDAC81c and PlpDAC81d is determined. According to this embodiment, switch 82 or switch 83 when not selected by switch 84.
The output currents I0 and I1 are also changed while the switch 84 is not selected, and the change in the modulation current Imod is caused only by the change timing of the modulation signal MOD as in the embodiment of FIG. Decided.

The changing speed of the output currents I0 and I1 is determined by the switching speed of the switches 82 and 83, and Pr
DAC80a, PeDAC80b, PbDAC80c,
PclDAC80d, PeDAC81a, PtpDA
The response speed of C81b, PmpDAC81c, and PlpDAC81d does not need to be high. Therefore, high-speed DA
This is effective when it is difficult to realize C. Since the output currents I0b and I1a output the same current, these D
AC may be shared. Further, the PrDAC 80a plays back the PeDAC 80b, PbDAC 80c, Pc during playback.
Since the lDAC80d is used for recording, P
rDAC80a to PeDAC80b, PbDAC80
It may be shared with one of c and PclDAC80d.

FIG. 11 is a block diagram showing still another example of the configuration of the modulation section 23 shown in FIG. 12 is shown in FIG.
FIG. 3 is a waveform diagram showing output signals of respective parts of FIG. As shown in FIG. 11, the sequencer 21 outputs the modulation data DmodL and DmodL.
In addition to modH, addition data exDataL and exDa
taH is supplied. These addition data are also output according to the state machines SMa and SMb. Pb + DAC
90, PbDAC91, Pt + DAC92, PtDAC
93 outputs a current based on those data. Adders 94 and 95 are Pb + DAC 90 and PbDA, respectively.
Addition of output current of C91, Pt + DAC92 and PtDA
The output current of C93 is added to obtain the currents I0 and I, respectively.
1 is output.

The switch 96 selects the output currents I0 and I1 according to the modulation signal MOD and outputs the LD modulation current Imod. Further, the scale DAC 43 is the same as in FIG. 3 except for Pb + DAC90, PbDAC91, Pt + DAC9.
2. Determine the full scale of PtDAC93. Pb + D
Since the AC 90 and Pt + DAC 92 only output the addition amount, it is not necessary to make the dynamic range large, and the full scale thereof may be made smaller than the full scale of PbDAC 91 and PtDAC 93 to reduce the number of addition data bits. By doing so, the number of bits of the register that holds the data can be reduced.

[Current Driver] The current driver 25 amplifies the current supplied from the current adder 24 and supplies the drive current ILD for the light source LD1 or the light source LD2. The switch 44 supplies the input current to the current amplifier 45 or 46 according to the selection signal IoutSel. Current amplifier 45
Reference numerals 46 and 46 amplify the current supplied from the switch 44 with a predetermined amplification factor Ai to generate the light source LD1 or the light source LD2.
Drive current ILD is supplied to. Therefore, at this time, L
The D drive current ILD is obtained by calculation based on the equation shown in the following Expression 4.

[0067]

## EQU00004 ## ILD = Ai * (Ibias + Imod-Ih
fmofs)

However, Ihfmofs becomes 0 when high frequency superimposition is not performed. In addition, the offset current Ihfmof
s may be turned off during high frequency superposition, and may be added when high frequency superposition is not performed. Also, Ib = Ai * (Ibi
as-Ihfmofs), Im = Ai * Imod,
As shown in FIG. 8, if Ib is controlled to be equal to the threshold current Ith, Im, that is, the modulation current Imod.
Has a waveform proportional to the optical waveform. In this embodiment, it is not assumed that the light sources LD1 and LD2 are simultaneously irradiated.

As can be seen from the above, the pulse width of the light modulation waveform of the light source LD is determined only by the modulation signal WSP,
Between two signals output from the LD modulation signal generator 10 (WS
Even if there is a skew in (P, STEN), it does not affect the optical waveform and an accurate recording mark can be formed. Therefore, the LD modulation signal generation unit 10 may be configured by an integrated circuit different from the LD drive unit 12, and it becomes possible to select a semiconductor process that suits the desired circuit characteristics.
It is possible to construct a device that matches the cost and performance.
That is, a fine CMOS process is suitable because high speed operation and high integration are required in the LD modulation signal generation unit.

On the other hand, since an LD having an operating voltage of about 1 to several V is connected to the LD driver, a high breakdown voltage process (for example, 5 V or 3.3 V) is required. Normal,
It is difficult to achieve a high breakdown voltage in a fine CMOS process (for example, in the 0.18 μm CMOS process, 1.
However, according to the present embodiment, each can be configured by a suitable process.

[PD Amplifier Section] The PD amplifier section 26 inputs a monitor light receiving signal from a monitor light receiving section for monitoring a part of the light emitted from the light source and performs offset adjustment and gain adjustment. The monitor light receiving unit includes a single light receiving element (PD: Pho
to detector, etc.), a type in which a monitor light receiving signal is output as a current, and a type in which a current-voltage converter is built in and a monitor light receiving signal is output as a voltage. In the present embodiment, either type can be used and is selected by the MUX 48. That is, in the case of the current output type, the input monitor light receiving signal is converted into a voltage by the current / voltage converter (I / V) 47, and in the case of the voltage output type, a signal not passing through the current / voltage converter 47 is selected. To do.

The adder 50 is for adjusting the offset of the monitor light-receiving signal, and is an offset DAC (Offse).
The offset voltage supplied from (tDAC) 49 is added or subtracted. Gain switching amplifier (X1 / X4 / X8 / X16
The AMP 51 performs gain adjustment by switching the gain of the offset-adjusted monitor light receiving signal in accordance with the gain switching signal PDGain (for example, four-step switching of 1/4/8/16 times). Generally, since the reproducing light amount and the recording light amount are largely different, it is advisable to switch the gain during recording / reproducing. The light receiving current Ipd of the PD is obtained by an operation based on the formula shown below, where α is the light utilization efficiency of the light source LD with respect to the emitted light Po and S is the light receiving sensitivity of the light receiving unit PD.

[0073]

[Equation 5] Ipd = α · S · Po

If the conversion gain of the current-voltage converter (47 or the built-in monitor light receiving unit) is Giv, and the gain of the gain switching amplifier 51 is Gpd, the monitor signal Imon is based on the following equation (6). It is obtained by calculation.

[0075]

[Equation 6] Imon = Gpd · Giv · Ipd = Gpd ·
Kpd / Po

Here, Kpd = Giv · α · S.
The offset voltage supplied from the offset DAC 49 is omitted for convenience. When a monitor light receiving unit for monitoring the light emitted from the light sources LD1 and LD2 is separately provided,
It suffices to provide two inputs of the PD amplifier unit 26, input the monitor light receiving signal supplied from the monitor light receiving unit to each of them, and select the monitor light receiving signal corresponding to the illuminating light source LD.

[Bias Current Control Unit] The bias current control unit 27 supplies the monitor signal Imon supplied from the PD amplifier unit 26 to the reference signal Itage generated from the target level signal Dtarget supplied from the sequencer 21.
The bias current Iapc is controlled so as to match t.
In the present embodiment, the following three control methods can be selected.

(1) Average value control method The modulation data D is included in the two target level signals Dtarget.
The same data as modL and DmodH is supplied, and P-BD
The AC 52, the P-PDAC 53, and the switch 54 generate the reference signal Ittarget that is proportional to the amount of light emission. P-B
The operations of the DAC 52, the P-PDAC 53 and the switch 54 are the same as the operations of the PbDAC 40, PtpDAC 41 and the switch 42, respectively. Here, the emitted light amount Po
Let K be the proportional coefficient between the reference signal Ittarget and
The relationship shown in the following Expression 7 is obtained.

[0079]

[Equation 7] Target = K · Po

Further, the proportional coefficient K is converted into P-BDA by the bias scale DAC (BSscale DAC) 70.
It is determined by setting the scale of C52 and P-PDAC53, and is set so that K = Kpd in advance. Kpd is the emitted light P of the light source LD of the light receiving section PD to be used
Since this depends on the variations in the light utilization efficiency α and the light receiving sensitivity S with respect to o, it is preferable to make this setting during the initial adjustment. Further, the bias scale setting value BiasScale is changed according to the gain Gpd of the gain switching amplifier 51. Since the reference signal Ittarget indicates the target emission light quantity, the LD can be irradiated with the target irradiation light quantity if the monitor signal Imon that monitors the emission light quantity matches the reference signal Ittarget.

The error amplifier 55 outputs the reference signal Itage.
The difference signal between t and the monitor signal Imon is amplified and supplied to the next stage. S / H integrator (S / H Integra.) 56
Outputs the bias current Iapc by integrating the amplified difference signal supplied from the error amplifier 55. The S / H integrator 56 always performs the integration operation in this control method. Further, the control speed can be changed by the SRSel signal. This is the charge / discharge current to the integrator (eg,
This is performed by changing the output current of the error amplifier 55). This makes it possible to set the control speed to the optimum value during recording / reproduction. In addition, R-Cont
Sets the settable range of charge / discharge current.

FIG. 14 is a diagram showing an example of each signal waveform for explaining the operation of the bias current controller 27. In the figure, (a) is an optical waveform that is a light emission waveform, and (b) is a monitor signal Imon. It is assumed that the light receiving section PD used is band-limited. Also, the broken line portion in the figure indicates the average level. As shown in the figure, when the irradiation power or duty is changed, the average level changes. In this case, accurate control cannot be performed by the conventional method of performing error control with respect to a predetermined average value calculated in advance. Also,
(C) of the figure is the reference signal Ittarget, which has a waveform proportional to the irradiation waveform as described above. The broken line portion is the signal in the bias control band. By thus generating a reference signal proportional to the irradiation waveform and using this for error control, accurate bias control can be performed even when the average level changes due to irradiation power or duty change.

(2) Sample and Hold Control Method The S / H integrator 56 performs an integration operation at the time of sampling (for example, ApcSmp = High) by the ApcSmp signal to perform bias current control, and at the time of hold, a control value is used. A certain bias current Iapc is held.
Therefore, since the output of the error amplifier 55 is not integrated during the hold, the drift of the control value due to the circuit offset of the error amplifier 55 can be reduced. In addition, the reference signal It
The generation of the target may be performed in the same manner as described above, but a constant reference signal Ita corresponding to the target irradiation power at the time of sampling is generated.
It may be rget. In this embodiment, the ApcSmp signal is generated by the sequencer 21, and is generated by the LD modulation signal and the state signal (controlled by the state machine).

An example of this waveform is shown in FIG. Apc
High of the Smp signal indicates a sampling period, and low indicates a holding period. ApcSm
The rising edge of the p signal is synchronized with the rising edge of the LD modulation signal WSP with the state signal STEN2 = low when the state state0 = SPe. Further, the fall is performed at the next rise of the LD modulation signal WSP (state stat).
e0 = SPe, state signal STEN2 = High).
In this way, there is no need to add a new signal line. Others perform the same operation as the control method of (1).

(3) ACC (Automatic Cu)
rent control) control method In the present embodiment, ACC control can be performed without performing APC control. Bypassing the error amplifier 55,
The output of the P-BDAC 52 according to the data is output as the bias current Iapc. At this time, if the output of the P-BDAC 52 is held in the S / H integrator 56, the initial value of the integrator will change from this mode to another control mode ((1) or (2) above). ACC that was on hold
Since it becomes data, the bias current does not become discontinuous, and it is possible to prevent the light source LD from excessively emitting light or turning off when switching.

On the contrary, when switching from the APC control mode to this ACC mode, the value of the bias current Iapc may be monitored and acquired and set as ACC data. Switching to the control mode is AC
It is instructed by the CSel signal. In the present embodiment, the bias current Iext can be applied from the outside without using the bias current controller 27. Although not shown, the external bias current I at this time is the same as described above.
If ext is held in the S / H integrator 56, the transition can be surely and quickly performed when switching to the internal bias current control unit 27.

FIG. 7 is a block diagram showing another example of the configuration of the bias current controller 27 shown in FIG. The target level signal Dtarget2 is data generated by switching the above-described modulation data DmodL and DmodH with the modulation signal MOD, and is a bias DAC (BiasDAC) 7
The reference signal Itage which is the average value of the light emission amount by 1
generate t. Since the bias DAC 71 is intended to generate an average value of the light emission amount, the PbDAC of the modulator 23 is
40, PtpDAC41 high speed operation is not required. According to this embodiment, the configuration of the reference signal Ittarget generating unit can be simplified and the response speed of the DAC can be reduced, so that the chip size and current consumption can be reduced. The other blocks operate similarly to those shown in FIG. 3, and the control methods (1) to (3) can be similarly applied.

[Differential Quantum Efficiency Control Unit] The differential quantum efficiency control unit 28 detects the differential quantum efficiency η of the light source LD (light source LD1 or light source LD2) being driven, and detects the LD modulation current in accordance with the detection result. Control the Scale Scale.
This is performed by detecting the difference in the amount of irradiation light between two predetermined points, comparing the difference with the reference value ηtarget, and increasing or decreasing the scale Sacle value based on the comparison result. The sample-hold circuit (S / H) 57 outputs the monitor signal Imon at the time of the irradiation light amount (referred to as P1) serving as a reference to EtaSmp.
Sample / hold according to signal. The differentiator 58 is
Output of sample hold circuit 57 and monitor signal Imon
And generate a difference signal between and.

The etaref DAC 59 has a reference value ηta.
Output rget. The comparator (Comp) 61 compares the output of the differentiator 58 with the reference value ηtarget, and if the output of the differentiator 58 is smaller than the reference value ηtarget, the Up signal is counted, and if it is larger, the Down signal is counted (C).
output). The comparison timing of the comparator 61 is performed according to the CompCK signal, and CompC
Comparison starts at the rising edge of the K signal. The counter 62 increases or decreases the counter value according to the comparison result Up / Down signal output from the comparator 61. Update the counter value by Com
It is performed at the falling edge of the pCK signal. This count value is Scal
The signal is supplied to the modulator 23 as an e signal, and the amount of light emission is also increased / decreased as the Scale signal is increased / decreased. The initial value of the counter 62 is PSscale (initial value at recording) or RSc.
ale (initial value during reproduction) is set.

Although not shown, a means for averaging the count values may be provided, and the moving average value of the count values may be used as the Scale signal. In this way, averaging can prevent oscillation of the control value (Scale). Further, when the dead zone is provided in the comparator 61, and when the both are substantially the same, U
Even if neither p / Down signal is output, the same effect can be obtained. Further, the full scale of the etaref DAC 59 is set by the bias scale DAC 70. Output light amount Po of light source LD and monitor signal Im
The relational expression with “on” is expressed by the above-mentioned equation 6, and the coefficient Kpd changes depending on the variations in the light utilization efficiency α and the light receiving sensitivity S for the emitted light Po of the light source LD of the light receiving unit PD to be used.

That is, the reference value ηtarget also varies from device to device, but the bias scale DAC 70 sets
The variation can be absorbed by adjusting the full scale of the arefDAC 59. Therefore, naturally the reference value ηtarget is calculated according to the coefficient Kpd.
You may set it. It should be noted that the bias scale DAC 70, as described above, uses the reference signal Ita of the bias current controller 27.
Since rget is also adjusted, common adjustment can be performed and the adjustment process can be simplified.

Next, an example of the differential quantum efficiency control method will be described. The control method during the recording operation on the phase change recording medium,
A description will be given based on the waveform diagram of FIG. In this control method, as shown in the optical waveform of FIG. 4C, light is emitted at the power P2 for detecting η for a predetermined period in a long space (broken line portion (B)), and the S / H circuit 57 samples during this period ( The sample signal is (EtaSmp in (j)). Further, during the subsequent irradiation of the erase power P1, the comparator 61 compares it with the reference value ((k) CompCK in the figure). That is, the differential quantum efficiency η is detected from the difference between P1 and P2.

In general, a phase change recording medium such as a CD-RW hardly deteriorates the recording characteristics with respect to some fluctuation of erase power. Further, since the fluctuation of the differential quantum efficiency is mainly due to the temperature change, this control band may be slow and the frequency of light emission with this special power P2 may be small, so that this control method does not adversely affect the recording performance. .
Further, the control frequency may be increased by increasing the sampling frequency only when there is a possibility that the initial value Pscale of Scale is deviated, such as immediately after the start of recording. By doing so, it is possible to automatically control the fluctuation of the differential quantum efficiency and cause the LD to emit a desired amount of light without affecting the recording performance.

Further, the EtaSmp signal and the CompCK signal, which are the control signals, are set to L in the sequencer 21.
It can be generated from the D modulation signal and the state signal. The generation method will be described below. First, the LD modulation signal (WSP signal) and the state signal (STEN signal) are generated in accordance with the desired light emission timing of the η detection power P2, as shown by the portion surrounded by the one-dot chain line frame (C) in FIG. To do. (E-2) The STEN2 signal is generated from the WSP signal and the STEN signal, and similarly has a broken line. At this time, the state machines SMa and SMb of the sequencer 21 perform the following state transitions.

{State machine SMa} In the state SPe, the state signal STEN2 = Low and LD
If the modulation signal WSP ↑ (“↑” represents a rising edge) (time t13), the state transits to the state SPcl. At this time,
The modulation data corresponding to the final bottom pulse power Pcl is output for the power P2 (= Peta) for η detection for a predetermined period. That is, in this state (Peta), when the LD modulation signal WSP = low (Low), light is emitted with the power P2 for η detection for a predetermined period. Further, in accordance with this, the EtaSmp signal is set to high (sample). Then, at the next LD modulation signal WSP ↑, the state returns to the state SPe (time t1.
5). Also, CompCK according to the transition to this state
Is made high, and made low when the state transits to the state SPb next time. The rest is the same as usual.

{State machine SMb} LD modulation signal WSP ↓ ("↓" represents a falling edge) at time t12
Then, since the state signal STEN = low, the state remains in the state SPe. The same applies at time t14. Time t
The LD modulation signal WSP ↓ at 16 is the state signal STE
Since N = High, the state transits to the state Ptp. The rest is the same as usual.

[High Frequency Modulation Section] Generally, in the optical disk device, in order to suppress the noise of the light source due to the return light from the information medium, so-called high frequency superposition is performed in which the high frequency signal is modulated during reproduction. The high frequency modulator 30 generates a high frequency superimposed signal HFMOD and an offset current Ihfmofs to be applied to a bias current when the high frequency is superimposed. Further, in the present embodiment, the high frequency modulation itself is performed using the modulation unit 23, so the operation of the modulation unit 23 at the time of high frequency superposition will also be described. The VCO 64 is an oscillator that generates a signal HFMOD having a frequency according to the frequency setting signal output from the FreqDAC 63.

The MUX 65 selectively outputs the high frequency superposed signal HFMOD and the modulation signal MOD output from the sequencer 21 in accordance with the HF-ON signal, and supplies it to the modulator 23. Since the high frequency superimposition will be explained here,
It is assumed that the OD signal is selected. In addition, HFBDAC
The offset current Ihfmofs to be added is generated by the 66 and the buffer amplifier 67, and the presence or absence of the application is set by the switch 68. Furthermore, when the VCO 64 does not perform high frequency superimposition (instructed by HF-ON), it is possible to suppress unnecessary power consumption by stopping oscillation. Modulator 2
3 operates as follows during high frequency superposition.

The modulation data DmodL and DmodH are supplied with data corresponding to the bottom level and the top level, respectively, and the PbDAC 40 and PtpDAC 41 are respectively set to I
Output btm and Itop. The degree of modulation can be changed by changing the modulation data. Then, the switch 42 performs the modulation current Im according to the high frequency superimposed signal HFMOD.
od is generated.

The LD drive current is obtained by the calculation based on the formula shown in the above equation 4, and the light modulation waveform is as shown in the diagram in FIG. 9 (in FIG. 9, for convenience, the amplification factor Ai of the current drive unit is shown.
Is omitted). Then, the bias current is controlled so that the average light amount Pavg becomes the target light amount Ptarget. Also, in the same way as described above, PbDAC 40 and Ptp
The full scale of the DAC 41 is set by the Scale signal, and if the differential quantum efficiency control unit 28 does not perform the control operation during reproduction, the initial value RSscale of the Scale signal during reproduction is given to be constant.

[DC / DC Converter] The DC / DC converter 32 converts the power supply voltage supplied to the LD drive integrated circuit 1 into the internal power supply voltage of the integrated circuit and supplies it to each unit. The internal power supply voltage value is set by the PwrReg signal. To operate the LD drive integrated circuit 1 at high speed,
It is desirable to realize it by a C-MOS fine process and operate it near the allowable voltage of the process. Further, the light source LD to be driven usually has an operating voltage of 2 to 3V, and a power source voltage of 3 to 4V is optimal for the LD driving section. This is because if it is larger than this, power consumption increases and heat generation also increases. To satisfy these conditions, for example, 0.35
It is advisable to operate with a power supply voltage of 3 to 4 V by using the um C-MOS process.

However, this optimum voltage may not be supplied to the information recording / reproducing apparatus (for example, 5 V and 1).
Only 2V is supplied). Therefore, it is necessary to separately convert the voltage to generate and supply the voltage, but the number of power supply lines supplied via the FCP substrate increases. Further, it is difficult to provide a voltage conversion unit in the pickup unit in terms of space for a pickup that is desired to be downsized. On the other hand, although the operating speed is slow, it is possible to easily mount a 5V withstand voltage transistor without increasing the cost, and this transistor is sufficient to form a voltage conversion unit.

Therefore, as in this embodiment, the voltage converter (DC / DC converter 32) is replaced by the LD drive integrated circuit 1.
The above-mentioned problems can be solved by incorporating the same in the. Furthermore, if a DC / DC converter (so-called switching regulator) is used as the voltage conversion unit, conversion loss can be reduced, and power consumption and heat generation amount can be reduced. Further, the DC / DC converter 32 is Pwr.
Since the internal power supply voltage value can be set by the Reg signal, the optimum power supply voltage can be set. DC
The / DC converter 31 is a voltage conversion unit for an input / output interface with the outside. As a result, it is possible to cope with various interface voltages without increasing the power supply lines of the FPC board.

In the above description, the operation for outputting the optical waveform of FIG. 4C has been described.
Other optical waveforms can be output by changing EN, set value, or the like. FIG. 10 is a waveform diagram showing an example of another output signal. As shown in FIG. 10, in order to perform the edge position control after the recording mark, the control of the final pulse power Plp and the cooling pulse power Pcl is not added, but the leading power Pep of the erase (the broken line portion ( iv)) to implement a method of adding control to pulse width control. LD modulation signal WSP, state signal ST
EN is given as shown in FIG. The only difference from the case of FIG. 4 is the fall timing of the state signal STEN. Further, the state machines SMa and SMb can be dealt with by only partially changing the transition condition.

Therefore, it is sufficient to add a condition by the optical waveform mode setting to the transition condition. That is, in the state machine SMa shown in FIG.
Alternatively, the transition of (b) may be performed. The irradiation power Pep corresponds to the state SPlp. In this way, the irradiation power corresponding to each state of the state machine,
Various optical waveforms can be generated by changing the transition condition.

Next, the LD modulation signal generator 10 will be described in detail. FIG. 15 shows the LD modulation signal generator 10
It is a figure which shows the structure of. The LD modulation signal generation unit 10 generates a clock signal PCK that is n times the recording clock signal WCK.
2 and a PLL unit 110 that generates a plurality of clock signals having phases different from the clock signal PCK by a predetermined amount, and FIG.
Recording data signal Wd supplied from the controller 19 of
run length signal Le by detecting the run length of ata
Run length detection unit (RunLength Det.) 1 that supplies n0 to Len2 and outputs a delayed recording data signal dWdata obtained by delaying a recording data signal of a predetermined amount.
11 and drive waveform generation information, and a drive waveform generation information holding unit (Strategy Memory) 112 that outputs information corresponding to the run length signals Len0 to Len2 in accordance with the delay recording data signal dWdata.
Is equipped with.

Further, a timing signal generating section 113 for generating a modulation timing signal from the drive waveform generating information output from the drive waveform generating information holding section 112, and an LD modulation from the modulation timing signal generated by the timing signal generating section 113. The state signal STE is generated from the modulation signal generation unit 114 that generates the signal WSP and the modulation timing signal that is also generated by the timing signal generation unit 113.
A state signal generator (STEN Ge) that generates N
n. ) 115 and the command waveform STCMD from the drive waveform generation information output from the drive waveform generation information holding unit 112.
State command generation unit (STCmd Ge
n. ) 116 and a sample signal generator (Sample Timing G) that generates a sample signal for APC control of a sample hold system from the recording data signal Wdata.
en. ) 117, and a control unit 118 that receives a control command supplied from the controller 19 of FIG. 2 and supplies a control signal to each unit.

Next, the detailed internal structure and operation of each section of the LD modulation signal generation section 10 shown in FIG. 15 will be described. [PLL] The PLL unit 110 outputs the recording clock signal WCK.
To generate a clock signal PCK that is multiplied by n, and generate a plurality of clock signals (in this embodiment, eight clock signals CK0 to CK7, and CK0 is the clock signal PCK) that are different in phase from the clock signal PCK by a predetermined amount. To generate. It also generates the recording channel clock signal CKch.

M divider (1 / M) 1 in PLL section 110
20, phase comparator (PC) 121, loop filter (F
The filter 122, the oscillator (VCO) 123, and the N frequency divider (1 / N) 124 are PLLs (Phase Locs).
ed loop) circuit. The operation of each of the above parts is similar to that of a normal PLL circuit, and therefore detailed description thereof is omitted. The M divider 120 divides the recording clock signal WCK by M. The frequency division ratio 1 / M can be set (for example, M
= 2, 4), which corresponds to the case where the recording clock signal WCK is supplied as a signal obtained by dividing the recording channel clock signal CKch. Therefore, the generation of noise can be reduced by lowering the frequency of the recording clock signal WCK for transfer.

The oscillator 123 generates m clock signals having different phases by a predetermined amount (in this embodiment, eight clocks CK0 to CK7 (m = 8), and CK0 is PCK). This is composed of, for example, a ring oscillator. The N divider 124 divides one clock signal (for example, CK0) output from the oscillator 123 by N. The frequency division ratio 1 / N can be set, and N / M is a clock signal PCK that is n times the recording clock signal WCK.
Becomes a multiplication number n. The M / N frequency divider 125 frequency-divides the clock signal PCK multiplied by n by M / N to generate a recording channel clock signal CKch, which is supplied to each unit.
As will be described later, the LD modulation signal WSP is the clock signal C.
It is generated based on K0 to CK7. That is, division ratio 1
LD modulation signal WS by setting / N, 1 / M
The pulse width setting resolution of P can be set.

For example, the supplied recording clock signal WC
If K is transferred at the same frequency as the recording channel clock CKch and M = 4 and N = 16 are set, the clock signal PCK has a frequency that is four times the channel clock signal CKch, and the LD modulation signal WSP has the channel clock. It can be generated with a pulse width setting resolution of 1/32 (= m · M / N) with respect to the signal CKch. Hereinafter, this will be referred to as a pulse width setting step (also simply referred to as a step). In the above example, 32 steps correspond to one channel clock cycle.

[Run Length Detecting Section] The run length detecting section 111 detects the run length of the recording data signal Wdata supplied from the controller 19 of FIG. 2 and supplies the run length signals Len0 to Len2. The recording data signal Wdata is NRZI (Non Return).
It is assumed that a high (H) section represents a recording mark and a low (L) section represents a space in a to-Zero Inverted binary signal. That is, the run length detection unit 1
Reference numeral 11 detects the mark length and space length of the recorded data. Here, Len1 supplies the mark length, Len0 supplies the immediately preceding space length, and Len2 supplies the immediately following space length.

Further, the run length detecting section 111 is constructed according to the minimum and maximum run lengths of the recording data signal to be applied. In this embodiment, the DVD format recording medium (D
Assuming application to an optical information recording device for recording information on an optical disk such as VD + RW, DVD-R, DVD-RAM, etc., the recording data signal Wdata will be described assuming a signal subjected to EFM + modulation. That is, the run length is 3T to 11T and 14T (T is the channel clock period). Further, the delay recording data signal dWdata is delayed by delaying the recording data by a predetermined amount in consideration of the predetermined time required to detect the run length and each circuit delay time.
Is output.

FIG. 16 is a diagram showing a detailed internal configuration example of the run-length detector 111. In addition, FIG.
7 is a waveform chart of a signal output by each unit in the run length detection unit 111 shown in FIG. Counter 1
40 counts and outputs the run length (high level section and low level section) of the recording data signal Wdata ((b) of FIG. 17) by the recording channel clock signal CKch ((a) of FIG. 17). : (C) of the same figure. The run length data counted by the counter 140 is temporarily held in the FIFO 143 once. The delay circuit (Delay) 141 is composed of a shift register or the like, and outputs the recording data signal Wdata by a predetermined amount (dl).
y) Delayed delayed recording data signal dWdata (FIG. 1)
7 (d)) is output. Further, the FIFO control unit (F
IFO Ctrl) 142.

The FIFO control unit 142 has a FIFO 143.
It supplies write / read control and control signals for each part.
The register (Reg) 144 holds and outputs the run length data read from the FIFO 143 (Len).
0, Len1, Len2). The read timing of the FIFO 143 (holding timing of the register 144) is set so that it coincides with the delayed recording data signal dWdata.
It is determined by the control signal supplied from the O control unit 142. That is, as shown in FIG. 17, the mark length Len1, the immediately preceding space length Len0, and the immediately following space length Len2 are matched with the delayed recording data signal dWdata (or drive waveform generation information (f) converted by Len0 to Len2). To match). The delay amount d
The sizes of ly and the FIFO 143 may be determined in consideration of the minimum / maximum run length of the recording data Wdata and each circuit delay so that the empty or full of the FIFO does not occur.

[Driving Waveform Generation Information Holding Unit] The driving waveform generation information holding unit 112 stores driving waveform generation information, and stores information corresponding to the run length signals Len0 to Len2 in the delay recording data signal dWdata. Output together. FIG. 18 is a timing chart showing the relationship between the drive waveform generation information and the optical waveform in this embodiment. FIG. 19 is a list showing a combination example of drive waveform generation information for each of a plurality of timing information.

The drive waveform generation information is composed of the irradiation level change timing of the optical waveform, that is, the timing information indicating the change timing of the LD modulation signal WSP and the command information transferred as the command signal STCMD such as the LD irradiation level. This timing information is represented by the pulse width setting step number, and each timing information (TSS, T
The change timing of the LD modulation signal WSP is determined by accumulating SP, ..., From the reference time (for example, the rising edge of the delayed recording data). NMP is the number of times TMS and TMP are repeated. In this way, the multi-pulse cycle and duty can be set arbitrarily.

Further, a suitable optical waveform may differ depending on the type of the information recording medium and the recording linear velocity. For example, when performing high-speed recording, the transit time of the irradiation beam on the information recording medium is shortened, so the amount of energy applied to the information recording medium is reduced, and the amount of heat required to form a recording mark is insufficient. For accurate recording, recording may be performed with a pulse train having a very narrow pulse width, but for that purpose, high laser power is required. Therefore, it is advisable to reduce the frequency of the multi-pulse train and record with low laser power. On the other hand, when low-speed recording is performed on an information recording medium having high recording sensitivity for high-speed recording, the amount of heat becomes excessive and accurate recording marks cannot be formed. Therefore, it is advisable to increase the frequency of the multi-pulse train for recording. In this way, by changing the timing information and the number of pulse repetitions according to the type of recording linear velocity and changing the frequency and duty of the multi-pulse, it is possible to generate the optimum optical waveform for the recording linear velocity. become.

In the present embodiment, the rising edge (a) and the falling edge (b) of the final pulse are set independently instead of being accumulated from the reference time (in addition, timings (c) and (d)). ) Is cumulative from (b)). In many types of information recording media, their timing greatly depends on the trailing edge position control of recording marks formed. On the other hand, TSS,
Timing information such as TSP becomes important. By independently setting the main parameters for the front and rear edge position control, the setting value of each parameter does not affect the final pulse timing, and the influence on the recording mark edge position is limited.

That is, when the parameter setting values are changed during the recording operation, even if the parameters are sequentially changed, the degree of influence on the recording mark shape is small. For example, it is necessary to change each parameter according to the recording linear velocity in order to control the shape of the recording mark with high accuracy, and when performing CAV recording, change the set value according to the recording linear velocity during the recording operation. Therefore, it is suitable in such a case. In order to simplify the circuit, the timings (a) and (b) may be determined by accumulating the timing information TLS and TLM, respectively, as indicated by the broken lines.

Further, in the present embodiment, the drive waveform is changed according to the mark length of the recording data signal Wdata and the space length adjacent to the mark length, and the recording mark edge position to be formed is controlled with high accuracy. When the recording mark is formed, the adjacent space length causes a thermal effect on the information recording medium, and the edge changes depending on the adjacent space length. In order to avoid this, the drive waveform is changed in consideration of the adjacent space length. That is, the drive waveform generation information corresponding to each combination of the mark length and the space length immediately before and after is stored, and the run length detecting unit 11 is stored.
Run length signals Len0 to Len detected by 1
The drive waveform generation information corresponding to 2 is supplied.

When the mark length and the adjacent space length are equal to or greater than the predetermined value, the thermal effect and the change amount thereof are small. Therefore, it is not necessary to prepare drive waveform generation information corresponding to all combinations. For example, as shown in FIG. 19, it is possible to reduce the memory capacity required for holding information by preparing a table in which only combinations having a large influence degree are registered in advance. Also, in this embodiment, the combination prepared according to each parameter is changed to achieve both reduction in memory capacity and high accuracy in mark shape control.

FIG. 20 is a diagram showing a detailed internal configuration example of the drive waveform generation information holding section 112 shown in FIG. The memories 152a to 152n for storing the respective parameters operate independently of each other, and the run length signals Len0 to Len2.
Address conversion unit (Addr Convert
er) 150a to 150n for conversion, selector 1
It is supplied as an address signal of the memories 152a to 152n via 51a to 151n. Output buffer 153a-
The control unit 118 controls the output of read data corresponding to the memory for which the control unit 118 has issued a read request. The register access control unit 154 generates an output enable signal and supplies it to each output buffer.

Register access control unit (Register)
r Access Control) 154 is shown in FIG.
Access control to each of the memories 152a to 152n is performed in response to a write / read request from the control unit 118. The selectors 151a to 151n include the register access control unit 1
When the memory is accessed from 54, the address supplied from the address conversion units 150a to 150n and the address supplied from the register access control unit 154 are switched. In addition, the register access control unit 154
Responds to the memory access request during the recording operation to access the memories 152a to 152n during the space period.

[Timing Signal Generation Unit and Modulation Signal Generation Unit] The timing signal generation unit 113 generates a modulation timing signal from drive waveform generation information (timing information). The modulation timing signal is composed of a timing pulse signal synchronized with the clock signal PCK multiplied by n and a phase selection signal. The modulation signal generation unit 114 generates the LD modulation signal WSP from the modulation timing signal supplied by the timing signal generation unit 113. At the time of generation, the clock signals CK0 to CK7 are used as a reference, and the time corresponding to the phase difference between these clock signals becomes the pulse width setting resolution of the LD modulation signal WSP.

FIG. 21 is a diagram showing a detailed internal configuration example of the timing signal generator 113 and the modulation signal generator 114. 22 and 23 are waveform diagrams of signals output from the respective units of the timing signal generation unit 113 and the modulation signal generation unit 114 shown in FIG. FIG. 24 is an explanatory diagram showing the operations of the two sequencers in the timing control section 160 shown in FIG. An outline of the operation of generating the LD modulation signal WSP from the drive waveform generation information via the generation of the timing pulse signal and the phase selection signal will be described with reference to FIGS.

The timing control unit (Timi shown in FIG.
ng Control) 160 generates a control signal for each unit described later based on the operation of the two sequencers shown in FIG. Further, the reference time of the pulse train of the LD modulation signal WSP is generated by delaying the delay recording data signal dWdata by a predetermined time Δ (PCK unit). Timing calculator 161
Calculates the pulse width setting step number from the timing information supplied from the drive waveform generation information holding unit 112 to the next modulation timing based on the calculation instruction signal supplied from the timing control unit 160.

In the present embodiment, the rising modulation timing and the falling modulation timing are separately processed in order to realize the high-speed operation of the circuit, and the next rising modulation timing Next.
Timing1 and the next falling modulation timing NextT
calculate each of iming2. Then, in the calculated number of steps up to the next rising modulation timing NextTiming1, the upper 5 bits are a counter (Count).
er) 163a and the lower 3 bits are supplied to the phase selection signal holding unit (Reg) 164a as a phase selection signal (here, the pulse width setting step number is 8 bits). Similarly, the next falling modulation timing Next
Regarding the number of steps up to Timing2, the upper 5 bits are supplied to the counter (Counter) 163b, and the lower 3 bits are supplied to the phase selection signal holding unit (Reg) 164b.

Further, similarly, the timing calculation unit 16
2 is a pulse (i) of the LD modulation signal WSP shown in FIG.
And (ii) rising / falling modulation timings are calculated (each rising modulation timing signal NextT
aiming3 and falling modulation timing signal NextTi
ming4), each counter (Counter) 1
63c and 163d and a phase selection signal holding unit (Reg) 1
Supply to 64c and 164d. In addition, the timing control unit 160 uses the delay recording data signal dWdata to (n−
3) Channel clock (n is the delayed recording data signal dWd
(mark length of ata) and a second reference time delayed by a predetermined time Δ. Modulation timing signal NextTimin
g3 and NextTiming4 are generated based on the second reference time.

The counters 163a to 163d count the time until the next modulation timing according to the clock signal PCK, and calculate the timing calculation units 161 and 162 according to the load signal load1 or load2 supplied from the timing control unit 160. Captures the number of steps until the next modulation timing and outputs the clock signal PCK
To count down. Then, when the count value becomes zero, the set pulse signal (Fse
t, Rset) / reset pulse signal (Frst, Rr
st) (collectively referred to as "timing pulse signal") is output. Phase selection signal holding units 164a to 164
d holds the phase selection signals ckph1 to ckph4 and supplies them to the next stage. The holding timing is determined based on the signal supplied from the timing control unit 160 (not shown).

The timing pulse signal control unit 165 receives the timing pulse signals Fset, Rset, Frst, Rr supplied from the counters 163a to 163d, respectively.
The set / reset signal for each of the flip-flops 167a to 167d is generated from st. The phase selection signals ckph1 to ckph4 supplied from the phase selection signal holding units 164a to 164d are supplied to the clock selectors 166a to 166d, respectively. The flip-flop 167a has a set pulse signal Fset.
(Or Rset) according to the output signal q_A high (H)
To At that time, the rising modulation timing signal is determined by the clock signal (any one of CK0 to CK7) selected by the clock selector 166a according to the phase selection signal ckphA. For example, although FIG. 23 is an enlarged view of the portion (P) of FIG. 22, CK2 is selected as shown in FIG.

On the other hand, the flip-flop 167b sets the output signal q_B to low (L) according to the reset pulse signal Frst (or Rrst). At that time, the falling modulation timing signal is determined by the clock signal (any one of CK0 to CK7) selected by the clock selector 166b according to the phase selection signal ckphB. Then, the LD modulation signal WSP is obtained by taking the logical product of the output signals q_A and q_B.
To generate.

The reset pulse signal Rst_A for the flip-flop 167a and the flip-flop 167b are used.
The set pulse signal Set_B is generated according to the set pulse signal Fset (or Rset) and the reset pulse signal Frst (or Rrst), respectively. Similarly, the flip-flops 167c and 167d and the clock selectors 166c and 166d also use the LD modulation signal WSP.
To realize a high-speed circuit operation, portions (I) and (II) shown by a chain line in FIG. 21 alternately operate,
Finally, the logical sum is taken to generate the LD modulation signal WSP. The timing pulse signal control unit 165 uses the timing pulse signals Fset, R in order to perform the alternating operation.
set, Frst, Rrst and phase selection signal ckph
It also functions to sort 1 to ckph4. Logic circuit 16
Reference numeral 8 denotes a logical product of the output signals q_A and q_B, a logical product of the output signals q_C and q_D, and a logical sum of the logical product output values to generate the LD modulation signal WSP.

FIG. 24 is a state transition diagram of the two sequencers provided in the timing control section 160 shown in FIG. 21, and includes two sequencers, (a) a sequencer (Sequencer) 1 and (b) a sequencer (Sequencer) 2. Each part is controlled by. Next, the transition conditions of the sequencers 1 and 2 will be described. 22 and 23 show an example of state transition.

(A) Sequencer 1 state Idle: initial state. Delayed recording data signal dWda
A transition to state SP is made by the rise of ta. Until then, stay here. State SP: transition to the next state by the load1 signal issued at the reference time, and the others are retained here. At this time, the transition destination differs depending on the drive waveform generation information (TSMS and TMS). That is, when TSMS≈0, the state SM
To P, and to state MP when TSMS = 0 and TMS≈0,
At other times (TSMS = 0 and TMS = 0), state L
Transition to P respectively. State SMP: The load1 signal issued at the same time as the reset pulse signal Frst causes a transition to the next state, and the others remain there. At that time, drive waveform generation information (TM
The transition destination differs depending on S). That is, when TMS≈0, the state changes to the state MP, and when TMS = 0, the state changes to the state LP.

State MP: Transition to state LP by the load1 signal issued at the same time as the reset pulse signal Frst. However, the number of MP repetitions designated by NMP stays here. FIG. 22 shows the case where NMP = 2. State LP: State W by reset pulse signal Frst
Transition to ait. State Wait: Standby state when the sequencer 2 controls each part. After transition to the initial state of the sequencer 2, the state transitions to Idle.

(B) Sequencer 2 State Idle: Initial state. Delayed recording data signal dWda
A transition to the next state occurs at the rise of ta. From the rising edge of the delayed recording data signal dWdata, (n-3) T (n:
During the mark length, T: channel clock period), a wait signal is output, and in that case, the state transits to Wait. On the other hand, when the wait signal is not output at n = 3, the state changes to the state LMP. State Wait: Stays here while the wait signal is being output. When the wait is released, the state transits to LMP. State LMP: Transition to the state EP by the load2 signal (issued after a predetermined time Δ for releasing the wait). State EP: transition to state End by the load2 signal issued at the same time as the reset pulse signal Rrst. State End: Transition to state Idle by the reset pulse signal Rrst.

Next, a timing calculation formula for each state of each sequencer calculated by the timing calculation units 161 and 162 will be shown. {Timing operation unit 161} NextTiming1 = TSS @Idle or SP TSMS + ckph2 @SMP TMS + ckph2 @MP NextTiming2 = TSS + TSP @Idle or SP TSMS + TSMP + ckph2 @SMP TMS + TMP + ckph2 @MP {Timing operation unit 162} NextTiming3 = TLMP @Idle or Wait or LMP TES + ckph4 @EP NextTiming4 = TEMP @Idle or Wait or LMP TES + TEP + ckph4 @EP

FIG. 25 is a waveform diagram for explaining the signal deleting process in the timing pulse signal control unit 165 shown in FIG. Further, the generation of the set pulse signal Fset and the reset pulse signal Frst and the set pulse signal Rs
Since it is performed independently of the generation of et and the reset pulse signal Rrst, as shown in FIG. 25, the pulse signal WSP_F generated by the set pulse signal Fset and the reset pulse signal Frst and the set pulse signal Rset are generated.
And the pulse signal WSP_R generated by the reset pulse signal Rrst may overlap. In that case, the timing pulse signal control unit 165 deletes the reset pulse signal Frst and the set pulse signal Rset (the deleted portions are circled in FIG. 25), and the LD is set by the set pulse signal Fset and the reset pulse signal Rrst. A signal is supplied to the next stage so that the modulation signal WSP is generated.

In the above-described embodiment, the delay of each circuit is neglected for the sake of simplification of description, but in the actual circuit, a holding circuit for the clock signal PCK is inserted in each signal line, so several PCK clocks are required. There will be a minute delay. Therefore, the output LD modulation signal WSP, that is, the optical waveform is delayed by several PCK clocks (Δ ′) from the reference time, and only Δ + Δ ′ in total from the delayed recording data signal dWdata synchronized with the recording channel clock signal CKch. Be delayed. By the way, since the multiplication number of the clock signal PCK with respect to the recording channel clock signal can be set as described above, if this multiplication number is changed at the time of additional recording or rewriting, the recording mark with respect to the recording channel clock signal will be deviated. In such a case, the delay amount Δ for generating the reference time may be set according to the PCK multiplication number. For example, circuit delay Δ ′ = 3PCK, Δ + Δ ′ = 2
If CKch, the multiplication number is 2 (1CKch = 2PC
K), Δ = 1PCK, and when the multiplication number is 4, Δ
= 5PCK should be set.

The timing signal generator 113 also includes a STEN timing pulse generator 170 for generating a modulation timing signal for generating the state signal STEN. Furthermore, the bias current control unit 2 shown in FIG.
7. Light source driven by the differential quantum efficiency control unit 28 (L
When the irradiation light amount of D) is controlled, a pulse indicating the sampling timing is inserted in the LD modulation signal WSP in order to generate various sample signals (ApcSmp signal, EtaSmp signal). For example, in the signal waveform diagrams shown in FIGS. 4 and 10, t11 to t12, t13 to t14, t15.
The pulse inserted at ~ t16 or the like corresponds.

The APC timing pulse generator 171
To generate the modulation timing signal for that,
The generated modulation timing signal is supplied to the timing pulse signal control unit 165, and the LD modulation signal WSP is generated in the same manner as described above. The generation of these modulation timing signals is performed by the control signal from the timing control unit 160. In this way, by inserting the pulse indicating the sampling timing into the LD modulation signal WSP, the sampling timing can be instructed without adding a signal line, so that the number of signal supply lines transmitted on the FPC board can be reduced. .

FIG. 26 shows the STEN timing pulse signal from the STEN timing pulse generator 170 and the APC timing pulse generator A from the APC timing pulse generator 171 shown in FIG.
FIG. 9 is a waveform diagram for explaining an example of generating a PC timing pulse signal. [APC timing pulse generator] Timing controller 1
60 outputs an APC count start signal at the same time as the second reset pulse signal Rrst. The APC timing pulse generation unit 171 receives the APC count start signal, and an internal counter causes a predetermined value APC to be output.
After counting S (PCK unit), the APCSet pulse signal is output after the counting.

Also, the APCRst pulse signal is APCS
It is output after a predetermined value (for example, 1PCK) from the et pulse signal. Further, when η is detected, the EtaDetOn signal becomes high (H) and is supplied, the predetermined values EtaS and EtaC are continuously counted by the counter, and the APCSet pulse signals are output. APCRst
The pulse signal is output after a predetermined value (for example, 1PCK) from the APCSet pulse signal in the same manner as described above.

The EtaDetOn signal becomes high (H) when there is an η detection instruction issued from the controller 19 of FIG. 2 at a predetermined interval and the space length is equal to or more than the predetermined value EtaLen, and the timing pulse signal generation processing is performed. After that, the η detection instruction is automatically cleared. On the other hand, EtaD
When the etOn signal is low (L), the APCSet pulse signal, APC in the frame (D) circled in FIG.
The Rst pulse signal is not generated, and the pulses (B) and (C) in the figure do not appear in the LD modulation signal WSP.

[STEN Timing Pulse Generator] As described above, in this embodiment, the optical waveform can be changed by changing the falling modulation timing of the state signal STEN. The waveform shown in FIG. 4 is called the LP mode and the waveform shown in FIG. 10 is called the EP mode, and the generation of the STEN timing pulse signal in each mode (indicated by LP / EPMode) will be described. As shown in FIG. 26, the STENRst pulse signal is Seq. 2 = EP and output at the same time as the Rset pulse ((A) in FIG. 26), and Seq. 1 = LP and output at the same time as the Fset pulse (broken line with arrow (a) in FIG. 26). Also, ST
The output timing of the ENSet pulse signal is EtaDet
It changes depending on the On signal and outputs at the timings shown in FIG. Further, in the same manner, not only the sampling timing but also the command instruction and the like can be transferred without adding a signal line.

[State Signal Generation Unit] The state signal generation unit 115 shown in FIG.
In S, the state signal STEN is generated from the STEN timing pulse signal which is the modulation timing signal generated from the drive waveform generation information (timing information). The internal configuration of the state signal generation unit 115 may be the same as that within the dashed-dotted frame (I) in FIG.
The generation of N is not as fast as that of the LD modulation signal WSP, so it is not necessary to perform the alternating operation. Also, the state signal STE
Since the edge position accuracy of N is not necessary as much as the LD modulation signal WSP, it is not necessary to use all 3 bits of the phase selection signal, and it may be fixed to any one of the clock signals CK0 to CK7. The bits of the selection signal may be reduced.

[State Command Generation Unit] The state command generation unit 116 generates the command signal STCMD from the drive waveform generation information (command information). The command signal STCMD is sent to the command decoder 2 as described above.
In 2, the state signal STEN is taken in at both edges. Therefore, the data change timing of the command signal STCMD only needs to ensure a sufficient fetch time before and after the edge of the state signal STEN. here,
The supplied command information is sequentially supplied to the LD drive integrated circuit (LD driver) 1 with the reference time and the APC count start time as switching timing.

[Sample Signal Generation Unit] The sample signal generation unit 117 generates a sample hold type APC control sample signal from the recording data signal Wdata. Since the light emission waveform of the light source is delayed by the delay in the run length detection unit 111 with respect to the recording data signal Wdata, the sample signal is generated according to the light emission waveform. However, as described above, the sample signal generated here is not used when the APC control is performed with the configuration shown in FIG.

[Error Detecting Section and Error Processing Section] When the drive waveform generation information contains incorrect data due to some accident, or when the drive waveform generation information is combined with incorrect data, the LD modulation signal WSP and the state signal STEN Cannot generate a pulse signal at a desired timing, and the LD driving integrated circuit 1 which drives the LD upon receiving them cannot obtain a desired optical waveform and erroneous information may be recorded. In addition, there is a possibility that an error may propagate to the next and subsequent marks, or that light emission with high power continues and the LD may be destroyed.

FIG. 27 is a block diagram showing a structural example of an embodiment in which an error detection means and an error processing means are added to the LD modulation signal generation section 10. The error detection unit 180 includes a timing control unit 160 in the timing signal generation unit 113.
Sequencer state and delayed recording data signal dWdata
The occurrence of an error is detected from and. For example, if the sequencer Seq1 and Seq2 do not return to the state Idle even after the recording data signal dWdata becomes a space for a predetermined time, an error occurrence signal is output as an error. Also,
The error may be determined by calculating from the drive waveform generation information (timing information).

The error processing unit 181 receives the error occurrence signal and instructs the timing signal generation unit 113 to stop the supply of the modulation timing signal and to return the sequencer to the initial state, thereby causing the sequencer 21 in the LD drive integrated circuit 1 to operate. Since the LD modulation signal WSP and the state signal STEN are generated so as to be reset to the initial state, the modulation signal generation unit 114
And an error processing pulse is supplied to the state signal generator 115. Furthermore, by directly supplying the error occurrence signal to the controller 19 (or via the control unit 118),
Instruct to correct the drive waveform generation information (timing information). By doing so, it is possible to prevent the error from being propagated and to prevent erroneous data from being continuously recorded.

The second error detection unit 182 shows another embodiment of error detection, and is provided with the same one as the sequencer 21, and receives the LD modulation signal WSP and the state signal STEN to perform LD drive integration. The irradiation level state in the circuit 1 is pseudo-monitored. In this way, the occurrence of an error is detected and error processing similar to the above is performed.

[Other Embodiments of Command Signal and Command Decoder] FIG. 28 is a diagram showing a configuration example of another embodiment of the state command generator and the command decoder. Further, FIG. 29 is a waveform diagram of signals output from the respective units shown in FIG. As shown in FIG. 28, the state command generation unit (STCmd Gen.) 190 outputs the command signal STCMD in synchronization with the LD modulation signal WSP based on the modulation timing signal. Command decoder (C
MD Decoder) 191 is an LD modulation signal WSP
And the command signal STCMD are converted into a mode control signal SeqMode that specifies the LD irradiation level and the irradiation mode. By doing so, the number of signal lines of the command signal STCMD can be reduced.

Next, the parts relating to the constituents of each claim of the present invention in the above embodiment will be specified. (1) Part related to claim 1 of the present invention The description based on FIG. 18 is the description. (2) The driving waveform generation information holding unit 112 of the partial diagram 15 according to claim 2 of the present invention performs the function of the driving waveform generation information holding unit, and the driving waveform generation information holding unit 112 of FIG. The function of the selection means
The timing signal generation unit 113 and the modulation signal generation unit 114 of FIG. 15 perform the functions of the above-mentioned modulation signal generation means. The description based on FIG. 3 is the description of the light source driving means.

(3) Part relating to claim 3 of the present invention A functional unit corresponding to the irradiation level selecting means is provided in the sequencer 21. (4) Part relating to claim 4 of the present invention The description in paragraph [0039] is the explanation. (5) The description of paragraph [0121] is based on the partial view 19 of claim 5 of the present invention. (6) Part relating to claim 6 of the present invention The same as the above (5), the paragraph number [01
21] is the description.

(7) Part relating to claim 7 of the present invention The description in paragraph [0117] is the explanation. (8) The description based on the partial diagram 18 of claim 8 of the present invention is the description. (9) The description based on the partial diagram 18 of claim 9 of the present invention is as follows. (10) The description based on the partial diagram 18 according to claim 10 of the present invention is the description thereof. (11) Part related to claim 11 of the present invention The description of the paragraph number [0055] and the like is the explanation.

[0158]

As described above, according to the optical information recording apparatus of the present invention, the deviation from the desired value of the optical modulation waveform due to the distortion or skew of the optical modulation control signal waveform is suppressed, and the information recording is performed. It is possible to meet the demand for higher speed and higher density recording on the information recording medium without sacrificing cost and performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an information recording / reproducing apparatus which is an embodiment of an optical information recording apparatus of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a signal processing unit 104 shown in FIG.

3 is an LD control unit 9 and an LD drive unit 12 shown in FIG.
FIG. 3 is a configuration diagram of an LD drive integrated circuit 1 in which is integrated.

FIG. 4 is a waveform diagram showing an example of output signals of respective parts of the LD drive integrated circuit 1 shown in FIG.

5 is a state transition diagram of the sequencer 21 shown in FIG.

FIG. 6 is a block diagram showing another configuration example of the modulator 23 shown in FIG.

FIG. 7 is a block diagram showing another configuration example of the bias current control unit 27 shown in FIG.

FIG. 8 is a diagram showing an example of drive current-optical output characteristics.

FIG. 9 is a diagram showing an example of a light modulation waveform.

10 is a waveform chart showing another example of the output signal of each part of the LD drive integrated circuit 1 shown in FIG.

FIG. 11 is a block diagram showing still another configuration example of the modulator 23 shown in FIG.

12 is a waveform diagram showing an output signal of each unit of the modulation unit 23 shown in FIG.

FIG. 13 is a diagram for explaining the disturbance of the optical waveform due to the deviation of the switch timing of the LD drive current.

FIG. 14 is a diagram showing an example of each signal waveform for explaining the operation of the bias current control section 27 shown in FIG.

15 is a diagram showing a configuration of an LD modulation signal generation section 10 shown in FIG.

16 is a diagram showing a detailed internal configuration example of the run-length detector 111 shown in FIG.

17 is a waveform chart of a signal output by each unit in the run length detection unit 111 shown in FIG.

FIG. 18 is a timing chart showing a relationship between drive waveform generation information and an optical waveform in this embodiment.

FIG. 19 is a list showing a combination example of drive waveform generation information for each of a plurality of timing information.

20 is a diagram showing a driving waveform generation information holding unit 11 shown in FIG.
It is a figure which shows the example of a detailed 2nd internal structure.

FIG. 21 is a timing signal generator 113 shown in FIG.
3 is a diagram showing a detailed internal configuration example of a modulation signal generation section 114. FIG.

FIG. 22 is a timing signal generator 113 shown in FIG.
3 is a waveform diagram of signals output from each unit of the modulation signal generation unit 114. FIG.

23 is a waveform chart of signals output from the respective parts of the timing signal generation unit 113 and the modulation signal generation unit 114 shown in FIG. 21.

24 is an explanatory diagram showing the operation of two sequencers in the timing control section 160 shown in FIG.

FIG. 25 is a waveform chart provided for explaining the signal deletion processing in the timing pulse signal control unit 165 shown in FIG.

FIG. 26 is a STEN timing pulse signal and A by the STEN timing pulse generator 170 shown in FIG.
FIG. 7 is a waveform diagram for explaining an example of generation of an APC timing pulse signal by a PC timing pulse generation unit 171.

27 is a block diagram showing a configuration example of an embodiment in which an error detection unit and an error processing unit are added to the LD modulation signal generation unit 10 shown in FIG.

FIG. 28 is a diagram showing a configuration example of a state command generation unit and a command decoder of another embodiment of the present invention.

FIG. 29 is a waveform chart of a signal output from each unit shown in FIG. 28.

[Explanation of symbols]

1: LD drive integrated circuit 2: Light reception signal processing unit 4: RF selection unit 6: Wobble signal generation unit 9: LD control unit 10: LD modulation signal generation unit 12: LD drive unit 13: Servo signal calculation processing unit 14: Servo Processor 15: Wobble signal processing unit 16: RF signal processing unit / PLL unit 17: WCK generation unit 18: Rotation control unit 19: Controller 20: Servo driver 21: Sequencer (Sequencer) 22: Command decoder (CMDDecoder) 23: Modulation unit (Data-Modulation) 24: Current addition unit 25: Current drive unit 26: PD amplifier unit (PD-AMP) 27: Bias current control unit (Bias-Contro)
l) 28: Differential quantum efficiency control unit (η-Control) 29: Bias current selection unit (MUX) 30: High frequency modulation unit (HF-Modulation) 31, 32: DC / DC converter 33: Control unit 40: PbDAC 41: PtpDAC 42, 44, 54, 96: Switch 43: Scale DAC (Scale DAC) 45, 46: Current amplifier 47: Current-voltage converter (I
/ V) 48,65: MUX 49: Offset DAC (Offset DAC) 50: Adder 51: Gain switching amplifier (X1 / X4 / X8 / X16)
AMP) 52: P-BDAC 53: P-PDAC 55: Error amplifier 56: S / H integrator (S / HInteg.) 57: Sample hold circuit (S / H) 58: Difference device 59: etarefDAC 61: Comparator (Comp) 62: Counter (Count
t) 63: FreqDAC 64: VCO 65: MUX 66: HFBDAC 67: Buffer amplifier 70: Bias scale DAC (BSscaleDAC) 71: Bias DAC (BiasDAC) 80a: PrDAC 80b: PeDAC 80c: PbDAC 80d: 81bPacDAC PtpDAC 81c: PmpDAC 81d: PlpDAC I0, I0a to I0d, I1, I1a to I1d: Current 82, 83, 84: Switch 90: Pb + DAC 91: PbDAC 92: Pt + DAC 93: PtDAC 94, 95: Adder ILD: Drive current 100. : Information recording medium 101: Pickup 102: Light source (LD) 103: Light receiving unit 104: Signal processing unit 105: Rotation drive unit 106: Controller 110: PLL unit 1 1: run-length detection unit (RunLength D
et. ) 112: Drive waveform generation information holding unit (Strategy)
Memory) 113: Timing signal generation unit 114: Modulation signal generation unit 115: State signal generation unit (STEN Gen.) 116: State command generation unit (STCmd Ge)
n. ) 117: Sample signal generator (Sample Timi)
ng Gen. ) 118: control unit 120: M frequency divider (1
/ M) 121: Phase comparator (PC) 122: Loop filter (Filter) 123: Oscillator (VCO) 124: N frequency divider (1
/ N) 125: M / N frequency divider 140: Counter (C
counter) 141: delay circuit (Delay) 142: FIFO control unit (FIFO Ctrl) 143: FIFO 144: register (R)
eg) 150a to 150n: Address conversion unit (Addr Co)
nverter) 151a to 151n: selectors 152a to 152n:
Memory 154: Register access control unit (Register)
Access Control 160: Timing control unit (Timing Control) 161, 162: Timing calculation units 163a to 163d: Counters 164a to 164d: Phase selection signal holding unit (Reg) 165: Timing pulse signal control units 166a to 166d: Clock selectors 167a to 167d: Flip-flop 170: STEN timing pulse generation unit 171: APC timing pulse generation unit 180: Error detection unit 181: Error processing unit 182: Second error detection unit 190: State command generation unit (STCmd Ge)
n. ) 191: Command decoder (CMD Decoder) IoutSel: Selection signal PD1 to PD5: Light receiving parts LD1 and LD2: Light source

Continued front page    F-term (reference) 5D044 BC04 CC04 EF02                 5D090 AA01 BB03 BB04 CC01 DD03                       EE02 KK04 KK05                 5D119 AA23 BA01 BB02 BB04 DA01                       HA12 HA16 HA47 HA60                 5D789 AA23 BA01 BB02 BB04 DA01                       HA12 HA16 HA47 HA60

Claims (11)

[Claims] 1. A light source is caused to emit light in a plurality of pulse train waveforms based on a multi-valued irradiation level corresponding to a binarized signal for recording on an information recording medium, and the emitted light is irradiated to the information recording medium, and An optical information recording apparatus for forming a recording mark corresponding to a binarized signal, wherein the frequency and duty of the pulse train waveform are set arbitrarily. 2. A light source is caused to emit light in a plurality of pulse train waveforms based on a multilevel irradiation level corresponding to a binary signal for recording on an information recording medium, and the emitted light is applied to the information recording medium, In an optical information recording device for forming a recording mark corresponding to a binarized signal, at least one or more of timing information indicating each pulse width of the plurality of pulse train waveforms and pulse number information indicating the number of repetitions of the timing information. A drive waveform generation information holding means to be stored, an information selection means for selecting one of the timing information based on the binarized signal, and timing information and pulse number information selected by the information selection means. A modulation signal generating means for generating a modulation signal indicating the change timing of the irradiation level based on the modulation signal, the modulation signal generated by the modulation signal generating means, and A light source drive unit that controls the transition of the state based on a state transition signal that instructs the transition of the state corresponding to the irradiation level and a preset transition rule, and drives the light source based on the selected state. An optical information recording device characterized by being provided. 3. A light source is caused to emit light with a plurality of pulse train waveforms based on a multi-valued irradiation level corresponding to a binarized signal for recording on an information recording medium, and the emitted light is applied to the information recording medium. In an optical information recording device for forming a recording mark corresponding to a binarized signal, at least one or more of timing information indicating each pulse width of the plurality of pulse train waveforms and pulse number information indicating the number of repetitions of the timing information. Drive waveform generation information holding means to be stored, information selection means for selecting one of the timing information based on the binarized signal, timing information selected by the information selection means and the pulse number information A modulation signal generating means for generating a modulation signal indicating the change timing of the irradiation level based on the above, and a modulation signal generated by the modulation signal generating means. Light source driving means for controlling the transition of the state based on a state transition signal instructing the transition of the state corresponding to the irradiation level and a preset transition rule, and driving the light source based on the selected state, , At least one of the states corresponding to at least one of the irradiation levels of the plurality of pulse train waveforms corresponds to a plurality of irradiation levels, one of which is selected according to irradiation level selection information, and corresponds to the state An optical information recording device, comprising: an irradiation level selecting means for changing the irradiation level to the selected irradiation level. 4. A light source is caused to emit light in a plurality of pulse train waveforms based on a multi-valued irradiation level corresponding to a binary signal for recording on an information recording medium, and the emitted light is irradiated to the information recording medium, and In an optical information recording device for forming a recording mark corresponding to a binarized signal, at least one or more of timing information indicating each pulse width of the plurality of pulse train waveforms and pulse number information indicating the number of repetitions of the timing information. Information selection means for selecting one of each of the timing information in accordance with a combination of the drive waveform generation information holding means to be stored and the recording mark length indicated by the binarized signal or a space length added before and after the recording mark length. Means, and a modulation signal indicating a change timing of the irradiation level based on the timing information and the pulse number information selected by the information selecting means. Modulation signal generating means for generating, the modulation signal generated by the modulation signal generating means, the state transition signal for instructing the transition of the state corresponding to the irradiation level, and the transition of the state based on a preset transition rule At least one of the light source driving means for controlling and driving the light source based on the selected state and the state corresponding to at least one of the irradiation levels of the plurality of pulse train waveforms corresponds to the plurality of irradiation levels. , One of them is selected according to the irradiation level selection information generated according to the recording mark length or the combination of the space length before and after the recording mark length, and the irradiation level corresponding to the above state is selected as the irradiation level. An optical information recording device, characterized in that an irradiation level selecting means for changing the optical information recording device is provided. 5. The optical information recording apparatus according to claim 2 or 3, wherein the information selecting means has a recording mark length that is an odd number or an even number with respect to a reference recording clock, or an odd number or an even number except for a specific mark length. An optical information recording device, characterized in that the optical information recording device is means for selecting the timing information. 6. The optical information recording apparatus according to claim 4, wherein the timing of the information selecting means is determined by whether the recording mark length is an odd number or an even number with respect to a reference recording clock, or whether the recording mark length is an odd number or an even number excluding a specific mark length. An optical information recording apparatus, characterized in that information is selected and the irradiation level selection information is generated. 7. The optical information recording apparatus according to claim 2, wherein the timing information and the pulse number information are changed according to a recording linear velocity. Information recording device. 8. The optical information recording apparatus according to claim 3 or 4, wherein the state where the irradiation level is changed by the irradiation level selecting means corresponds to the head pulse irradiation level of the pulse train waveform. Optical recording device. 9. The optical information recording apparatus according to claim 3 or 4, wherein the state where the irradiation level is changed by the irradiation level selecting means corresponds to the final pulse irradiation level of the pulse train waveform. Optical recording device. 10. The optical information recording apparatus according to claim 3 or 4, wherein a state in which the irradiation level is changed by the irradiation level selecting means corresponds to an erase start head pulse irradiation level of the pulse train waveform. An optical information recording device characterized by: 11. The optical information recording apparatus according to claim 3 or 4, wherein the state in which the irradiation level is changed by the irradiation level selection means is changed by changing the state transition signal or the transition rule. An optical information recording device characterized by: