JP2003133855A - Temperature compensating input circuit and temperature compensating oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a temperature compensating input circuit capable of suppressing the change of an operating point bias voltage due to a leakage current, and to provide a temperature compensating oscillation circuit. SOLUTION: The temperature compensating input circuit comprises an input terminal 1, an input circuit 2, and a temperature compensating circuit 3. The circuit 2 is a circuit block having an input end of a predetermined high impedance. The input end of the circuit 2 is connected to the input terminal 1, and the output end of the compensating circuit 3 is connected to the input end of the circuit 2. Therefore, the voltage of the input end of the circuit 2 is controlled so as to be equal to the reference voltage provided in the compensating circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temperature-compensated input circuit and a temperature-compensated oscillator circuit, and more particularly to a temperature-compensated input circuit and a temperature-compensated oscillator circuit in which fluctuations in operating point bias voltage due to leak current are suppressed. Regarding

[0002]

2. Description of the Related Art A crystal oscillation circuit is an example of a configuration in which an external signal is input through an input terminal to an input circuit having a high impedance input terminal formed on a semiconductor integrated circuit chip.

As shown in FIG. 6, a conventional crystal oscillation circuit has an electrostatic discharge as an input terminal 1 and an output terminal 4 provided on a semiconductor integrated circuit chip and an input circuit 2 having an input end with high impedance ( A protection circuit 21, a CMOS inverter 22, and a feedback resistor 23;
An ESD protection circuit 8, a Schmitt circuit 9, a crystal oscillator 5, a capacitor 6, and a capacitor 7 are provided.

Crystal oscillator 5 outside the semiconductor integrated circuit chip
Is connected between the input terminal 1 and the output terminal 4, the capacitor 6 is connected between the input terminal 1 and the low potential side power supply VSS, and the capacitor 7 is connected between the output terminal 4 and the low potential side power supply VSS. CMOS connected as an input end of the input circuit 2
The input terminal of the inverter 22 is connected to the input terminal 1,
The output terminal of the OS inverter 22 is connected to the output terminal 4,
The feedback resistor 23 and the input terminal of the CMOS inverter 22 and CM
It is connected between the output terminal of the OS inverter 22 and the ESD
The protection circuit 21 is connected to the input end of the CMOS inverter 22, and the ESD protection circuit 8 is connected to the output end of the CMOS inverter 22.

In the ESD protection circuit 21 as an overvoltage protection circuit, the gate end and the source end are the high-potential-side power supply VD.
A P-channel MOS transistor P1 connected to D and having a drain end connected to an input end of the CMOS inverter 22
And an N-channel MOS transistor N1 having a gate end and a source end connected to the low-potential-side power supply VSS and a drain end connected to the input end of the CMOS inverter 22, and the ESD protection circuit 8 as an overvoltage protection circuit includes: A P-channel MOS transistor P2 having a gate end and a source end connected to the high potential side power supply VDD and a drain end connected to the output end of the CMOS inverter 22, and a gate end and a source end connected to the low potential side power supply VSS and a drain end. Is C
And an N-channel MOS transistor N2 connected to the output terminal of the MOS inverter 22.

The input end of the Schmitt circuit 9 is CM.
An internal circuit (not shown) as a clock signal is connected to the output end of the OS inverter 22 and the oscillation signal obtained from the output end of the CMOS inverter 22 is waveform-shaped by the Schmitt circuit 9 having a noise removal function at the time of starting oscillation. To be given to.

[0007]

CMOS inverter 2
When the feedback resistor 23 is connected to 2, the CMOS inverter 22 functions as an inverter amplifier. Figure 7
[Fig. 4] is an input / output characteristic diagram of an inverter amplifier. CMOS
The operating point bias voltage at the input terminal of the inverter 22 is a threshold voltage point (A) of the CMOS inverter 22 where the gain (output voltage change amount / input voltage change amount) as an inverter amplifier is maximized due to self-bias by the feedback resistor 23. Point), and oscillation is started at the resonance frequency of the crystal unit 5 by the gain of the inverter amplifier and the phase adjustment by the capacitors 6 and 7.

However, when the ambient temperature rises and a leak current is generated in the source / drain path of the N-channel MOS transistor N1 which is normally in the off state of the ESD protection circuit 21, the input end of the CMOS inverter 22 has a high impedance. Therefore, the leakage current is the CMOS inverter 2
Since the voltage is supplied from the second output terminal, the operating point bias voltage at the input terminal of the CMOS inverter 22 shifts due to the voltage drop of the feedback resistor 23. As shown in FIG. 8, the leak current exponentially increases with temperature rise (for example, a temperature rise of 8 ° C. doubles, and a temperature rise of 100 ° C. increases 6000 times.
Therefore, when the temperature is high, the point (point B) at the end of the dynamic range of the inverter amplifier fluctuates, the gain becomes 1 or less, and oscillation stops. As an example, the resistance value of the feedback resistor 23 is 5M.
In the case of a crystal oscillating circuit having a leakage current of 100 nA at Ω and 120 ° C. and an oscillation frequency of 32 KHz, the operating point bias voltage is shifted by 0.5 V.

Further, if the power supply voltage is lowered due to the miniaturization of the manufacturing process, the N-channel MOS transistor N1
The threshold voltage of is also reduced. As shown in FIG. 9, the leak current has an exponentially increasing characteristic with respect to a decrease in threshold voltage. Therefore, as the manufacturing process becomes finer, the operating point bias voltage greatly changes, and oscillation stop easily occurs. The problem occurs.

The present invention has been made in view of the above problems, and provides a temperature-compensated input circuit and a temperature-compensated oscillator circuit capable of suppressing fluctuations in operating point bias voltage due to leak current. With the goal.

[0011]

A temperature-compensated input circuit according to the present invention comprises an input circuit having an input end having a predetermined impedance, an output end connected to the input end, and a voltage at the input end serving as a reference voltage. And a temperature compensating circuit for controlling the temperature to be equal to each other.

Further, the temperature compensation circuit includes a reference voltage source for generating the reference voltage, a low pass filter for removing an AC component from the voltage at the input terminal, an output of the reference voltage source and an output of the low pass filter. Is input, and an output transistor that adjusts the voltage at the output end by the output of the differential amplifier is provided.

The temperature compensating circuit includes a reference voltage source for generating the reference voltage, a P-channel transistor having a source terminal connected to a high-potential side power source and a drain terminal connected to the output terminal, and a source terminal. An N-channel transistor connected to a low-potential-side power supply and a drain end thereof connected to the output end, a low-pass filter whose input end is connected to the output end, and a non-inverting input end connected to the output end of the low-pass filter A first differential amplifier having an inverting input terminal connected to the reference voltage source and an output terminal connected to the gate terminal of the P-channel transistor, and a non-inverting input terminal connected to the output terminal of the low-pass filter A second differential amplifier having an end connected to the reference voltage source and an output end connected to the gate end of the N-channel transistor.

The temperature compensating circuit includes a reference voltage source for generating the reference voltage, an N-channel transistor having a drain terminal connected to a high potential side power source and a source terminal connected to the output terminal, and a drain terminal. A P-channel transistor connected to the low-potential-side power source and a source end connected to the output end, a low-pass filter whose input end is connected to the output end, and an inverting input end connected to the output end of the low-pass filter A first differential amplifier having an inverting input terminal connected to the reference voltage source and an output terminal connected to the gate terminal of the N-channel transistor; and an inverting input terminal connected to the output terminal of the low-pass filter and a non-inverting input A second differential amplifier having an end connected to the reference voltage source and an output end connected to the gate end of the P-channel transistor.

The temperature compensating circuit includes a reference voltage source for generating the reference voltage, a P-channel transistor having a source terminal connected to a high-potential side power source and a drain terminal connected to the output terminal, and a source terminal. An N-channel transistor connected to a low-potential-side power supply and a drain end thereof connected to the output end, a low-pass filter whose input end is connected to the output end, and a non-inverting input end connected to the output end of the low-pass filter An inverting input terminal is connected to the reference voltage source, and an output signal is output from the gate terminal of the P-channel transistor and the N-type transistor.
And a differential amplifier applied to the gate terminal of the channel transistor.

The temperature compensating circuit includes a reference voltage source for generating the reference voltage, an N-channel transistor having a drain terminal connected to a high-potential side power source and a source terminal connected to the output terminal, and a drain terminal. A P-channel transistor connected to the low-potential-side power source and a source end connected to the output end, a low-pass filter whose input end is connected to the output end, and an inverting input end connected to the output end of the low-pass filter An inverting input terminal is connected to the reference voltage source, and an output signal is output from the gate terminal of the N-channel transistor and the P terminal.
And a differential amplifier applied to the gate terminal of the channel transistor.

Further, it is characterized in that an overvoltage protection circuit connected to the input terminal is provided.

Further, the temperature-compensated oscillator circuit of the present invention is
An inverter, a feedback resistor connected between an input end and an output end of the inverter, a piezoelectric vibrator connected between the input end and the output end, and a first connected to the input end Capacitor, a second capacitor connected to the output end, and a temperature compensation circuit having an output end connected to the input end and controlling the voltage of the input end to be equal to a reference voltage. Is characterized by.

Further, it is characterized in that an overvoltage protection circuit connected to the input terminal is provided.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a temperature compensation type input circuit according to a first embodiment of the present invention. As shown in FIG. 1, the temperature-compensated input circuit according to the first embodiment of the present invention includes an input terminal 1, an input circuit 2, a temperature-compensated circuit 3,
Equipped with.

The input terminal 1 is a terminal provided on a semiconductor integrated circuit chip to which an external signal is input, and the input circuit 2
Is a circuit block having a predetermined high impedance input end, and the input end of the input circuit 2 is connected to the input terminal 1.

The temperature compensating circuit 3 has its output end connected to the input end of the input circuit 2 and controls the voltage at the input end of the input circuit 2 to be equal to the reference voltage of the temperature compensating circuit 3.

Therefore, even when the operating point bias voltage at the input end of the input circuit 2 fluctuates due to the leak current, the fluctuation is suppressed by the temperature compensating circuit 3,
The input circuit 2 can operate normally.

FIG. 2 is a configuration diagram of a temperature compensation type oscillation circuit as a specific configuration of the temperature compensation type input circuit of the first embodiment of the present invention shown in FIG. As shown in FIG. 2, the temperature-compensated oscillator circuit includes an input terminal 1, an input circuit 2, a temperature compensation circuit 3, an output terminal 4, a crystal oscillator 5 as a piezoelectric oscillator, a capacitor 6, and Capacitor 7 and ESD
A protection circuit 8 and a Schmitt circuit 9 are provided.

The output terminal 4 is a terminal for outputting a signal to the outside of the semiconductor integrated circuit chip. A crystal oscillator 5 outside the semiconductor integrated circuit chip is connected between the input terminal 1 and the output terminal 4 to adjust the phase. A capacitor 6 for connection is connected between the input terminal 1 and the low potential side power supply VSS, and a capacitor 7 for phase adjustment is connected between the output terminal 4 and the low potential side power supply VSS.

The input circuit 2 includes an ESD protection circuit 21 and a C
The MOS inverter 22 and the feedback resistor 23 are provided.

The input terminal of the CMOS inverter 22 as the input terminal of the input circuit 2 is connected to the input terminal 1, and the CMOS
The output end of the inverter 22 is connected to the output terminal 4, and the feedback resistor 23 is connected to the input end of the CMOS inverter 22 and the CMOS.
It is connected to the output terminal of the inverter 22.

The ESD protection circuit 21 is connected to the input terminal of the CMOS inverter 22, and the ESD protection circuit 8 is connected to the CMOS.
It is connected to the output terminal of the inverter 22.

The ESD protection circuit 21 discharges the overvoltage due to static electricity applied to the input terminal 1 to the high potential side power supply VDD or the low potential side power supply VSS, and the ESD protection circuit 8 eliminates the overvoltage due to static electricity applied to the output terminal 4. High potential side power supply V
The input circuit 2 is protected by discharging to DD or the low potential side power supply VSS.

ESD protection circuit 2 as an overvoltage protection circuit
Reference numeral 1 denotes a P-channel MOS transistor P1 having a gate end and a source end connected to the high potential side power supply VDD and a drain end connected to the input end of the CMOS inverter 22, and a gate end and a source end connected to the low potential side power supply VSS. And an N-channel MOS transistor N1 having a drain end connected to the input end of the CMOS inverter 22.

ESD protection circuit 8 as an overvoltage protection circuit
Is a P-channel MOS transistor P2 having a gate end and a source end connected to the high potential side power supply VDD and a drain end connected to the output end of the CMOS inverter 22, and a gate end and a source end connected to the low potential side power supply VSS. N whose drain end is connected to the output end of the CMOS inverter 22
And a channel MOS transistor N2.

The input end of the Schmitt circuit 9 is connected to the output end of the CMOS inverter 22, and the CMOS inverter 2
The oscillation signal obtained from the output terminal 2 is waveform-shaped by the Schmitt circuit 9 having a noise removing function at the time of oscillation start, and is supplied to an internal circuit (not shown) as a clock signal.

The temperature compensation circuit 3 is a CMOS inverter 3
1, a differential amplifier 32, a differential amplifier 33, a low-pass filter 34, a P-channel MOS transistor P3
And an N-channel MOS transistor N3.

Here, the differential amplifier 32 and the differential amplifier 3
3 does not need to be a wide band amplifier, but may be a direct current amplifier, and can be a low power consumption type.

The input terminal and the output terminal of the CMOS inverter 31 are connected to form a reference voltage source, and the reference voltage is generated from the output terminal of the CMOS inverter 31.

Here, the temperature compensating circuit 3 does not change the operating point bias voltage of the CMOS inverter 22 in the most stable oscillation state when the leak current does not occur in the ESD protection circuit 21. To C
Reference voltage from the output terminal of the MOS inverter 31 and CMO
In order to equalize and balance the operating point bias voltage of the S inverter 22, the transistor size of the CMOS inverter 31 and the transistor size of the CMOS inverter 22 are set to be the same.

The low-pass filter 34 comprises a resistor 35 and a capacitor 36 which constitute an RC type filter, the resistor 35 is connected between the input end and the output end of the low-pass filter 34, and the capacitor 36 is connected to the low-pass filter 34. Is connected to the output terminal of the low potential power supply VSS.

Since an oscillating sine wave is generated at the input end of the CMOS inverter 22, the low pass filter 3
The cutoff frequency fL of 4 (fL = 1 / 2πCR, C is the capacitance of the capacitor 36, and R is the resistance value of the resistor 35) is set sufficiently lower than the oscillation frequency fOSC of the CMOS inverter 22.

As an example, fOSC = 32 KHz, fL
= 3200 Hz, C = 10 PF and R = 5 MΩ, so that it can be built in the semiconductor integrated circuit chip.

The source end of the P-channel MOS transistor P3 is connected to the high potential side power supply VDD, and the P-channel MO transistor P3 is connected.
The drain end of the S transistor P3 is connected to the output end of the temperature compensation circuit 3, and the output end of the temperature compensation circuit 3 is connected to the input end of the input circuit 2.

The source end of the N-channel MOS transistor N3 is connected to the low potential side power source VSS, and the N-channel MO transistor N3 is connected.
The drain end of the S transistor N3 is connected to the output end of the temperature compensation circuit 3.

The input end of the low-pass filter 34 is connected to the output end of the temperature compensation circuit 3, the non-inverting input end of the differential amplifier 32 is connected to the output end of the low-pass filter 34, and the inverting input end of the differential amplifier 32 is connected. It is connected to the output end of the CMOS inverter 31 and the output end of the differential amplifier 32 is connected to the gate end of the P-channel MOS transistor P3.

The non-inverting input terminal of the differential amplifier 33 is connected to the output terminal of the low pass filter 34, the inverting input terminal of the differential amplifier 33 is connected to the output terminal of the CMOS inverter 31, and the output terminal of the differential amplifier 33 is connected. It is connected to the gate end of N-channel MOS transistor N3.

Here, the P-channel MOS transistor P
3 and the N-channel MOS transistor N3 are connected to the input terminal of the CMOS inverter 22 in parallel with the ESD protection circuit 21, so that the leak currents of the P-channel MOS transistor P3 and the N-channel MOS transistor N3 can be ignored. The sizes of the P-channel MOS transistor P3 and the N-channel MOS transistor N3 are set sufficiently smaller than the sizes of the P-channel MOS transistor P1 and the N-channel MOS transistor N1.

As an example, the channel width of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is 500 μm to 10 μm in order to secure an electrostatic discharge withstand capacity of 2000 V in the human body model and 200 V or more in the machine model as the discharge model.
Since about 100 μm is required, the size of the P-channel MOS transistor P3 and the N-channel MOS transistor N3 is set to about 1/10 to 1/100 of that size.

Next, the operation will be described. First, when the power is turned on, the CMOS inverter 22 functions as an inverter amplifier. Therefore, the operating point bias voltage at the input end of the CMOS inverter 22 is self-biased by the feedback resistor 23, so that the gain (output voltage change amount) as the inverter amplifier is generated. / Input voltage change amount) is stabilized at the threshold voltage of the CMOS inverter 22 which is maximum, and oscillation is started at the resonance frequency of the crystal resonator 5 by the gain of the inverter amplifier and the phase adjustment by the capacitors 6 and 7.

In a normal state in which no overvoltage is applied due to static electricity, N channel MOS transistor N1, P channel MOS transistor P1, N channel MOS transistor N2 and P channel MOS transistor P2 are all in the off state.

Further, when no leak current is generated in the source / drain path of the N-channel MOS transistor N1 or the P-channel MOS transistor P1 of the ESD protection circuit 21, the operating point bias voltage at the input end of the CMOS inverter 22 is DC. Since it is a voltage, it is directly output to the output end of the low-pass filter 34 and input to the non-inverting input end of the differential amplifier 32. Since the voltage at the non-inverting input end and the reference voltage at the inverting input end are equal, The output becomes the high-potential-side power supply VDD level, and the P-channel MOS
The transistor P3 is turned off.

Similarly, the operating point bias voltage at the input end of the CMOS inverter 22 is directly output to the output end of the low-pass filter 34 and input to the non-inverting input end of the differential amplifier 33, and the voltage at the non-inverting input end and the inverting input. Since the reference voltage at the end is equal, the output of the differential amplifier 33 is
Becomes SS level and N-channel MOS transistor N3
Is also turned off.

Next, the N channel M of the ESD protection circuit 21
Taking a state where a leak current is generated in the source / drain path of the OS transistor N1 as an example, the CMOS inverter 22
Since the input terminal of is high impedance, the leak current is supplied from the output terminal of the CMOS inverter 22, and the operating point bias voltage of the input terminal of the CMOS inverter 22 starts to decrease due to the voltage drop of the feedback resistor 23.

Then, the operating point bias voltage at the input end of the CMOS inverter 22 is output to the output end of the low-pass filter 34 as it is, so that the voltage at the non-inverting input end of the differential amplifier 32 decreases and the differential amplifier 32 has a negative voltage. The output voltage decreases, the P-channel MOS transistor P3 transitions to the ON state, and the leak current of the source / drain path of the N-channel MOS transistor N1 is supplied, and the output of the differential amplifier 33 is the low-potential-side power supply VSS level. As it is, the N-channel MOS transistor N3 remains off.

Therefore, the operating point bias voltage at the input end of the CMOS inverter 22 returns to the voltage in the state where there is no leakage current, and fluctuations in the operating point bias voltage at the input end of the CMOS inverter 22 are suppressed, so that a stable oscillation state is achieved. Is maintained.

On the other hand, the P channel M of the ESD protection circuit 21
Taking a state in which a leak current is generated in the source / drain path of the OS transistor P1 as an example, the operating point bias voltage at the input end of the CMOS inverter 22 starts to rise due to the voltage drop of the feedback resistor 23.

Then, the operating point bias voltage at the input end of the CMOS inverter 22 is output as it is to the output end of the low-pass filter 34, so that the voltage at the non-inverting input end of the differential amplifier 33 rises and the differential amplifier 33's voltage rises. The output voltage rises, the N-channel MOS transistor N3 transitions to the ON state to absorb the leak current in the source / drain path of the P-channel MOS transistor P1, and the output of the differential amplifier 32 is at the high-potential-side power supply VDD level. As it is, the P-channel MOS transistor P3 remains in the off state.

Therefore, the operating point bias voltage at the input end of the CMOS inverter 22 returns to the voltage in the state where there is no leakage current, and fluctuations in the operating point bias voltage at the input end of the CMOS inverter 22 are suppressed, so that a stable oscillation state is achieved. Is maintained.

As described above, according to the temperature-compensated input circuit of the first embodiment of the present invention and the temperature-compensated oscillator circuit as a specific configuration thereof, the input circuit 2 having the input terminal of high impedance is provided. And a temperature compensation circuit 3 whose output end is connected to the input end of the input circuit 2 and which controls the voltage at the input end of the input circuit 2 to be equal to the reference voltage. 3 is a CMOS inverter 31 as a reference voltage source for generating a reference voltage
And a low-pass filter 34 for removing an AC component from the voltage at the input end of the input circuit 2, and a differential amplifier 32 and a differential amplifier to which the output of the CMOS inverter 31 as the reference voltage source and the output of the low-pass filter 34 are input. 33, a P-channel MOS transistor P3 and an N-channel M as output transistors for adjusting the voltage at the output end of the temperature compensation circuit 3 by the outputs of the differential amplifier 32 and the differential amplifier 33.
Since the OS transistor N3 is provided, it is possible to realize a temperature-compensated input circuit and a temperature-compensated oscillator circuit that can suppress fluctuations in the operating point bias voltage due to leak current.

Although the above description has been made on the temperature compensation type oscillation circuit, the effect of the temperature compensation circuit is not limited to this, and a high impedance such as an inverter amplifier in which a feedback resistor is connected to a CMOS inverter is used. Similar effects can be obtained for various circuit blocks having the input ends of

Next, FIG. 3 is a configuration diagram of a temperature compensation type input circuit of the second embodiment of the present invention. As shown in FIG. 3, the temperature compensation type input circuit according to the second embodiment of the present invention includes an input terminal 1, an input circuit 2, and a temperature compensation circuit 10.
And

The input terminal 1 is a terminal provided on a semiconductor integrated circuit chip to which an external signal is input, and the input circuit 2
Is a circuit block having a high impedance input end, and the input end of the input circuit 2 is connected to the input terminal 1.

In the temperature compensating circuit 10, the output end is the input circuit 2
Of the input circuit 2 and the input voltage of the input circuit 2 are controlled to be equal to the reference voltage of the temperature compensating circuit 10.

Therefore, even when the operating point bias voltage at the input end of the input circuit 2 fluctuates due to the leakage current, the temperature compensating circuit 10 suppresses the fluctuation and the input circuit 2 operates normally. You can

The configuration of the temperature compensation type input circuit of the second embodiment of the present invention shown in FIG. 3 and the temperature compensation type input circuit of the first embodiment of the present invention shown in FIG. The difference from the temperature compensation oscillation circuit shown in FIG.
This is a part in which the temperature compensating circuit 3 is changed to the temperature compensating circuit 10, and the same components are designated by the same reference numerals and the description thereof is omitted.

The temperature compensating circuit 10 has a CMOS inverter 31 whose input and output terminals are connected as a reference voltage source for generating a reference voltage, a drain terminal which is connected to the high potential side power source VDD, and a source terminal which is the output of the temperature compensating circuit 10. N connected to the end
The channel MOS transistor N4 and the drain end are connected to the low-potential-side power supply VSS and the source end is the temperature compensation circuit 10.
P-channel MOS transistor P connected to the output terminal of
4, a low-pass filter 34 whose input end is connected to the output end of the temperature compensation circuit 10, an inverting input end connected to the output end of the low-pass filter 34, and a non-inverting input end connected to the output end of the CMOS inverter 31 N channel MO at the end
A differential amplifier 101 connected to the gate terminal of the S-transistor N4, an inverting input terminal connected to the output terminal of the low-pass filter 34, a non-inverting input terminal connected to the output terminal of the CMOS inverter 31, and an output terminal connected to the P-channel MOS transistor. A differential amplifier 102 connected to the gate end of P4.

The low-pass filter 34 includes a resistor 35 and a capacitor 36 which form an RC type filter, the resistor 35 is connected between the input end and the output end of the low-pass filter 34, and the capacitor 36 is connected to the low-pass filter 34. Is connected to the output terminal of the low potential power supply VSS.

As described above, the P channel MO shown in FIG.
The S transistor P3 is replaced by an N channel MOS transistor N
4 and replace the N-channel MOS transistor N3 with P
Since the channel polarity of the transistor is inverted by replacing it with the channel MOS transistor P4, the differential amplifier 32 and the differential amplifier 33 shown in FIG. 2 are replaced with the differential amplifier 101 and the differential amplifier 102, and the polarity of the input terminal is changed. Inverted.

Therefore, according to the temperature-compensated input circuit of the second embodiment of the present invention, the temperature-compensated input circuit and the temperature-compensated oscillator circuit capable of suppressing the fluctuation of the operating point bias voltage due to the leak current. Can be realized.

Next, FIG. 4 is a configuration diagram of a temperature compensation type input circuit of the third embodiment of the present invention. As shown in FIG. 4, the temperature compensation type input circuit according to the third embodiment of the present invention includes an input terminal 1, an input circuit 2, and a temperature compensation circuit 11.
And

The input terminal 1 is a terminal provided on a semiconductor integrated circuit chip to which an external signal is input, and the input circuit 2
Is a circuit block having a high impedance input end, and the input end of the input circuit 2 is connected to the input terminal 1.

The output terminal of the temperature compensating circuit 11 is the input circuit 2
Of the input circuit 2 and the input voltage of the input circuit 2 are controlled to be equal to the reference voltage of the temperature compensation circuit 11.

Therefore, even when the operating point bias voltage at the input end of the input circuit 2 fluctuates due to the leak current, the temperature compensating circuit 11 suppresses the fluctuation and the input circuit 2 operates normally. You can

The configuration of the temperature compensation type input circuit of the third embodiment of the present invention shown in FIG. 4 and the temperature compensation type input circuit of the first embodiment of the present invention shown in FIG. The difference from the temperature compensation oscillation circuit shown in FIG.
This is a part in which the temperature compensating circuit 3 is changed to the temperature compensating circuit 11, and the same components are designated by the same reference numerals and the description thereof is omitted.

The temperature compensating circuit 11 has a CMOS inverter 31 whose input and output terminals are connected as a reference voltage source for generating a reference voltage, a source terminal which is connected to the high potential side power supply VDD, and a drain terminal which is the output of the temperature compensating circuit 11. P connected to the end
The channel MOS transistor P3 and the source end are connected to the low-potential-side power supply VSS and the drain end is the temperature compensation circuit 11.
N-channel MOS transistor N connected to the output terminal of
3, a low-pass filter 34 whose input end is connected to the output end of the temperature compensation circuit 11, a non-inverting input end connected to the output end of the low-pass filter 34, and an inverting input end connected to the output end of the CMOS inverter 31. A differential amplifier 111 is provided, in which one of the double output signals of the same polarity is applied to the gate terminal of the P-channel MOS transistor P3, and the other of the double output signals is applied to the gate terminal of the N-channel MOS transistor N3.

The low-pass filter 34 comprises a resistor 35 and a capacitor 36 which form an RC filter, the resistor 35 is connected between the input end and the output end of the low-pass filter 34, and the capacitor 36 is connected to the low-pass filter 34. Is connected to the output terminal of the low potential power supply VSS.

As described above, the differential amplifier 32 shown in FIG.
The differential amplifier 33 is replaced with the differential amplifier 111 having two output terminals to reduce the number of elements.

Therefore, according to the temperature compensation type input circuit of the third embodiment of the present invention, the number of elements is reduced and the variation of the operating point bias voltage due to the leak current can be suppressed. And a temperature compensation type oscillation circuit can be realized.

Next, FIG. 5 is a configuration diagram of a temperature compensation type input circuit according to the fourth embodiment of the present invention. As shown in FIG. 5, the temperature compensation type input circuit according to the fourth embodiment of the present invention includes an input terminal 1, an input circuit 2, and a temperature compensation circuit 12.
And

The input terminal 1 is a terminal provided on the semiconductor integrated circuit chip to which an external signal is input, and the input circuit 2
Is a circuit block having a high impedance input end, and the input end of the input circuit 2 is connected to the input terminal 1.

The output terminal of the temperature compensating circuit 12 is the input circuit 2
Connected to the input terminal of the temperature control circuit 12 and controls the voltage of the input terminal of the input circuit 2 to be equal to the reference voltage of the temperature compensation circuit 12.

Therefore, even when the operating point bias voltage at the input end of the input circuit 2 fluctuates due to the leak current, the temperature compensating circuit 12 suppresses the fluctuation and the input circuit 2 operates normally. You can

The configuration of the temperature compensation type input circuit of the fourth embodiment of the present invention shown in FIG. 5 and the temperature compensation type input circuit of the first embodiment of the present invention shown in FIG. The difference from the temperature compensation oscillation circuit shown in FIG.
This is a part in which the temperature compensating circuit 3 is changed to the temperature compensating circuit 12, and the same components are designated by the same reference numerals and the description thereof is omitted.

The temperature compensating circuit 12 has a CMOS inverter 31 whose input and output terminals are connected as a reference voltage source for generating a reference voltage, a drain terminal which is connected to the high potential side power source VDD, and a source terminal which is the output of the temperature compensating circuit 12. N connected to the end
The channel MOS transistor N4 and the drain end are connected to the low-potential-side power supply VSS and the source end is the temperature compensation circuit 12
P-channel MOS transistor P connected to the output terminal of
4, an input terminal connected to the output terminal of the temperature compensation circuit 12, a low-pass filter 34 connected to the output terminal of the low-pass filter 34, an inverting input terminal connected to the output terminal of the CMOS inverter 31, The differential amplifier 121 is provided with one of the double output signals having the same polarity applied to the gate end of the N-channel MOS transistor N4 and the other of the double output signals applied to the gate end of the P-channel MOS transistor P4.

The low-pass filter 34 comprises a resistor 35 and a capacitor 36 which form an RC type filter, the resistor 35 is connected between the input end and the output end of the low-pass filter 34, and the capacitor 36 is connected to the low-pass filter 34. Is connected to the output terminal of the low potential power supply VSS.

As described above, the differential amplifier 32 shown in FIG.
2 is replaced with a differential amplifier 121 having two output terminals to reduce the number of elements, and FIG.
The P-channel MOS transistor P3 shown in FIG.
The transistor N3 is a P-channel MOS transistor P4
2 and the channel polarity of the transistor is inverted, the differential amplifier 32 shown in FIG.
To replace the polarity at the input end.

Therefore, according to the temperature compensation type input circuit of the fourth embodiment of the present invention, the number of elements is reduced and the variation of the operating point bias voltage due to the leak current can be suppressed. And a temperature compensation type oscillation circuit can be realized.

[0085]

The effect of the present invention is that it is possible to realize a temperature-compensated input circuit and a temperature-compensated oscillator circuit which can suppress the fluctuation of the operating point bias voltage due to the leak current.

[0086]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a temperature-compensated input circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a temperature-compensated oscillator circuit as a specific configuration of the temperature-compensated input circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a temperature compensation type input circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a temperature compensation type input circuit according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a temperature compensation type input circuit according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional crystal oscillation circuit.

FIG. 7 is an input / output characteristic diagram of an inverter amplifier.

FIG. 8 is a temperature characteristic diagram of leakage current.

FIG. 9 is a threshold voltage characteristic diagram of leakage current.

[Explanation of symbols]

1 input terminal 2 input circuits 21 ESD protection circuit 22 CMOS inverter 23 Feedback resistor 3 Temperature compensation circuit 31 CMOS inverter 32 differential amplifier 33 differential amplifier 34 Low-pass filter 35 resistance 36 capacitors 4 output terminals 5 Crystal unit 6 capacitors 7 capacitors 8 ESD protection circuit 9 Schmidt circuit 10 Temperature compensation circuit 101 differential amplifier 102 differential amplifier 11 Temperature compensation circuit 111 differential amplifier 12 Temperature compensation circuit 121 differential amplifier N1 N-channel MOS transistor N2 N channel MOS transistor N3 N-channel MOS transistor N4 N channel MOS transistor P1 P-channel MOS transistor P2 P-channel MOS transistor P3 P-channel MOS transistor P4 P-channel MOS transistor

Claims (9)

[Claims] 1. An input circuit having an input end having a predetermined impedance, and a temperature compensation circuit having an output end connected to the input end and controlling the voltage of the input end to be equal to a reference voltage. A temperature-compensated input circuit characterized by: 2. The temperature compensation circuit includes a reference voltage source for generating the reference voltage, a low-pass filter for removing an AC component from the voltage at the input terminal, an output of the reference voltage source and an output of the low-pass filter. The temperature-compensated input circuit according to claim 1, further comprising: a differential amplifier to which is input, and an output transistor that adjusts a voltage at the output end by an output of the differential amplifier. 3. The temperature compensating circuit includes a reference voltage source for generating the reference voltage, a P-channel transistor having a source end connected to a high-potential-side power supply and a drain end connected to the output end, and a source end. An N-channel transistor connected to a low-potential-side power supply and a drain end thereof connected to the output end, a low-pass filter whose input end is connected to the output end, and a non-inverting input end connected to the output end of the low-pass filter A first differential amplifier having an inverting input terminal connected to the reference voltage source and an output terminal connected to the gate terminal of the P-channel transistor, and a non-inverting input terminal connected to the output terminal of the low-pass filter 2. A second differential amplifier having an end connected to the reference voltage source and an output end connected to the gate end of the N-channel transistor. The temperature-compensated input circuit described. 4. The temperature compensating circuit includes a reference voltage source for generating the reference voltage, an N-channel transistor having a drain end connected to a high-potential side power source and a source end connected to the output end, and a drain end. A P-channel transistor connected to a low-potential-side power supply and a source end connected to the output end, a low-pass filter whose input end is connected to the output end, and an inverting input end connected to the output end of the low-pass filter A first differential amplifier having an inverting input terminal connected to the reference voltage source and an output terminal connected to the gate terminal of the N-channel transistor; and an inverting input terminal connected to the output terminal of the low-pass filter and a non-inverting input 2. A second differential amplifier having an end connected to the reference voltage source and an output end connected to the gate end of the P-channel transistor. The temperature-compensated input circuit described. 5. The temperature compensation circuit includes a reference voltage source for generating the reference voltage, a P-channel transistor having a source end connected to a high-potential-side power supply and a drain end connected to the output end, and a source end An N-channel transistor connected to a low-potential-side power supply and a drain end thereof connected to the output end, a low-pass filter whose input end is connected to the output end, and a non-inverting input end connected to the output end of the low-pass filter 2. The differential amplifier according to claim 1, further comprising: a differential amplifier having an inverting input terminal connected to the reference voltage source and an output signal applied to the gate terminal of the P-channel transistor and the gate terminal of the N-channel transistor. Temperature compensated input circuit. 6. The temperature compensation circuit includes a reference voltage source for generating the reference voltage, an N-channel transistor having a drain end connected to a high-potential-side power supply and a source end connected to the output end, and a drain end. A P-channel transistor connected to the low-potential-side power source and a source end connected to the output end, a low-pass filter whose input end is connected to the output end, and an inverting input end connected to the output end of the low-pass filter 2. The differential amplifier according to claim 1, further comprising: a differential amplifier having an inverting input terminal connected to the reference voltage source and an output signal applied to the gate terminal of the N-channel transistor and the gate terminal of the P-channel transistor. Temperature compensated input circuit. 7. The temperature compensated input circuit according to claim 1, further comprising an overvoltage protection circuit connected to the input terminal. 8. An inverter, a feedback resistor connected between an input end and an output end of the inverter, a piezoelectric vibrator connected between the input end and the output end, and an input end connected to the piezoelectric vibrator. A first capacitor connected, a second capacitor connected to the output end, and a temperature compensation circuit having an output end connected to the input end and controlling the voltage of the input end to be equal to a reference voltage. And a temperature-compensated oscillation circuit. 9. The temperature-compensated oscillator circuit according to claim 8, further comprising an overvoltage protection circuit connected to the input terminal.