JP2003132013A - Transition signal control circuit and arbitration apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an asynchronous transition signal control circuits, capable of applying to a bus arbitration apparatus, etc. SOLUTION: An OR gate 41-1 maintains a token (a feedback signal S) so long as a device grant signal 'Grant' has been outputting, even after a Muller C element with invertor 10-1 dropped an output of a response event AckOut as a result of being dropped of a request event ReqIn. If a device request signal Req is not output, the feedback signal S is passed through an AND gate 41-2 and a request event ReqOut is output from the AND gate 41-2. At the same time, the grant signal Grant is stopped to output and a loop composed of a Muller C element with invertor 10-2, the OR gate 41-1 and an AND gate 41-3 is cancelled. As a result of this cancellation, the token (the feedback signal S) is handed to a next transition signal control circuit, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transition signal control circuit of a new circuit type which is used in pipeline control or the like and which is configured by a Muller C element, and when a predetermined resource such as a bus using the transition signal control circuit is jointly used. The present invention relates to an arbitration device that arbitrates device competition.

[0002]

2. Description of the Related Art Conventionally, as a technique related to such a field, for example, there is one described in the following documents. Reference 1: 1988 ACM Turing Award Winning Commemorative Lecture (Ivan E. Sutherland: Micr, described in magazine "bit", vol.22, No.3, Kyoritsu Shuppan Co., Ltd., P.246-268.
opipelines, CACM, Vol.32, No.6, pp.720-378) Reference 2: Japanese Patent Laid-Open No. 6-90165, Reference 3: Japanese Patent Laid-Open No. 6-96019, Reference 4: Japanese Patent Laid-Open No. 6-244890 : Japanese Patent Laid-Open No. 11-3206

For example, as described in Reference 1,
In recent years, traditional clocked logic
The transition signal control (transition s
ignalling) was introduced. This is an area of Asyncronous Design Methodologies.

The conventional clock control logic is based on the premise that all signals are binary and the time can be discretized. This means that Boolean logic, which is a logic that represents the input condition and the result of the logic circuit by an algebraic expression, can be applied, which has the effect of facilitating the circuit design even in a relatively large-scale circuit. Even in the asynchronous design method, all signals are binary,
This time differs from the conventional clock control logic in that the time is not standardized. As a result, the following three advantages have been pointed out.

The first advantage is that the clock sk
(w)), for example, the occurrence of so-called glitch in a large-scale circuit can be suppressed.

The second advantage is that the power consumption is large because the clock control logic constantly operates the clock in an unnecessary portion of the logic operation. However, the asynchronous design method requires the calculation. Since only a part needs to be operating, its power consumption can be suppressed.

A third advantage is that in the clock control logic, the overall speed is governed by the critical path (longest path), but the asynchronous design method can secure an average speed.

The transition signal control circuit includes an event (event,
Event)) to form a logical combination. In transition signal control, rising transition and falling transition of a signal have the same meaning, and these rising transition and falling transition are called an event. In the transition signal control, the rising transition and the falling transition are not distinguished, and both the rising edge and the falling edge are used as trigger events, so that it is possible to potentially realize twice as high speed as the conventional clock control.

As described in Reference 1, for example,
The Muller C element is one of transition signal control circuits, and is a logical product (hereinafter referred to as “AND”) of transition events.
Provide the function. In addition to this, the transition signal control includes an exclusive OR (hereinafter referred to as "XOR") element and a toggle (TOGGLE) element that provide a logical sum (hereinafter referred to as "OR") function for a transition event.

7A and 7B are explanatory views of a conventional Muller C element with an inverter, which is one of transition signal control circuits. FIG. 7A is a logical symbol diagram and FIG. 7B. Is a logic circuit diagram. This Muller C element with an inverter 10
Transition signals, for example, two request events ReqIn1, Req
An element that inputs In2 and outputs a request event ReqOut1 that is a transition signal. The inverters 11 and 2 are for signal inversion.
The input AND gates 12, 13, 14 and the 3-input OR gate 15 are included.

The request event ReqIn 2 that is input is inverted by the inverter 11, and the AND gate 1 is connected to this output terminal.
3, 14 are connected. Request event ReqIn1, Req
Out1 is input to the AND gate 12. The request event ReqIn1 and the output signal of the inverter 11 are input to the AND gate 13. The output signal of the inverter 11 and the request event ReqOut1 are input to the AND gate 14.
These AND gates 12, 13, 14 are connected to an OR gate 15, and the request event RegOut1 is output from the output terminal of the OR gate 15. A
The ND gate 12 and the OR gate 15 form a latch circuit, and the AND gate 14 and the OR gate 15 form a latch circuit.

Muller C element 10 with such an inverter
Then, when the two input request events ReqIn1 and ReqIn2 have different values (for example, logic “H” and “L”), the output request event ReqOut1 becomes the request event.
The same value as ReqIn 1 is output from the OR gate 15, and this value is applied to the AND gate 12 and the OR when any of the input request events ReqIn 1 and ReqIn 2 changes thereafter.
Latch circuit by gate 15 or AND gate 1
4 and the OR gate 15 holds the latch circuit.
When request events ReqIn 1 and ReqIn 2 of two inputs both have the same value (for example, logic “H” and “H” or logic “L” and “L”), and then one of the inputs changes. As the output request event ReqOut 1, the same value as the request event ReqIn 1 is output from the OR gate 15.

Two input request events ReqIn 1 and Req
It is not assumed that both In 2 change at the same time as in the reset / set type flip-flop (Flip-Flop).

As mentioned above, in general, ReqIn 1, ReqI
Transition signals such as n 2 and ReqOut 1 can be prompted as an event for the logic device and the Muller C element acts as an AND gate for that event. On the other hand, the Muller C element with an inverter transmits the event only when an event of different logic occurs in both inputs. This is the basis for creating a directional flow of events.

As described in Document 1, a pipeline is a data flow and is processed in an operational manner. In this pipeline, data is stored and processed.
The pipeline operates by clock control (each unit operates according to a clock distributed from the outside) or event drive (each unit operates independently each time a local event occurs).

Some pipelines are inelastic.
astic), and the amount of data inside the pipeline is fixed. In an inelastic pipeline, the input and output speeds must match exactly, which behaves like a shift register when processing logic is removed. On the other hand, in an elastic pipeline, the amount of data inside the pipeline is variable, and the speed of input and output may change momentarily due to buffering. When the processing logic is removed, the elastic pipeline operates as a FIFO (First-In First-Out) memory. An event-driven and elastic pipeline with or without a simple structure (with or without internal processing) is called a micropipeline.

FIG. 8 is a conceptual diagram showing a control circuit of a conventional micro pipeline described in Document 1 and the like. The control circuit of this micro pipeline is the left side block 20.
-1 and the right block 20-2. The left block 20-1 is a request event Req (1) which is a transition signal and the response event which is a transition signal from the right block 20-2.
Input Ack (2), Muller with inverter similar to Fig. 7
It has a C element 10-1, and a response event that is a transition signal from the output terminal of the Muller C element 10-1 with an inverter.
Ack (1) is output. Muller C element with inverter 10-
The response event Ack (1) is output to the output terminal of 1 with delay time DELA.
Request event Req (2), which is a transition signal delayed by Y1
Is connected to the delay element 21-1.

Similarly, the right block 20-2 inputs the request event Req (2), which is a transition signal, and the response event Ack (3), which is a transition signal, to the Mu with inverter similar to FIG.
ller C element 10-2, and the Muller C element 10-1 with an inverter and the delay element 21-2 are connected to the output terminal. The delay element 21-2 is a Muller C with an inverter.
This is an element which receives the response event Ack (2) which is the transition signal output from the element 10-2, delays this by the delay time DELAY2, and outputs the request event Req (3) which is the transition signal.

In FIG. 8, the logic circuit controlled by the control circuit of this micro pipeline is omitted in the figure, but the flow of data passing through the logic circuit by the one-dot chain line (from input data Din to output data To Dout). Document 1 exemplifies a latch circuit, a decode circuit, and a multiplication circuit as logic circuits to be controlled.

FIG. 9 is a timing waveform chart showing the operation of the control apparatus for the micro pipeline shown in FIG. The operation of the control circuit of the micro pipeline shown in FIG. 8 will be described below with reference to FIG.

As described above, the control circuit of the micro pipeline of FIG. 8 is composed of a combination of two blocks, and the left block 20-1 and the right block 20-2.
Have the same circuit configuration.

For example, when a request event Req (1) occurs in the left block 20-1 (corresponding to logic "H"),
If the right block 20-2 is not yet activated and the response event Ack (2) has not occurred (corresponding to the logic “L”), the response event Ack (1) is output from the Muller C element with inverter 10-1. Occurs to gain control over a logic circuit not shown (this link is shown at L1 in FIG. 9). The response event Ack (1) is delayed by the delay element 21-1 by a constant delay time DELAY 1, and the right block 20-
Request event Req (2) for 2 (This link is
(L2 in FIG. 9).

Then, also in the right block 20-2, a response event Ack (2) is generated from the Muller C element 10-2 with an inverter and fed back to the Muller C element 10-1 with an inverter by the exactly same logic, so that the response event Ack ( 1) loses its control (this link is L3 and L in Figure 9)
5). That is, the response event Ack (1) generated from the inverter-equipped Muller C element 10-1 acquires control over the logic circuit (not shown) for the constant delay time DELAY 1 of the delay element 21-1, and then the control is performed by the inverter. The response event Ack (2) generated from the attached Muller C element 10-2 shifts.

The request event Req (1) itself also disappears in the left block 20-0 (not shown) after the delay time DELAY 0 of the delay element (not shown) (this is the link L4 in FIG. 9). It is shown). Similarly, the request event Req output from the delay element 21-1
(2) is the delay time DELAY1 in the left block 20-1.
After that, the event disappears (this is the link L in FIG. 9).
4).

However, when the request event Req (1) occurs in the left block 20-1, if the right block 20-2 has already been activated and the event Ack (2) has occurred, the Muller C element with inverter 10- Due to the property of 2, the response event Ack (1) does not change. This state is shown as an invalid link L3 (broken line) in the event Ack (2) # 1 and the event Ack (1) # 1 generated in the link L7 in FIG.

The disappearance of the response event Ack (2) is similar to the disappearance of the response event Ack (1), and the Mull with an inverter is included.
Upon receiving the response event Ack (3) input to the erC element 10-2, it disappears at the link L8 in FIG.

Here, the delay times DELAY 0 and DELAY of FIG.
The meaning of 1 and DELAY 2 is very important. If there is no delay time DELAYO, DELAY1, and DELAY2, the delay time of the logic circuit that is not shown in the figure cannot be secured, and the request event Req (1), ... And the response event Ack (1 ), ... run out of control, and as a result, asynchronous transition signal control cannot be realized.

According to the description of Document 1, the control circuit of FIG. 8 operates according to a simple stage state rule. That is, when the states of the preceding block 20-2 and the succeeding block 20-1 are different, the state of the preceding block 20-2 is transmitted to the succeeding block 20-1, and otherwise the current state is maintained. . And this stage state rule is inferred by a differential equation that defines ocean waves and electromagnetic waves. In fact, in the control circuit of the micro pipeline of FIG.
Muller with inverter in the loop where the event goes around
Since one inverter of the C elements 10-1 and 10-2 is included, each loop oscillates, the request event Req (1), etc. propagates to the right side of FIG. 8, and the response event Ack (1), etc. Propagate to the left side of FIG.

For example, referring to the timing waveform of FIG.
Response event ACK (1) transited to response event Ack (2).
As described above, the control circuit of FIG.
If there is an event in the right block 20-2, the operation is transmitted to the right block 20-2.
It can be seen as similar to FO. Here, the events are accumulated in the FIFO, and the events of the left block 20-1 are completed, so that the right block 20- is sequentially processed.
It is transmitted to 2, ... This operation as a whole favors the control of micropipelines.

[0030]

However, in the conventional micro-pipeline control circuit of FIG. 8, the application range of the asynchronous transition signal control using this is as described in (a) and (b) below. There was a problem that was narrow.

(A) In the control circuit of the micropipeline shown in FIG. 8, each has a constant delay time DELAY1 ,.
The control becomes effective only during the period, and then the control propagates to the subsequent blocks as if it were a wave. As long as the logic delay time of the logic circuit (not shown) to be controlled does not exceed the propagation time of the control, this asynchronous transition signal control works effectively. However, control propagation may not always be effective signal control. In general, a device such as a processor is composed of devices having various input / output interfaces. In addition, many devices cannot be incorporated in asynchronous transition signal control because the upper limit of the delay time is not fixed. Devices that require interrupt control, such as DMA (Direct Memory Access, direct data transfer between memories) and timers, correspond to this, and asynchronous transition signal control using the control circuit of the micro pipeline in FIG. 8 cannot be performed. .

(B) FIG. 10 is a schematic block diagram of a conventional general bus arbitrator. In this bus arbitration device, a plurality of N devices 30 such as memories are used.
-1 to 30-N are connected to the common bus 31, and the control circuit 32 performs arbitration for bus use. Device 30-
1 to 30-N output the device request signals Req1 to ReqN to the control circuit 32 when the common bus 31 is used.
The control circuit 32 arbitrates the competition of the device request signals Req1 to ReqN, and determines a certain device (30-1 to 30-N).
Device grant signal (Grant1 ~ G)
1 of the rant N), and the common bus 31 for a certain period of time.
To wait for the other device to be used.

The control circuit 32 of such a bus arbitration device
Consider the case where is configured by the control circuit of the micro pipeline in FIG. Device 30 using common bus 31-
The time in which 1 to 30-N occupies the common bus 31 is irregular depending on the devices 30-1 to 30-N. Therefore, it is generally considered unsuitable for such asynchronous transition signal control.

It is an object of the present invention to provide a transition signal control circuit which solves the problems of the above-mentioned prior art and realizes asynchronous transition signal control applicable to a bus arbitration device and the like, and an arbitration device using the same. And

[0035]

In the conventional control circuit of the micro-pipeline shown in FIG. 8, a control circuit is separated from a logic structure having a combination of a control signal and a logic circuit (not shown) to be controlled. By creating a logical structure, asynchronous transition signal control applicable to a bus arbitration device or the like can be realized. Therefore, the present invention proposes a circuit system based on a new concept in order to realize asynchronous transition signal control applicable to a bus arbitration device and the like.

That is, in the first aspect of the present invention, in the transition signal control circuit, the first Muller C with an inverter is used.
The element, the gate circuit, and the second Muller C element with an inverter are provided.

The first Muller C element with an inverter is
Outputs a first positive input terminal for inputting a first transition signal whose logic value transits, a first negative input terminal for inputting a feedback signal whose logic value transits, and a second transition signal whose logic value transits And a second output signal having the same logical value as the first transition signal when the first transition signal and the feedback signal have different logical values. It is an element which outputs from a terminal and holds the previous state when the first transition signal and the feedback signal have the same logical value.

The gate circuit has a first input terminal for inputting the second transition signal output from the first output terminal of the first Muller C element with an inverter, and a second input for inputting a control signal. ON by the terminal and the control signal,
It is a circuit having a second output terminal that outputs an output signal corresponding to the second transition signal when in the off state and in the on state.

Further, the second Muller C with an inverter
The element has a second positive input terminal for inputting the output signal output from the gate circuit, a second negative input terminal for inputting a third transition signal whose logic value transits, and the feedback signal for the second input terminal. 1 has a third output terminal for outputting to the first negative input terminal of the Muller C element with an inverter, and when the output signal of the gate circuit and the third transition signal have different logical values, the output signal is It is an element that outputs the feedback signal having the same logical value from the third output terminal and holds the previous state when the output signal of the gate circuit and the third transition signal have the same logical value.

The first aspect of the present invention is characterized by the logical structure of only control signals, and specifically introduces the concept of a token. Then, the token can be held in the loop constituted by the gate circuit which is turned on / off by the control signal and the second Muller C element with the inverter connected to the output side. A bus arbitration device or the like can be realized by using such a new asynchronous transition signal control circuit capable of passing tokens.

According to a second aspect of the present invention, in a transition signal control circuit, a first Muller C element with an inverter, a first gate circuit, a second Muller C element with an inverter, a third gate circuit, and a fourth gate circuit. And a gate circuit.

The first Muller C element with an inverter is
Similar to the first Muller C element with an inverter of the first invention, a first positive input terminal for inputting a first transition signal whose logic value transits, and a first positive input terminal for inputting a feedback signal whose logic value transits
Has a negative input terminal and a first output terminal for outputting a second transition signal whose logic value transits, and when the first transition signal and the feedback signal have different logic values, the first transition It is an element that outputs the second transition signal having the same logical value as that of the signal from the first output terminal, and holds the previous state when the first transition signal and the feedback signal have the same logical value.

Like the gate circuit of the first invention, the first gate circuit inputs the second transition signal output from the first output terminal of the first Muller C element with an inverter. 1 input terminal, a second input terminal for inputting a first control signal whose logic value transits, and a second transition signal when turned on / off by the first control signal and in an on state It is a circuit that outputs the output signal.

The second Muller C element with an inverter is
Similarly to the second Muller C element with an inverter of the first invention, a second positive input terminal for inputting the output signal output from the first gate circuit and a third transition signal for transitioning a logical value It has a second negative input terminal for inputting and a third output terminal for outputting the feedback signal, and when the output signal of the first gate circuit and the third transition signal have different logic values, The feedback signal having the same logical value as the output signal is output from the third output terminal, and the previous state is held when the output signal of the first gate circuit and the third transition signal have the same logical value. It is an element that does.

The second gate circuit has a third input terminal connected to the third output terminal of the second Muller C element with an inverter, and a fourth control signal for inputting a second control signal whose logic value transits. Input terminal and the second control signal to turn on and off to turn on when the second control signal has the second logic and output the fourth transition signal corresponding to the feedback signal. It is a circuit to do.

Further, the third gate circuit has a fifth input terminal connected to the third output terminal of the second Muller C element with an inverter, and a sixth input for inputting the second control signal. ON by the terminal and the second control signal,
When the second control signal is turned off and turned on when the second control signal has the first logic, the first control signal corresponding to the feedback signal is output to the second input terminal of the first gate circuit. Is a circuit having a fifth output terminal.

According to the second aspect of the invention, when the second control signal is input, the second and third gate circuits are turned on and off. When the second control signal has the second logic, the second gate circuit is turned on, and the fourth gate signal corresponding to the feedback signal is output.
Transition signal is output. When the second control signal has the first logic, the third gate circuit is turned on, and the first control signal corresponding to the feedback signal is output to the second input terminal of the first gate circuit. . Then, when the token is held by the first gate circuit and the second Muller C element with an inverter when the second control signal is input, the first control signal is output from the third gate circuit. .
A bus arbitration device or the like can be realized by using a new asynchronous transition signal control circuit that transfers such tokens.

A third aspect of the present invention is, in an arbitration device, a plurality of devices that output a second control signal and request a use when sharing a predetermined resource such as a bus, and the plurality of devices. The control means is provided with a plurality of transition signal control circuits of the second invention corresponding to the device.

In the control means, the output terminal for outputting the fourth transition signal of the transition signal control circuit of the preceding stage among the plurality of transition signal control circuits provided therein has the transition signal control circuit of the succeeding stage. The input terminal that is connected to the input terminal for inputting the first transition signal in and the input terminal that inputs the third transition signal in the transition signal control circuit in the previous stage outputs the second transition signal in the transition signal control circuit in the subsequent stage. When the plurality of transition signal control circuits are connected in cascade and connected to the output terminal and the second control signal output from the plurality of devices is input, use permission is provided for arbitration of these conflicts. The first control signal of 1 is output to perform arbitration between the devices.

In the third aspect of the invention, when the control means inputs the second control signals output from the plurality of devices, the first permission of use is arbitrated in order to arbitrate the competition between them.
The control signal is output to arbitrate between devices. As a result, shared use of predetermined resources such as buses can be smoothly performed.

A fourth invention is, in the arbitration device of the third invention, a Muller with an inverter which constitutes a transition signal control circuit.
By setting the initial value of the C element, the token exists in only one of the plurality of transition signal control circuits. As a result, even if one token is held in a certain transition signal control circuit, the token circulates between the transition signal control circuits, and any device has an opportunity to occupy a predetermined resource by arbitration. Given.

According to a fifth invention, in the arbitration device according to the fourth invention, the predetermined resource is a common bus, and only one of the plurality of devices connected to this common bus is the common bus. Arbitration is used to occupy the usage. As a result, even a device that is originally not suitable for asynchronous transition control can be targeted for bus arbitration.

[0053]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Explanation of Principle) (1) Configuration FIG. 2 is a principle explanatory view showing an embodiment of the present invention, in which elements common to those in the conventional FIGS. 7 and 8 are common. The reference numeral is attached. In FIG. 2, a plurality of blocks 40
-1, 40-2, 40-3, ... Are cascade-connected.

The block 40-1 is the same as the left block 20-1 in FIG.
And a delay element 21-1 having a delay time DELAY1. The Muller C element 10-1 with an inverter is
The request event Req (1) that is a transition signal is input to the positive input terminal, the response event Ack (2) that is a transition signal from the block 40-2 is input to the negative input terminal, and the response that is a transition signal is output from the output terminal. Event Ack (1) is output. The output terminal of the Muller C element 10-1 with an inverter has a delay element 2
1-1 is connected. The delay element 21-1 inputs the response event Ack (1) from the input terminal, and inputs this to the delay time D
Request event Re, which is a transition signal, delayed by ELAY1
Output q (2) from the output terminal to the block 40-2.

The block 40-2 corresponds to the right block 20-2 in FIG. 8, and includes the Muller C element 10-2 with an inverter and the delay element 21-2 having the delay time DELAY2 similar to those in FIG. An input OR gate 41-1 and
2-input AND gate 41-2 and switches 42-1 and 4-4
2-2 and.

The OR gate 41-1 has a first input terminal connected to the output terminal of the delay element 21-1, and a second input terminal grounded via the switch 42-1 (logic "L").
Side or the second input terminal of the AND gate 41-2, and the output terminal is connected to the positive input terminal of the Muller C element with inverter 10-2. The OR gate 41-1 opens the gate when the second input terminal connected to the switch 42-1 is, for example, “L”, and receives the request event Req (2) input to the first input terminal. Output the corresponding signal from the output terminal. The Muller C element with inverter 10-2 has a response event Ack which is a transition signal from the block 40-3.
(3) is input to the negative input terminal and the output terminal is switch 42
-1, 42-2 and the second input terminal of the AND gate 41-2.

The first input terminal of the AND gate 41-2 is the power supply VDD (logic "H") by the switch 42-2.
Side or the GND (logic "L") side, the second input terminal is connected to the output terminal of the Muller C element with inverter 10-2, and the second input terminal is connected to the switch 42-.
1 connects to the second input terminal of the OR gate 41-1. The output terminal of the AND gate 41-2 is connected to the delay element 21-2, and the switch 42-
Open when the first input terminal connected to 2 is "H",
When it is "L", it is closed, and when it is open, an output signal corresponding to the input signal of the second input terminal is output from the output terminal. The delay element 21-2 delays the output signal of the AND gate 41-2 by the delay time DELAY2, and outputs the request event Req (3) which is a transition signal to the block 40-3.

Similar to the block 40-1, the block 40-3 is composed of a Muller C element 10-3 with an inverter and a delay element 21-3 having a delay time DELAY3. In the Muller C element 10-3 with an inverter, the positive input terminal is connected to the output terminal of the delay element 21-2, the response event Ack (4) which is a transition signal is input from the negative input terminal, and the response event Ack (4) is input from the output terminal. Output 3). Delay element 21
-3 is an Muller C element 10-2 with an input terminal having an inverter
Is connected to the negative input terminal of Muller C element 10-3 with an inverter and the response event Ack (3) input from the input terminal is delayed by the delay time DELAY3 to output the request event Req (4). It has become.

For example, in the block 40-2, the switch 42-1 is connected to the GND side to connect the OR gate 41-1.
Open, connect switch 42-2 to the power supply VDD side, and
If the ND gate 41-2 is opened, the right block 20 in FIG.
Same as -2. (2) Roles of the switches 42-1 and 42-2

3A to 3C are timing explanatory diagrams of FIG. 2, where FIG. 3A shows the effect of the switch 42-1 and FIG. 3B shows the effect of the switch 42-2. FIG. 7C is a diagram showing the effect of using the switches 42-1 and 42-2 together.

In FIG. 3, the block N is composed of the logic circuit of the block 40-2 of FIG. 2, and the other blocks NK are the logic circuits of the blocks 40-1 and 40-3 of FIG. It is configured.

<Effect of Switch 42-1 in FIG. 3 (a)>
It is assumed that the switch 42-1 of the block 40-2 in FIG. 2 is connected to the output side of the Muller C element with inverter 10-2 and the switch 42-2 is connected to the power supply VDD side. In block 40-2, when the request event Req (2) from the delay element 21-1 reaches the OR gate 41-1, this O
R gate 41-1 and Muller C element with inverter 10-2
The request event Req (2) is latched in the loop constituted by. This state serves to limit the operation of the control circuit of the micropipeline of FIG.

That is, the event Ack (NK) (corresponding to the request event Req (2)) coming from the left block 40-1 is blocked one after another because the event Ack (NK) is locked in this block N. Event to N (eg Ac
Since k (NK)) approaches, control stops before that.
If this is compared with waves such as ocean waves and electromagnetic waves, it can be considered that the block N acts like a breakwater.

<Effect of Switch 42-2 in FIG. 3B>
If the switch 42-1 of the block 40-2 of FIG. 2 is connected to the output side of the Muller C element 10-2 with an inverter,
And the switch 42-2 is connected to the power supply VDD side
It is assumed that the D gate 41-2 is open. In this case, in the blocks 40-3, ... On the right side of the block N, even if the processing that has been delinquent progresses, the block N appears as a wave source to the right block 40-3, ... Event Ack (N) ( The request event Req (3) is generated continuously.

This time, the switch 42-1 of the block 40-2 of FIG. 2 is connected to the output side of the Muller C element 10-2 with an inverter, and the switch 42-2 is connected to the GND side to make the AND gate 41-2. Is closed. In this case, the response event Req is output by the AND gate 41-2.
Since (3) disappears, in the block on the right side of the block N, the events disappear one after another as the processing that has been delinquent progresses, but the generation and transition of the event to the right block in the block N. Means nothing will happen. This means the disappearance of waves when compared to waves such as ocean waves and electromagnetic waves.

<Switches 42-1 and 42- in FIG. 3 (c)
Effect of combined use of 2> By selectively using the switches 42-1 and 42-2 by switching the control signal, block N
Can also be used as a gate for transition events. In FIG. 3C, the block 40- of FIG.
2 switch 42-1 is Muller C element with inverter 10
-2 is connected to the output side, and the switch 42-2 is connected to the GND side and closed. In this case, the OR gate 41-
The event is locked in the loop composed of 1 and the Muller C element with inverter 10-2, and this event is not transmitted to the right block 40-3 by the effect of the switch 42-2. If there is no event in the left block 40-1, the wave will be isolated in the block N. This situation is a wave packet (Soliton) in terms of waves such as electromagnetic waves. Then, in this embodiment, the wave packet is promoted by the concept of the token, and the delivery is considered.

(3) Comparison with the conventional control circuit of FIG. 8 The second difference between the block 40-2 of FIG. 2 and the block 20-2 of FIG. 8 is as follows.

In the block 20-1 of FIG. 8, the control signal directly controls the logic circuit (not shown) to control the data flow (from the input data Din to the output data Dout). On the other hand, in the block 40-2 of FIG. 2, the control event Ack (2) or the like does not necessarily need to directly control the logic circuit. This means that the control is not necessarily required to transit because the token is held in the loop formed by the OR gate 41-1 and the Muller C element with inverter 10-2. On the contrary, in the conventional asynchronous transition signal control as shown in FIG. 8, since the circuit configuration that can hold the token is not provided, the control has to be transited. In this sense, the loop composed of the OR gate 41-1 and the Muller C element with inverter 10-2 corresponds to the latch circuit of the clock control logic. However, it is not just the data that is held, but the control event Ack (2).
Etc. are different.

(First Embodiment) (1) Configuration FIG. 1 is a configuration diagram of a transition signal control circuit showing a first embodiment of the present invention, which is common to the elements in FIG. 2 which is a principle explanatory diagram. Common elements are denoted by common reference numerals.

This transition signal control circuit is shown in FIG.
It can be used as one unit in the control circuit 32 in the bus arbitration device. Compared to the principle diagram of FIG. 2,
The transition signal control circuit includes blocks 40-1 and 4-4 of FIG.
0-2 has a combined configuration, and for example, when a device 30-1, ... Of FIG. 10 outputs a device request signal Reg, after performing necessary arbitration, a device permission signal Gr
is a circuit for outputting ant to the device 30-1 ,.

In FIG. 1, the first Muller with an inverter
In the C element 10-1, the request event ReqIn that is the first transition signal is input to the first positive input terminal, and the feedback signal S that is the transition signal is input to the second negative input terminal. From the output terminal of the, the response event AckO which is the second transition signal
Output ut. The first input terminal of the first gate circuit (for example, a 2-input OR gate) 41-1 is connected to the first output terminal of the Muller C element with inverter 10-1, and the second input terminal is The device permission signal Grant, which is the first control signal, is input, and the second output terminal is connected to the second positive input terminal of the second Muller C element with inverter 10-2. The Muller C element with inverter 10-2 is
The response event AckIn, which is the third transition signal, is input to the second negative input terminal, and the feedback signal S is output from the third output terminal.

Third Muller C Element 10-2 with Inverter
Is connected to the first negative input terminal of the Muller C element with inverter 10-1 and the third input terminal and the third input terminal of the second gate circuit (for example, 2-input AND gate) 41-2. The fifth input terminal of the gate circuit (for example, a 2-input AND gate) 41-3 is connected. AN
The D gate 41-2 receives the second control signal (for example, the device request signal Req from the device) at the fourth input terminal, and the request event ReqOut which is the fourth transition signal from the fourth output terminal. Is output. AND gate 41-3
Receives the device request signal Req, which is the second control signal, at the sixth input terminal, and outputs the device permission signal Grant, which is the first control signal, from the fifth output terminal. Is fed back to the second input terminal of the OR gate 41-1 and applied to the device.

In the transition signal control circuit of FIG. 1, the OR of FIG.
The loop composed of the gate 41-1 and the Muller C element with inverter 10-2 is the Muller C element with inverter 10-
2 and an OR gate 41-1 and an AND gate 41-3.

OR gate 41-1 inserted between loops
As long as the device enable signal Grant is output from the AND gate 41-3 even after the request event ReqIn is withdrawn and as a result, the Muller C element with inverter 10-1 withdraws the output of the response event AckOut, the token is still output. It is provided to maintain. However, when the device request signal Req is not output from any device, the feedback signal S output from the Muller C element with inverter 10-2 passes through the AND gate 41-2 and a request event is output from the AND gate 41-2. ReqOut is output and at the same time,
The AND gate 41-3 does not output the device permission signal Grant, the loop is released, and as a result, the token is handed to the next block.

(2) Operation FIG. 4 is a timing waveform chart showing the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG. When the input request event ReqIn occurs, the output response event AckO of the Muller C element 10-1 with an inverter is linked by the link L1.
ut occurs. The output response event AckOut is the OR gate 41-1, the Muller C element with inverter 10-2, and A.
An output request event ReqOut is generated by the link L2 via the ND gate 41-3. AND gate 41-2
Are provided to secure the delay time (for example, DELAY2) in FIG. If the delay time DELAY2 is not secured, the input response event AckIn is immediately output by the link L3, and there is a risk of conflict with the output request event ReqOut, so this is prevented by the AND gate 41-2.

Output request event after delay time DELAY2
ReqOut disappears by link L6. The disappearance of the output request event ReqOut leads to the disappearance of the input response event AckIn via the link L7. On the other hand, output response event Ac
The occurrence of kOut leads to the disappearance of the input request event ReqIn after a certain delay time (eg, DELAY1) by the link L4, and this disappearance is caused by the output response event by the link L5.
Guide the disappearance of AckOut.

In the operation of the transition signal control circuit of FIG.
Whether or not you have a token is important. If the token is not held, that is, the return signal S that is an event
If the device request signal Re
Even if q is output, the AND gate 41-3 does not output the device permission signal Grant to the device, and the standby state of the device continues.

(3) Effects The first embodiment has the following effects (i) and (ii). (I) According to the present embodiment, it is possible to configure a control event latch circuit that is not provided in the conventional asynchronous transition signal control circuit. The transition signal control circuit in FIG. 1 is based on the idea that an event does not directly control a logic circuit, but transitions control by passing a token (feedback signal S). In this sense, the device request signal Req of Fig. 1
The device grant signal Grant can be thought of as a signal that controls an event.

(Ii) The transition signal control circuit of FIG. 1 can be applied to various devices and circuits such as a bus arbitration device.

(Second Embodiment) (1) Configuration FIG. 5 is a configuration diagram of a bus arbitration device showing a second embodiment of the present invention, showing a transition signal control circuit of the first embodiment. 1 and elements common to those in FIG. 10 showing the conventional bus arbitration device are designated by common reference numerals.

This bus arbitration device has a predetermined resource (for example, a common bus) 31, and a plurality N (N is an arbitrary positive integer of 2 or more) of devices 30-to share this resource. 1 to 30-N are connected. Each device 30
-1 to 30-N are composed of, for example, those suitable for asynchronous transition control such as a DMA controller and timer, or those which are originally unsuitable for asynchronous transition control, and are device request signals Req1 which are second control signals. ~ ReqN respectively, and device grant signals Grant1 to GrantN
Has a function of inputting each.

A control means for executing arbitration for selecting occupation of the common bus 31 is connected to these devices 30-1 to 30-N. The control means has a plurality N of transition signal control circuits 50-1 to 50-N configured by the transition signal control circuit of FIG. 1, which are connected in a ring shape, and each transition signal control circuit 50-1. ˜50-N controls the arbitration of each device 30-1 to 30-N.

Each of the control circuits 50-1 to 50-N has terminals for input request events ReqIn1 to ReqInN, terminals for output response events AckOut1 to AckOutN, terminals for input response events AckIn1 to AckInN, and output request event Re.
A certain output request event with qOut1 to ReqOutN terminals
The terminal of ReqOut is cyclically connected to the terminal of the input request event ReqIn of the next transition signal control circuit, and the terminal of its output response event AckOut is cyclically connected to the terminal of the input response event AckIn of the preceding transition signal control circuit. As a result, even if one token is held in a certain transition signal control circuit (one of 50-1 to 50-N), the token is rotated counterclockwise in FIG. 5, for example, in the transition signal control circuit 50-. 1-50-N
The transition signal control circuits 50-1 to 50-N provide an opportunity to occupy the common bus 31 in any of the devices 30-1 to 30-N.

Here, the transition signal control circuits 50-1 to 50-50
In order to give the token to only one transition signal control circuit of -N and not to give the token to the other, for example, each transition signal control circuit 50-1 to 50-N is configured to have an initial state. do it.

For example, in the Muller C element with an inverter shown in FIG. 7, the reset signal Re is provided on the feedback line of the OR gate 15.
terminal of set and negative logic AND gate with this as input,
Alternatively, by adding a terminal of the set signal Set and a positive logic OR gate for inputting the terminal, it is possible to easily configure a Muller C element with an inverter having a reset or a set. Other configuration examples are shown in FIGS. 6 (a) and 6 (b).

FIGS. 6A and 6B are explanatory views of a Muller C element with an inverter having a set terminal and a reset terminal showing a second embodiment of the present invention, and FIG. 6A is a logical symbol diagram. , And FIG. 7B are logic circuit diagrams, and elements common to those in FIG. 7 are designated by common reference numerals.

A Muller C element with an inverter 10A having a set terminal and a reset terminal shown in FIG. 6 includes an inverter 11 similar to that shown in FIG. 7 and two-input AND gates 12 to 14 shown in FIG.
3 input AND gates 12A to 14A provided in place of
4 provided in place of the 3-input OR gate 15 of FIG.
It is composed of an input OR gate 15A and an inverter 16 which inverts the reset signal Reset. With such a configuration, the Muller C element with inverter 10A can be set to the initial state by the reset signal Reset or the set signal Set.

Each of the transition signal control circuits 50-1 to 50-N shown in FIG. 5 is configured by using the Muller C element with an inverter with a reset or a set, or the Muller C element with an inverter with a set and a reset. if,
The token can be given only to one transition signal control circuit and not given to the other transition signal control circuit.

(2) Operation In the bus arbitration device of FIG. 5, a plurality of devices 30-
, 1 desire to use the common bus 31, and a plurality of device request signals Req 1, ... Are enabled.

At this time, if there is a transition signal control circuit (for example, 50-2) held by the token, the device 3
0-2 from the device request signal Req 2 is received and the transition signal control circuit 50-2 receives the device permission signal Grant.
2 is output. Other transition signal control circuits 50-1 and 50
Since −3, ... Does not hold the token, the device permission signals Grant 1, Grant 3, ... Are not output. Therefore, the device 30-2 occupies the common bus 31, and this occupancy continues until the device 30-2 withdraws the device request signal Req2. Device 30-2 receives device request signal Re
When q 2 is removed, the token circulates counterclockwise in FIG. 5 to the transition signal control circuit 50-3, ..., The device which first met the device request signal Req validates the device grant signal Grant. Output and become the next occupant of the shared bus 31.

(3) Effects In this embodiment, the transition signal control circuits 50-1 to 50-N are provided.
Since the asynchronous bus arbitration device was configured by combining
Even the devices 30-1, ... Not suitable for asynchronous transition control can be arbitrated.

(Usage Mode) The present invention is not limited to the above embodiment, and various modifications and usage modes are possible. Examples of this modification and use form include the following (a) and (b).

(A) The gates shown in FIGS. 1, 6 and 7 may be replaced with gate circuits other than those shown in the drawings.

(B) Although the bus arbitration device has been described with reference to FIG. 5, the transition signal control circuit and the like of FIG. 1 are also applied to the case of sharing a predetermined resource such as a computer other than the common bus 31. be able to.

[0095]

As described in detail above, according to the first and second aspects of the present invention, the transition signal control circuit is constructed using the Muller C element with the inverter, so that the conventional asynchronous transition signal control circuit is not provided. A control event latch circuit can be configured. This transition signal control circuit is based on the idea that an event does not directly control a logic circuit but rather makes a transition by passing a token.

According to the third to fifth inventions, an arbitration device such as an asynchronous bus can be constructed by combining a plurality of transition signal control circuits. Therefore, even a device that is originally not suitable for asynchronous transition control can be a target of arbitration.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a transition signal control circuit showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating the principle of the embodiment of the present invention.

FIG. 3 is a timing explanatory diagram of FIG. 2;

FIG. 4 is a timing waveform chart showing the operation of FIG.

FIG. 5 is a configuration diagram of a bus arbitration device showing a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of an Muller C element with an inverter having a set terminal and a reset terminal according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a conventional Muller C element with an inverter.

FIG. 8 is a conceptual diagram of a control circuit of a conventional micro pipeline.

9 is a timing waveform chart showing the operation of FIG.

FIG. 10 is a block diagram of a conventional bus arbitration device.

[Explanation of symbols]

10, 10-1, 10-2, 10A Mu with inverter
ller C element 11, 16 Inverters 12-14, 12A-14A, 41-2, 41-3
AND gates 15 and 15A OR gates 21-1 to 21-3 Delay elements 30-1 to 30-N device 31 Common bus 40-1 to 40-3 Block 41-1 OR gates 42-1 and 42-2 Switch 50- 1-50-N transition signal control circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B061 BB28 PP00 RR02                 5J056 AA04 BB58 CC00 CC05 CC14                       DD00 GG14 KK01

Claims (5)

[Claims] 1. A first positive input terminal for inputting a first transition signal having a logical value transition, a first negative input terminal for inputting a feedback signal having a logical value transition, and a second logical value transition. Of the first transition signal and the feedback signal have different logical values, the second transition signal having the same logical value as that of the first transition signal is output. A first Muller C element with an inverter, which outputs from the first output terminal and holds the previous state when the first transition signal and the feedback signal have the same logical value, and the first Muller C element with an inverter. A first input terminal for inputting the second transition signal output from the first output terminal of the second input terminal, a second input terminal for inputting a control signal, and an on state by turning on / off by the control signal. Sometimes the output signal corresponding to the second transition signal The outputs two
A second positive input terminal for inputting the output signal output from the gate circuit, a second negative input terminal for inputting a third transition signal having a logical value transition, and It has a third output terminal for outputting the feedback signal to the first negative input terminal of the first Muller C element with an inverter, and the output signal of the gate circuit and the third transition signal have different logical values. In the case of, the feedback signal having the same logical value as that of the output signal is output from the third output terminal, and when the output signal of the gate circuit and the third transition signal have the same logical value, the previous state is held. A second Muller C element with an inverter, and a transition signal control circuit. 2. A first positive input terminal for inputting a first transition signal having a logic value transition, a first negative input terminal for inputting a feedback signal having a logic value transition, and a second logic value transition. Of the first transition signal and the feedback signal have different logical values, the second transition signal having the same logical value as that of the first transition signal is output. A first Muller C element with an inverter, which outputs from the first output terminal and holds the previous state when the first transition signal and the feedback signal have the same logical value, and the first Muller C element with an inverter. Input terminal for inputting the second transition signal output from the first output terminal of the second input terminal, a second input terminal for inputting a first control signal having a logical value transition, and the first control When the signal is turned on and off and it is on, First to a second output terminal for outputting an output signal corresponding to a transition signal
Gate circuit, a second positive input terminal for inputting the output signal output from the first gate circuit, a second negative input terminal for inputting a third transition signal having a logical value transition, and the A third output terminal for outputting a feedback signal is provided, and when the output signal of the first gate circuit and the third transition signal have different logical values, the feedback signal having the same logical value as the output signal is provided. A second Muller C with an inverter, which outputs from the third output terminal and holds the previous state when the output signal of the first gate circuit and the third transition signal have the same logical value.
An element, a third input terminal connected to a third output terminal of the second Muller C element with an inverter, a fourth input terminal for inputting a second control signal whose logic value transits, and the second And a fourth output terminal for outputting a fourth transition signal corresponding to the feedback signal by being turned on and off by the control signal and being turned on when the second control signal has the second logic. A second gate circuit, a fifth input terminal connected to the third output terminal of the second Muller C element with an inverter, a sixth input terminal for inputting the second control signal, and the second Is turned on and off by the control signal of No. 1 to turn on when the second control signal has the first logic, and the first signal corresponding to the feedback signal is turned on.
A third gate circuit having a fifth output terminal for outputting the control signal of 1. to the second input terminal of the first gate circuit, and a transition signal control circuit. 3. A plurality of devices that respectively output a second control signal to request the use when sharing a predetermined resource, and a transition signal according to claim 2 corresponding to the plurality of devices. A plurality of control circuits are provided, and among the plurality of transition signal control circuits, the output terminal for outputting the fourth transition signal in the transition signal control circuit in the previous stage is the first transition in the transition signal control circuit in the subsequent stage. The input terminal for inputting a signal, and the input terminal for inputting the third transition signal in the transition signal control circuit in the previous stage are connected to the output terminal for outputting the second transition signal in the transition signal control circuit in the subsequent stage. hand,
When the plurality of transition signal control circuits are connected in cascade and the second control signal output from the plurality of devices is input, the first control signal for permitting the use is transmitted in order to arbitrate these conflicts. An arbitration device comprising: a control unit that outputs and arbitrates between the devices. 4. A configuration in which a token exists in only one of the plurality of transition signal control circuits by setting an initial value of a Muller C element with an inverter that constitutes the transition signal control circuit. The arbitration device according to claim 3, which is characterized in that. 5. The predetermined resource is a common bus, and only one device among a plurality of devices connected to the common bus performs arbitration to occupy the use of the common bus. The arbitration device according to claim 4.